Recent Content
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
MAX 10: Can an ASx1 RBF be written directly to internal CFM via on-chip flash Avalon-MM?
Hi, I am implementing an in-system self-update mechanism for an Intel MAX 10 FPGA (10M16SAU169I7G) and I would like to confirm the correct configuration image format for programming the internal CFM through logic running inside the FPGA. My setup Device: MAX 10 10M16SAU169I7G Current design already boots normally from internal flash Inside the running design, I receive a new FPGA image over UART I split the image into blocks, verify CRC, and then write the data into the internal CFM using the on-chip flash IP Avalon-MM data interface After the transfer is complete, I plan to power-cycle the board so the FPGA boots from the newly written image What I am currently doing I generate the update file using quartus_cpf from the .sof: ~.bat ''' quartus_cpf ^ --option=bitstream_compression=off ^ --configuration_mode=ASx1 ^ -c ^ input.sof ^ output_file_active_serial.rbf ''' Then I send this .rbf file to the FPGA and write it word-by-word into the internal CFM. My question Can a Raw Binary File (.rbf) generated from a MAX 10 .sof with --configuration_mode=ASx1 be written directly into the MAX 10 internal CFM through the on-chip flash Avalon-MM interface, and then be used successfully as a bootable configuration image after power cycle? Or, stated differently: Is the ASx1 RBF byte layout identical to the internal CFM configuration image layout expected by MAX 10? If not, what is the correct file format / conversion flow for self-updating the internal CFM from user logic? Should I be using RBF, POF, or another file/image format for this purpose? Is there any official Intel example or application note showing the correct way to write a new configuration image into MAX 10 CFM from inside the running FPGA design? Additional context I already reviewed: MAX 10 FPGA Configuration User Guide Remote System Upgrade in Intel MAX 10 Devices Using the MAX 10 User Flash Memory From the documentation, I understand that MAX 10 supports configuration from JTAG and internal flash, and that remote/dual configuration is supported. However, I could not find a clear statement confirming whether an ASx1-generated RBF is the correct binary image to write directly into CFM via Avalon-MM. My main concern is avoiding a situation where: the UART transfer is correct, the CFM write completes, but the FPGA does not boot afterwards because the file format/layout written into CFM is not the expected one. If anyone from Intel or anyone who has implemented MAX 10 self-update / remote update can clarify the correct image format and recommended flow, I would appreciate it. Thank you.JESD204B RX Link Never Achieves CGS at 12.8 Gbps on S10 ES (1SG280LU3F50E3VGS1, Quartus Pro 17.1)
Hi Team, I am using the Intel JESD204B RX Example Design on a Stratix 10 GX Engineering Sample FPGA (1SG280LU3F50E3VGS1, L-Tile) with Quartus Prime Pro 17.1.I have two JESD204B configurations using the same board, RTL, and hardware. Case 1 (Working):ADC Clock = 1228.8 MHz, Decimation = 6 Lane Rate = 8.192 Gbps REFCLK (Core/XCVR) = 409.6 MHz Link/Frame Clock = 204.8 MHz SYSREF = 6.4 MHz This configuration works correctly and the JESD link comes up successfully. Case 2 (Not Working): ADC Clock = 1280 MHz Decimation = 4 Lane Rate = 12.8 Gbps REFCLK (Core/XCVR) = 640 MHz Link/Frame Clock = 320 MHz SYSREF = 5 MHz The JESD204B parameters are identical in both cases: L = 4 M = 8 F = 4 S = 1 N = 16 NP = 16 K = 32 Subclass 1 In the failing case, the following status is observed: Core PLL Locked = Yes ADC PLL Locked (Register 0x056F = 0x80) rx_is_lockedtodata = 0xF rx_ready = 0x0F rx_cal_busy = 0 rx_analogreset = 0 rx_digitalreset = 0 jesd204_rx_link_ready = 1 jesd204_rx_link_valid = 0 The Debug Link Buffer outputs are always zero: jesd204_rx_dlb_kchar_data = 0 jesd204_rx_dlb_data_valid = 0 jesd204_rx_dlb_data = 0 jesd204_rx_dlb_disperr = 0 jesd204_rx_dlb_errdetect = 0 Therefore, no CGS (/K28.5/) characters are detected and the link never progresses beyond this point. I have verified the following: ADC SPI configuration is correct.SYSREF is present on both ADC and FPGA.Register 0x0120 is written with 0x1C and correctly reads back 0x18 after SYSREF capture.Register 0x056E is configured correctly for the 12.8 Gbps lane rate.Register 0x0201 is set correctly for decimation by 4.REFCLK, Link Clock, and Frame Clock frequencies are correct.Native PHY calibration completes successfully.No Quartus warnings are reported.The Intel example design is used without RTL modifications.I also tried lane swapping and RX polarity inversion, but the result was unchanged.This 12.8 Gbps configuration has never worked even once since the beginning, whereas the 8.192 Gbps configuration works reliably on the same hardware. Could you please advise: Is there any known limitation or errata for Stratix 10 ES (1SG280LU3F50E3VGS1 L-Tile) at 12.8 Gbps?Is any additional Native PHY or transceiver configuration required for 640 MHz reference clock and 12.8 Gbps lane rate?Are there any known issues in Quartus Prime Pro 17.1 related to JESD204B RX at this operating point?Any suggestions on additional debug steps would be greatly appreciated.
Why 390.625MHz clock to F-Tile Reference fequency
Hi, This question is regarding the Agilex 7 M-Series FPGA Development Kit. In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs. From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock. My questions are: 1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board? 2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application? 3. Are there any official reference designs that use this 390.625 MHz reference clock? I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit. Regards,
HPS First Boot Configuration for Agilex 7
Dear Community, I'm developing a design using Agilex 7 on Quartus Pro 24.2. I'm a bit confused on the parameter settings I need for the HPS (and its EMIF) and my Quartus project settings in order to have HPS-First boot (Called HPS Early Release in former Quartus versions). For that, I'd like to generate .core.rbf and .periph.rbf files. I tried generating the .rbf files in two different ways given below, none succeeded. #1) Having the below pfg command in a text file and sourcing it in my .qsf --convert --hps -o bitstream_compression=on output_files/ProjectName.sof output_files/ProjectName.rbf #2) Using the Programming File Generator tool of Quartus I can generate .sof programming file, but converting that to .rbf fails with the following error when I did either given above. "sof is incomplete. Hps is present but bootloader information is missing". When doing case #2, I even add a bootloader .hex file that I could find on Rocketboards' webpage. Could anyone support me to have an HPS-first boot on Agilex 7 ? Thanks in advance!VVP Protocol Converter Not work
Hello, I am looking for how to use the VVP protocol converter, by converting Altera Stream Video Lite to Avalon Streaming Video. I generate a simple pipeline with Protocol Converter to Frame Buffer on Cyclone 10 GX... Here's the settings of the converter, And the Register settings for this IP, For unknown reason, I am unable able to see the protocol converter ready to work by setting rx ready signal goes "high" on STP. Even when the tx side ready signal is OK. Readback the register, the mode is fine and the CTRL is bit 0 is set already.. What would be wrong on my settings? Please help. Thank you.Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs
Hello, I am developing a custom PCIe endpoint using the Agilex 7 R-Tile PIPE Direct interface. The PHY is provided by the R-Tile IP, while the LTSSM, Data Link Layer, and TLP/DLLP handling are implemented in soft RTL. Environment FPGA: Agilex 7 AGIB027R29A Quartus Prime Pro 24.3.0 Build 212 R-Tile PIPE Direct mode PCIe Gen3 x8 Custom soft LTSSM and Data Link Layer Linux host with a commercial PC/root complex The FPGA is configured before a host cold boot The endpoint is not currently visible in lspci In a successful Signal Tap capture: The LTSSM reaches Gen3 L0. The Data Link Layer reaches DL_ACTIVE. InitFC1 and InitFC2 for Posted, Non-Posted, and Completion traffic are exchanged. We observe valid incoming TLP traffic with a correct LCRC. The host sends a Message TLP that appears to decode as Set_Slot_Power_Limit. No subsequent Configuration Type 0 Read TLP or other expected enumeration TLP is observed. The link later returns from L0 to Recovery.RcvrLock. Our understanding is that Set_Slot_Power_Limit is a posted Message TLP and should not require a Completion TLP from the endpoint. The endpoint should only acknowledge successful reception at the Data Link Layer. Please correct us if this interpretation is wrong. Questions Is receiving Set_Slot_Power_Limit before the first Configuration Read a normal root-port enumeration sequence? Does the endpoint need to respond to this Message TLP in any way other than sending a Data Link Layer ACK? If the ACK DLLP has an incorrect sequence number, CRC, or timing, could the root port stop sending further TLPs and eventually force the link into Recovery? Are there any R-Tile PIPE Direct-specific status or control signals that must be handled before the host starts Configuration transactions? Are there recommended R-Tile debug signals for determining why the root port stops after this message? Could an incorrect Flow Control advertisement—especially Completion Header/Data credits—cause this behavior even if InitFC2 completes? Are there known PERST#, cold-boot, or FPGA-configuration timing requirements for enumeration when using PIPE Direct mode? We are currently capturing the following signals: LTSSM state Data Link Layer state InitFC1/InitFC2 and UpdateFC status Received TLP Fmt/Type and complete header Received TLP sequence number LCRC result ACK/NAK request and transmitted ACK/NAK sequence number Replay timer/replay status RX block lock, CDR lock, and lane numbers Raw 1024-bit PIPE RX block data Any guidance on the expected transaction sequence after Set_Slot_Power_Limit, or additional signals that should be captured, would be greatly appreciated. Thank you.
Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY
Hardware Intel Stratix 10 Development Kit E-Tile Native PHY IP Single SMA TX and RX channel SMA-to-SMA cable (50 Ω) Software Quartus Prime Pro 18.1 Intel Transceiver Toolkit Configuration PAM4 operation Line rate: 51 Gbps One TX channel connected directly to one RX channel through an SMA cable Design compiles successfully and programming is successful. Problems Encountered 1. PAM4 Eye Detection Failure Transceiver Toolkit reports: "PAM4 eye could not be detected, check lock status and run RX adaptation." 2. RX Adaptation Questions One-time adaptation completes successfully, but: Eye detection still fails. BER measurements do not produce a usable eye diagram. Questions: Should continuous adaptation be used instead? Is there a recommended adaptation sequence before running Eye Viewer? 3. Eye Diagram Parameters Undefined After running Eye Viewer: Eye Width = Undefined Eye Height = Undefined i.e. ratio = (0/0) The heatmap returns with full RED and no eye diagram. The eye diagram is not generated even though the receiver reports lock. 4. BER Test Issues I am unsure: How many bits are required before Eye Viewer can successfully generate a PAM4 heat map. Whether there is a minimum BER sample count required for a valid eye diagram at 51 Gbps. Whether insufficient captured bits can cause "Undefined" eye width/height. 5. TX Pattern Currently transmitting a repeating user-defined pattern, for example: .tx_parallel_data({20{40'b0, 40'h0F0F0F0F0F, 40'b0, 40'h0F0F0F0F0F}}) Questions: Is this pattern suitable for PAM4 eye measurements? Would PRBS13 or PRBS31 be required instead? 6. Signal Integrity Questions: Can a 50 cm SMA cable (Pasterneck PE3CA1035) reliably carry a 51 Gbps PAM4 signal? Is additional equalization or TX pre-emphasis typically required even for short SMA connections? 7. Transceiver Toolkit Configuration I would appreciate guidance on: Recommended Eye Viewer settings. Auto Sweep configuration. Vertical and horizontal ranges. TX FIR tap values. RX CTLE/DFE settings. Required number of bits before starting the eye scan. What are the common reasons for "PAM4 eye could not be detected" despite PLL/CDR lock? What checks should be performed before running Eye Viewer? PRBS as well as USER sequence, both generate complete RED heatmap, why? How many bits should be accumulated before generating an eye diagram at 51 Gbps? Are there recommended TX FIR, CTLE, and DFE settings for a direct SMA-to-SMA connection? Has anyone successfully generated a PAM4 eye using the Stratix 10 E-Tile Native PHY over SMA? If so, could you share the required configuration or debugging steps?Issue with MIPI CSI2 Encrypted IP File During Project Integration
Hi, I am working on a project where I have integrated two separate projects into a single top-level design. Project A includes the MIPI CSI2 IP and other related components. Project B contains the logic to process the output data generated by the MIPI CSI2 IP. When I compile both projects individually, they complete successfully without any errors. However, after instantiating both projects together in a single top-level wrapper, I encounter a compilation error originating from the generated encrypted file of the MIPI CSI2 IP. I have attached the error snapshot for your reference. Could you please help identify the possible cause of this issue? Is there any known limitation or configuration requirement when integrating the MIPI CSI2 IP with additional logic in the same top-level design? Thanks.
