Recent Content
Operating system kernel-level FPGA bridge communication
We are using a custom (Agilex 5) platform and need to access the FPGA bridges from the Linux kernel. We are unable to locate the corresponding device tree nodes or modifications required to access these memory-mapped regions. We're aware of the devmem2 package, but we want to access the FPGA from the kernel side without relying on it. Please guide us on how to configure the device tree and use kernel-level commands or interfaces to access the HPS-to-FPGA and Lightweight HPS-to-FPGA bridges. configuration from Linux. CONFIG_OF_RESOLVE y CONFIG_OF_OVERLAY y CONFIG_OF_CONFIGFS y CONFIG_FPGA_MGR_STRATIX10_SOC y CONFIG_FPGA_BRIDGE y CONFIG_FPGA_REGION y CONFIG_OF_FPGA_REGION y CONFIG_OVERLAY_FS y
Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[1]
Hello. Please, suggest how to resolve this error. Quartus 25.1, Cyclone V, Start Fitter. inout [3:0] HPS_DDR3_DQS_N, inout [3:0] HPS_DDR3_DQS_P, .memory_mem_dqs (HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n (HPS_DDR3_DQS_N), // .mem_dqs_n
Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi all, I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question: My Target FPGA: Intel MAX 10 (10M25DAF4817G). Reference Design: I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center) . The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1. My Experience: In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1 and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues. [Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available: What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1 as the known stable version for my device family?Is 25.1 (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue? Any insights would be greatly appreciated. Thank you.
Cyclone IV E – PLL Power Track Width Recommendation Clarification
Hi, I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil trace width for the PLL power supply routing. Due to space constraints on our PCB, we have routed the PLL supply net as follows: From the ferrite bead to the FPGA cutout: 20 mil trace width After the cutout region leading into the FPGA power pin area: reduced to 6 mil trace width My questions are: Is it acceptable to reduce the PLL power trace width from 20 mil to 6 mil after the cutout region? If not, what issues might arise due to this narrower trace? I have attached a snapshot from the guideline for reference. Requesting your comments and guidance on whether this implementation is safe or if the narrower section could cause problems with PLL performance. Thanks in advance!Help with BTS and .sof example files for Agilex 7 AGM039EA
I'm trying to program the .sof BTS examples files onto my Agilex 7 AGM039EA dev board (files are from AGM039FES installer package). I'm using Quartus 25.3 and the BTS is able to detect the board however when loading the .sof files, BTS mentions the .sof files were compiled using an older version and not able to complete programming. When I switch over to Quartus 24.3.1, the JTAG scan does not pick up my board (lists it as Unknown_434CC0DD) and the BTS GUI will not open because there is a FPGA mismatch. Any help on getting the correct files to work with the proper BTS for my FPGA board?
Cyclone5 SoC: U-Boot not detecting USB-HUB
Hello there, I'm working on a design on top of a Chameleon96 Board (CycloneV based), featuring a USB OTG Chip USB3300, and connected to it an USB 2513B Hub. My issue is that neither U-Boot or Linux are able to detect the USB Hub connected to the USB3300. This used to work with older U-Boot versions and are still working on my board, but I was not able to reproduce such behavior with up-to-date versions (cloned from https://github.com/altera-fpga/u-boot-socfpga and https://github.com/altera-fpga/linux-socfpga). The Chameleon96 has two GPIO pins to control the reset of the mentioned USB chips, with a fixed configuration on the USB 2513B (the I2C interface is not exposed). With my version (U-Boot 2025.07-gd4f268660a70-dirty and Linux 6.12.33-g3234b1ed8956), the USB OTG is detected and the hub registered with logs like the following: [ 0.883275] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 0.890619] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 0.898034] dwc2 ffb40000.usb: Configuration mismatch. dr_mode forced to host [ 0.905721] dwc2 ffb40000.usb: DWC OTG Controller [ 0.910454] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 0.917571] dwc2 ffb40000.usb: irq 32, io mem 0xffb40000 [ 0.923324] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, b2 [ 0.931588] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 0.938800] usb usb1: Product: DWC OTG Controller [ 0.943509] usb usb1: Manufacturer: Linux 6.12.33-g3234b1ed8956 dwc2_hsotg [ 0.950362] usb usb1: SerialNumber: ffb40000.usb [ 0.955682] hub 1-0:1.0: USB hub found [ 0.959499] hub 1-0:1.0: 1 port detected but the connected USB hub never shows up. Similarly 'usb start' from the U-Boot prompt just shows something called U-Boot Root Hub: => usb start starting USB... USB DWC2 Bus usb@ffb40000: 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Older u-boot versions (and linux) are able to detect the USB hub after 'usb start'. In this case, the root hub is named DWT OTC RootHub, and I don't know if this is just a change of naming somewhere or something wrong is also happening while detecting the USB3300 Hub: SOCFPGA_CHAMELEON96 # usb start (Re)start USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_CHAMELEON96 # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | DWC OTG RootHub | +-2 Hub (480 Mb/s, 2mA) the linux kernel (4.1.33-ltsi-altera) is also able to detect the USB Hub as can be seen in these logs: [ 0.913203] ffb40000.usb supply vusb_d not found, using dummy regulator [ 0.919864] ffb40000.usb supply vusb_a not found, using dummy regulator [ 0.957196] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRM [ 1.817295] dwc2 ffb40000.usb: DWC OTG Controller [ 1.822011] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.829076] dwc2 ffb40000.usb: irq 44, io mem 0x00000000 [ 1.834617] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.841394] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 1.848596] usb usb1: Product: DWC OTG Controller [ 1.853282] usb usb1: Manufacturer: Linux 4.1.33-ltsi-altera-svn260 dwc2_hsog [ 1.860481] usb usb1: SerialNumber: ffb40000.usb [ 1.865670] hub 1-0:1.0: USB hub found [ 1.869457] hub 1-0:1.0: 1 port detected ... [ 2.367190] usb 1-1: new high-speed USB device number 2 using dwc2 [ 2.577385] usb 1-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.584069] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.591939] hub 1-1:1.0: USB hub found [ 2.595782] hub 1-1:1.0: 3 ports detected I think I've ported all the needed configuration to the u-boot sources (basically resetting the USB hub using the attached GPIOs, and I also tried the reset sequence manually from U-Boot with the gpio command) and I'm not able to figure out how to find where the issue might be. I've forked u-boot sources here: https://github.com/teiram/u-boot-socfpga/, using the socfpga_chameleon96_defconfig configuration. Could you please support me in order to troubleshoot what the issue might be? I tried to backport my changes to some different branches on u-boot-socpfga but got the same results or even worse (no boot at all). I also have sources for a working U-Boot but they are quite old and the configuration changed sensibly since. I think all the needed options are set. Cheers, Manuel
Error(23098) when using IPM_IOPLL on Agliex 7
I am trying to use the IPM_IOPLL in my project on the Intel Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) but whenever i use it i get the following error: Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_0_2 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted. Info(20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info(20274): Successfully committed planned database. Error: ERROR: An error occurred during automatic periphery placement Error: Quartus Prime Fitter was unsuccessful. 3 errors, 0 warnings Error: Peak virtual memory: 9478 megabytes Error: Processing ended: Tue Feb 24 11:20:55 2026 Error: Elapsed time: 00:01:22 Error: System process ID: 177973 Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 109 warnings When i use an IOPLL generate from platform designer the project compiles successfully. The code for the IPM_IOPLL is below: inst_mac_iopll : IPM_IOPLL generic map( REFERENCE_CLOCK_FREQUENCY => "100.0 MHz", N_CNT => 1, M_CNT => 10, C0_CNT => 8, C1_CNT => 16, C2_CNT => 32, OPERATION_MODE => "direct", PLL_SIM_MODEL => "Agilex 7 (I-Series)" ) port map( refclk => clk, -- 100MHz input reset => g_rst_d1, outclk0 => i_mac_clk, -- 125MHz output outclk1 => mac_half_clk, -- 62.5MHz output outclk2 => i_ipb_clk, -- 31.25MHz output locked => i_locked ); I am not sure what is causing this error. I am using Quartus Prime Pro 24.3.1 with the DK-SI-AGI040FES board. Thanks
