Recent Content
Fitter stalls on "Advanced Physical Optimization" on Windows 10
We are reluctantly moving from Windows 7 to Windows 10. I have a project that compiles just fine on a Windows 7 Pro machine with an Intel Core i7-3930K CPU using Quartus 19.1 Lite. I copied the project to a new Windows 10 Pro machine with a Ryzen Threadripper PRO 3995WX processor. Also copied the Quartus 19.1 install files and it installed with no problem. But when I try to compile, it stalls during fitting at a line: Info (14951): The Fitter is using Advanced Physical Optimization. On Windows 7, the whole compile takes 11 minutes. I let it run for two hours on Windows 10 and it just sits there. I limited the number of parallel cores to 6. That did not help. I upgraded to Quartus 24.1 Lite (the last one to support Windows 10) and that did not help. If I disable "Advanced Physical Optimization" in the Advanced Fitter options, the compile completes. But this is bizarre. Why would the exact same project with the exact same version of Quartus compile fine on Windows 7 but not on Windows 10?
Unique ID registers in Cyclone V
Hello everyone, I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side. Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as: - A hardware serial number - A unique device ID - OTP (One-Time Programmable) fuses with unique identifiers - Any factory-programmed identification values What I've Tried: I've reviewed the Cyclone V documentation but haven't found clear information about unique ID registers accessible from the HPS side (unlike some other ARM SoCs that have dedicated UID registers). However I have seen Unique ID present in the FPGA side (https://www.intel.com/content/www/us/en/docs/programmable/683336/20-3/cores-user-guide.html), but this is not useful for my use case. Any guidance, documentation references, or code examples would be greatly appreciated! Thanks in advance!
Error creating Nios II Application and BSP from Template
I got this error while trying to create a Nios II Application and BSP from Template from a .sopcinfo file. Any hints? Thank you ! Executing: ./create-this-bsp --cpu-name nios2_cpu --no-make (F:\fsoc_lab\software\d_bsp) 2 [main] bash (7548) C:\intelfpga_lite\18.1\quartus\bin64\cygwin\bin\bash.exe: *** fatal error - cygheap base mismatch detected - 0xECD408/0x10ED408. This problem is probably due to using incompatible versions of the cygwin DLL. Search for cygwin1.dll using the Windows Start->Find/Search facility and delete all but the most recent version. The most recent version *should* reside in x:\cygwin\bin, where 'x' is the drive on which you have installed the cygwin distribution. Rebooting is also suggested if you are unable to find another cygwin DLL.MAX 10. No 3.0 V Schmitt Trigger I/O standard
For some reason Max 10 doesn't support 3.0 V Schmitt Trigger I/O standard. Of course, using 3.3V I/O standard would work as well. But then Quartus would complain and would issue a fatal error if there other pins in the same bank are configured as 3.0 V LVTTL or 3.0 V LVCMOS. I guess I could change all the pins in the same bank to 3.3V, instead of 3.0V. But I don't want to do that because some features are supported on 3.0V but not on 3.3V I/O standard. E.g., configurable slew rate is not available for 3.3V I/O standard. It would seems that something doesn't make much sense. Not sure if it's a real hardware issue or just a Quartus limitation. So the question is how I can enable both the Schmitt Trigger and features such as slew rate control in the same I/O bank. I don't need this in the same pin, at least not in this case,. Or the only workaround is to use something like 2.5V I/O standard? Didn't try, but according to the datasheet 2.5V I/O standard does support both features. Thanks,
Setup slack violations?
Hi, I have a design implemented in a Cyclone 10LP device, but I am struggling a bit with the Timing Analyzer. I am using Quartus Prime Lite edition 24.1. The setup-slack is violated for a number of paths, but I need some help interpreting the waveform shown in the attachment. And, looking at the path in Technology Map viewer I also struggle on how to improve the timing. How can I attack the issue? A pointer to relevant documentation is highly appreciated
EDA_MAINTAIN_DESIGN_HIERARCHY obsolete?
Hi Community, I'm using Quartus Pro 25.1.1 and for simulation need to enable EDA_MAINTAIN_DESIGN_HIERARCHY during eda netlist writing. I wasn't able to find it somewhere in the settings and setting it via global assignment in qsf leads to this: # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation" # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation" Does anyone know how to turn the hierarchy preservation on? Thanks in advance!
Power Rating Required for RZQ Resistor on Cyclone V SE
Hi, I need to include the 100R resistor we are using connected to RZQ pin D21 on the 484 ball package. Can anyone tell me what the maximum current I would realistically experience. If I just assumed that the resistor connected directly from a voltage rail through the resistor to ground it would make my resistor too large, physically, thus the need for realistic figures please. Thanks.
