Recent Content
M9K utilization is different for the same RAM IP for two different projects.
I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects. The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks. For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below: The settings for the RAM-IP are as shown in the image below: Quartus Tool Version : Quartus 18.1 Standard FPGA Device : MAX-10 10M50DAF256I7G Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks. Thank you, Akhilesh.
AMD/ XQVC1902 Xilinx Versal AI Core Inventory Availability
Hi Everyone, I’m reaching out regarding some available XQVC1902 inventory in sealed OEM packaging. I wanted to see if the 1902 family is currently relevant to any active designs or procurement efforts. Here is a brief description: Available Device: AMD/Xilinx Versal AI Core Device: XQVC1902-IVIQA1596-5241 Quantity Available: 63 pcs Condition: New & unused Packaging: Original trays / sealed packaging Traceability labels and Data Matrix codes present We are currently looking to identify qualified companies that may have evaluation, development, integration, or program-related interest in this device family. Additional information can be provided upon request, including: photos, packaging details, traceability information, Data Matrix examples, and supporting documentation. I understand these are highly specialized devices, so I would appreciate any feedback regarding potential fit or interest within your organization. Thank you Everyone for your time and consideration. RK
timing impact
I performed compilation on two separate servers(A and B)using identical RTL source code and identical project configurations; however, the resulting timing violations differ between the two builds, with one server A has less timing violations. Does a server with more CPU cores, higher clock speed and bigger RAM help improve project timing results?
Quartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?
Mac internal loopback F-Tile, Quartus 25.2
Hi all, I have Quartus 25.2 and I'm looking to run some tests in loopback mode without having any physical hardware connected. I have Reflexv2 FPGA Card. Can you guide me which IP from quartus should i choose to run loopback for testing purposes? I want only to run internal loopback, without card connection. Best Regards, Przemyslaw PajakGTS JESD204C IP Evaluation Mode not working
Using Quartus Pro 25.3 I can't generate time limited sof for GTS JESD204C. I have reviewed Licensing 'know-How' Guild. I found and corrected an issue with the LM_LICENSE_FILE variable. I have verified that IP Evaluation Mode is enabled within Quartus. I'm working with the GTS JESD204C Example Design generated with Platform Designer selecting the "Agilex 5 E-Series 065b Premium Development Kit". I'm also using the GTS JESD204C IP Design Example User Guild. When I compile the design I get Message ID 23714 "Can not generate programming files", 115005 "Unlicensed IP: JESD204C (6AF7 0146)", and 115004 "Unlicensed encrypted design file". At this time, I'm only interested in evaluating the GTS JESD204C IP. Does this IP support evaluation mode? If so, any suggestions as to why Quartus Pro will not generate time-limited sof files?
