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Configurable transceiver enable
I need to enable transceiver channels in groups based on a board parameter read during board start-up. If the parameter is '0', channels 1 and 2 are enabled, channels 3 and 4 are disabled. If the parameter is '1', channels 3 and 4 are enabled and 1 and 2 are disabled. I want to explicitly disable the unused channels to save power and prevent them from driving outputs. The only way to disable channels that I've figured out is to hold the input reset of the reset controller asserted. Then I'll need 2 reset controllers, one for each group of 2 channels. I'll also need 2 PLLs since they are interconnected with the reset controller. Is this the way to do it or is there a better way? Best regards, Julia
Manual checksum verification of CFM0
I am working on some post-build scripting for generating firmware update programming files for the Max 10 series FPGA. My goal is to generate 2 separate files: POF file, for use with USB Blaster. Proprietary file, for use through a different communication channel. The POF file is easy; the file is basically auto-generated when you compile in Quartus. When loading the POF into the Quartus programmer software, it shows "Checksum" and "Usercode Checksum". The usercode checksum can also be found in the RPT file. So I have used my post-build scripting to make a copy of the POF file, with the usercode checksum appended to the POF filename. That is all working great and goal #1 is satisfied. I have been working on the proprietary file. In this case, I would be storing something that amounts to the raw data that will end up written to the CFM0 section of the FPGA. To get the raw data, I used quartus_cpf to generate RPD files from the compiled SOF file. The raw data can then make its way into the FPGA's CFM0 section through undisclosed means other than USB-Blaster. All of that is OK, but the problem I have is that I wish to use the SAME usercode checksum as the POF file for consistency, and I have not been able to figure out how to correctly calculate that. One thing that I did where I got close was, I added this argument to the quartus_cpf command when generating the MAP file: -o memory_map_file=on The MAP file generated shows a totally different checksum. However, when I do a simple 32-bit checksum on the RPD data (just adding all 32-bit words of the file and coming to a 32-bit result), it DOES exactly match the checksum in the MAP file. In summary: I want the consistency between one of the POF's checksums shown in Quartus Programmer, vs. what I can calculate from the raw RPD data. Since both methods of programming the FPGA should produce identical results, I want to be able to have the same checksum in both methods. How may I correctly use the RPD data to calculate the same checksum shown in Quartus programmer when loading the POF file?Quartus Prime Lite 25.1 License Error - "Unable to checkout a license" (SALT_LICENSE_SERVER)
Hi everyone, I'm trying to run a simulation in Quartus Prime Lite 25.1 on Windows, but it fails right away with this error: "Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER) is set correctly" Does anyone had the same problem? And how can i fix it? Thanks!
F-Tile Ethernet Hard IP Design Example - Testbench
I have a question regarding this Ftile Ethernet hard IP example Design. I am able to generate this example design for 400gbe. I am able to load this design (sof) to MA2700Kit. I was able to run tcl script and internal loopback test was successful. I was also able to run testbench basic_avl_tb_top.sv and VSIM run was successful. I have following questions and areas where I need help. At line 144 and 145 in basic_avl_tb_top.sv I can see that Tx outputs are assigned Rx input pins. I would like to understand reason for doing this? I mean shouldn’t the RX lines driven by tasks/function to simulate incoming packets over the ethernet link? I want to modify the testbench to simulate Receiving of a particular 98 byte ethernet frame, and check how mac segmented interface is behaving to communicate this frame; So i can write my custom RTL block to receive it properly. I need help developing tasks/function to simulate incoming packets over the ethernet link. Thank youF-tile-ethernet-hard-ip TX/RX MAC Segmented Client Interface
https://docs.altera.com/r/docs/683023/25.1.1/f-tile-ethernet-hard-ip-user-guide/tx-mac-segmented-client-interface "i_tx_mac_inframe" signal is explained as " Indicates valid data in each segment for specific rate. Along with the previous segment's inframe signal, this signal indicates the SOP and EOP location." i dont understand the underlined part of explanation. how does i_tx_mac_inframe indicates start of packer (SOP) and end of packet (EOP). can someone please elaborate on this with a couple of examples also another question is how to interpret i_tx_mac_data signals if i_tx_mac_valid == 1'b1 and i_tx_mac_inframe [15:0] == 16'h0 ?
F-tile 10GBASE-R firecode FEC IP (Agilex 7)
Hi! We require to support 10GBASE-R clause 74 (firecode) FEC + PCS. This option isn't available in the Agile 7 F-Tile hard FEC IP. It is available for 25G rates, but we need it specifically for 10G. Our application doesn't require a MAC, in other rates we are to use PCS/MII mode It seems the only way forward is a soft firecode FEC + PCS, which would could connect to our FGT in PMA direct mode. Is this correct, and does altera provide an equivalent soft IP in order to support this configuration?
Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5
Hello, According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Center), the RMS jitter integrated from 10 kHz – 20 MHz, including spurs, is indicated as 522fs (maximum value). We are using in our design a 156.25MHz clock (AX3DAF1-156.2500 from abracon), and the measured jitter is ~1ps currently. We would like to know if this specification is for specific performances or if it’s a strict specification. (in our case, it’ll be for a 1G operation) Thanks, Best RegardsError (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10
I am trying SSS communication with Intel® Cyclone® 10 LP FPGA Evaluation Board. https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/10-lp-evaluation-kit.html The project is from https://www.intel.com/content/www/us/en/design-example/714923/cyclone-10-lp-nios-ii-simple-socket-server-for-c10-lp.html? Then I got these two errors: Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10min_trial_edition (AE7C_0014) in current license. Error (10003): Can't open encrypted VHDL or Verilog HDL file "C:/Work/FPGA/C10_SSS/db/ip/q_sys/submodules/sll_ca_hbc_t001_top_enc.v" -- current license file does not contain a valid license for encrypted file I can compile other projects successfully. Also updated all license (University Program), tried 17.1, 19.1, 22.1std, nothing helped There is similar post here (@AR_A_Intel) https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-292014-Can-t-find-valid-feature-line-for-core-VT-User-FPGA/td-p/1262329 It seems I need third-party license (if same reason), but no idea how/where to get it.... Very appreciate if anybody could help!!
NIOS V: Systick based timeouts not available when using internal timer
Hello, We are using Quartus 25.1 Standard. I came across something, which I would consider a but in the BSP generated HAL files, or at least a major limitation in the usage of NIOS V. System Setup: NIOS V + JTAG UART NIOS V in internal Timer as Sys_clk_timer BSP Setting: Problems: The JTAG UART drivers have a timeout functionality based on the systick interrupt to avoid getting stuck, in case there is not JTAG UART connected, so the internal buffer fills up. --> see altera_avalon_jtag_uart_timeout() This used to work fine with: NIOS II Setup (using external Timer) NIOS V Setup with external Timer block as sys_clk_timer But when using the NIOS V internal as sys_clk_timer the JTAG UART timeout does not trigger and when calling alt_printf it gets stuck in altera_avalon_jtag_uart_write /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) Analysis When I check the initialization routine of the JTAG UART altera_avalon_jtag_uart_init by stepping through with the debugger, I realize, the alarm is not setup: /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) This is because the alt_ticks_per_second() returns 0 During the main() function alt_ticks_per_second() is correctly set to 10 (which is my setting from the BSP) The root cause, is the initialization order in alt_sys_init() within the generated alt_sys_init.c file: void alt_sys_init( void ) { ALTERA_AVALON_TIMER_INIT ( NIOS_SUBSYSTEM_TIMER_0, nios_subsystem_timer_0); ALTERA_AVALON_JTAG_UART_INIT ( NIOS_SUBSYSTEM_JTAG_UART_0, nios_subsystem_jtag_uart_0); ALTERA_AVALON_SPI_INIT ( NSC3_SUBSYSTEM_0_ADC_SPI, nsc3_subsystem_0_adc_spi); ALTERA_AVALON_SYSID_QSYS_INIT ( NIOS_SUBSYSTEM_SYSID_NIOS, nios_subsystem_sysid_nios); ALTERA_AVALON_UART_INIT ( NIOS_SUBSYSTEM_UART_IP, nios_subsystem_uart_ip); INTEL_NIOSV_M_INIT ( NIOS_SUBSYSTEM_INTEL_NIOSV_M_0, nios_subsystem_intel_niosv_m_0); } _alt_tick_rate is initalized to 0 per default and gets set duing alt_sysclk_init(), called from the INTEL_NIOSV_M_INIT Macro As seen above. The INTEL_NIOSV_M_INIT Macro is called last within alt_sys_init. Hence all other modules do see _alt_tick_rate = 0. Hence assume there is no sys tick timer present. Hence all sys tick based alarms are disabled. NOTE: The ALTERA_AVALON_TIMER_INIT Macro is called first. Which appears to be correct IMHO, so the Timer module works as sys tick timer @ Altera: Please advise on this issue. Is there any possibility to change the alt_sys_init initialization order? best regards Fabian
