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USB Blaster III Pin connection
Hi, Onboard_USB3_Instructions_11Dec24.pdf document pinout for FT4232 Connection, some pins are not matching with AGILEX™ 5 FPGA E-SERIES 065B MODULAR DEVELOPMENT KIT - SOM schematic. Please let me know which one we need to fallow. Example ENABLE Pin. And LED Connections i can fallow as per below table ? is there any proven reference with LEDs ? Regards, Manu
How to create a new component that instantiates a IP variant in PD?
Hi, I want to connect an Avalon stream multiplexer to an Avalon S2MM Memory FIFO using a dual clock FIFO that has different input and output width. My data packet from the Avalon stream multiplexer is 128-bit and the S2MM Memory FIFO only supports 32-bit data when it is configured S2MM (I want to stream the data packet to HPS). Since the current Avalon stream FIFO dual clock does not support misaligned input and output width, I created a custom Avalon Stream DC FIFO the wraps a DCFIFO (128->32) IP. I wanted to use the Component Editor in Platform Designer to make the wrapped AVS DCFIFO an custom IP so I can instantiate it in Platform Designer. Here is my question, can I add the *.ip IP variant file along the HDL top-level file into the Component Editor file list to create the IP? If not, what are some alternate approaches to make instantiating HDL + IP comb in Platform designer happen? Thanks,
Quartus Assembler-only run after updating ROM .mif — should .sof/.pof checksum change?
Hello, I have a question about Quartus output files and checksums when only the Assembler is re-run. 1) Run a full compile once (Analysis & Synthesis + Fitter/Place & Route). 2) Modify a *.mif file that is used as the initialization file for a Quartus IP: “ROM: 1-PORT”. 3) Without re-running Analysis & Synthesis or the Fitter, run: 4) Processing → Start → Start Assembler 5) to regenerate the .sof and .pof files. A customer asked whether the checksum of the generated .sof/.pof should remain unchanged because the logic is not re-synthesized and the design is not re-fitted. However, in my repeated tests, the checksum of the .sof/.pof changes every time the contents of the .mif file change. Could you please confirm whether this behavior is expected? In other words, does the Assembler incorporate the updated memory initialization data into the programming files (thus changing the file contents/checksum), even though A&S and Fitter are not re-run? Any clarification or recommended flow for updating ROM init contents would be appreciated. Best regards,
Quartus Prime Pro 25.1 Crashes Randomly
I’ve been having trouble compiling projects with Quartus Prime Pro version 25.1 for several days. In an unpredictable manner, Quartus stops the compilation or freezes at a certain point—it can happen at the beginning, during synthesis, when the fitter starts, or during timing analysis. I’ve carried out extensive testing. I’ve tried reinstalling the program several times, and it’s true that right after installation, several successful compilations can be achieved; however, after around the fifth one, it usually starts failing and won’t compile anymore. The message window during compilation doesn’t provide any details about the error. I’ve also tried installing the newest version, but it behaves similarly. After a few attempts, I noticed that at the exact moment of the crash, the program generates a file called serv_req_info.txt, which I’ve attached. I’ve formatted my computer and updated to the latest version of Windows, and even replaced the internal SSD, but nothing has solved the issue. I’d appreciate any help in finding the cause of the problem.Cyclone5 SoC: U-Boot not detecting USB-HUB
Hello there, I'm working on a design on top of a Chameleon96 Board (CycloneV based), featuring a USB OTG Chip USB3300, and connected to it an USB 2513B Hub. My issue is that neither U-Boot or Linux are able to detect the USB Hub connected to the USB3300. This used to work with older U-Boot versions and are still working on my board, but I was not able to reproduce such behavior with up-to-date versions (cloned from https://github.com/altera-fpga/u-boot-socfpga and https://github.com/altera-fpga/linux-socfpga). The Chameleon96 has two GPIO pins to control the reset of the mentioned USB chips, with a fixed configuration on the USB 2513B (the I2C interface is not exposed). With my version (U-Boot 2025.07-gd4f268660a70-dirty and Linux 6.12.33-g3234b1ed8956), the USB OTG is detected and the hub registered with logs like the following: [ 0.883275] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 0.890619] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 0.898034] dwc2 ffb40000.usb: Configuration mismatch. dr_mode forced to host [ 0.905721] dwc2 ffb40000.usb: DWC OTG Controller [ 0.910454] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 0.917571] dwc2 ffb40000.usb: irq 32, io mem 0xffb40000 [ 0.923324] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, b2 [ 0.931588] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 0.938800] usb usb1: Product: DWC OTG Controller [ 0.943509] usb usb1: Manufacturer: Linux 6.12.33-g3234b1ed8956 dwc2_hsotg [ 0.950362] usb usb1: SerialNumber: ffb40000.usb [ 0.955682] hub 1-0:1.0: USB hub found [ 0.959499] hub 1-0:1.0: 1 port detected but the connected USB hub never shows up. Similarly 'usb start' from the U-Boot prompt just shows something called U-Boot Root Hub: => usb start starting USB... USB DWC2 Bus usb@ffb40000: 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Older u-boot versions (and linux) are able to detect the USB hub after 'usb start'. In this case, the root hub is named DWT OTC RootHub, and I don't know if this is just a change of naming somewhere or something wrong is also happening while detecting the USB3300 Hub: SOCFPGA_CHAMELEON96 # usb start (Re)start USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_CHAMELEON96 # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | DWC OTG RootHub | +-2 Hub (480 Mb/s, 2mA) the linux kernel (4.1.33-ltsi-altera) is also able to detect the USB Hub as can be seen in these logs: [ 0.913203] ffb40000.usb supply vusb_d not found, using dummy regulator [ 0.919864] ffb40000.usb supply vusb_a not found, using dummy regulator [ 0.957196] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRM [ 1.817295] dwc2 ffb40000.usb: DWC OTG Controller [ 1.822011] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.829076] dwc2 ffb40000.usb: irq 44, io mem 0x00000000 [ 1.834617] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.841394] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 1.848596] usb usb1: Product: DWC OTG Controller [ 1.853282] usb usb1: Manufacturer: Linux 4.1.33-ltsi-altera-svn260 dwc2_hsog [ 1.860481] usb usb1: SerialNumber: ffb40000.usb [ 1.865670] hub 1-0:1.0: USB hub found [ 1.869457] hub 1-0:1.0: 1 port detected ... [ 2.367190] usb 1-1: new high-speed USB device number 2 using dwc2 [ 2.577385] usb 1-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.584069] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.591939] hub 1-1:1.0: USB hub found [ 2.595782] hub 1-1:1.0: 3 ports detected I think I've ported all the needed configuration to the u-boot sources (basically resetting the USB hub using the attached GPIOs, and I also tried the reset sequence manually from U-Boot with the gpio command) and I'm not able to figure out how to find where the issue might be. I've forked u-boot sources here: https://github.com/teiram/u-boot-socfpga/, using the socfpga_chameleon96_defconfig configuration. Could you please support me in order to troubleshoot what the issue might be? I tried to backport my changes to some different branches on u-boot-socpfga but got the same results or even worse (no boot at all). I also have sources for a working U-Boot but they are quite old and the configuration changed sensibly since. I think all the needed options are set. Cheers, Manuel
Arria 10 Reconfiguration
Hello, I am working with an Arria 10 (10AS048) and using an external FPGA to manage configuration from a flash memory. When working with a non encrypted image, i am able to configure, then reconfigure, without issue. When i try to do the same thing with an encrypted image i have success on the initial configuration. Once i try to reconfigure I never get config_done. The A10 never pulls nStatus low to indicate a CRC error. When encryption is used is there something in the A10 that is stopping reconfiguration? Thanks
Agilex 5 RSU Reboot without any Image
Dear all, I'm currently in the process of configuring RSU on our system by following this tutorial: https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/rsu/ug-rsu-agx5e-soc/. I've added a factory partition. I've activated the Watchdog. When I don't service the watchdog, the watchdog triggers a cold reset and the system boots to the same application image again. After doing this 3 times, it's booting to the factory image. So this loooks okay. Now I want to test a corrupted image. To this end, I erase all application images (using linux rsu_client --erase) and reboot. I expect that RSU boots to the fallback image. However, the system doesn't reboot at all and I don't see any output on the console after the shutdown. If I now power-cycle the board it does boot to the fallback image. I suspect the "reboot" command only triggers the "HPS warm reset", while the watchdog triggers the "HPS cold reset". Is this expected behavior? How can I configure the reboot to trigger the cold reset? Attached you can find the log when rebooting and when applying a power cycle afterwards. I use Quartus 25.1.1. Kind Regards, Eric Opitz