Forum Widgets
Recent Discussions
Cyclone5 SoC: U-Boot not detecting USB-HUB
Hello there, I'm working on a design on top of a Chameleon96 Board (CycloneV based), featuring a USB OTG Chip USB3300, and connected to it an USB 2513B Hub. My issue is that neither U-Boot or Linux are able to detect the USB Hub connected to the USB3300. This used to work with older U-Boot versions and are still working on my board, but I was not able to reproduce such behavior with up-to-date versions (cloned from https://github.com/altera-fpga/u-boot-socfpga and https://github.com/altera-fpga/linux-socfpga). The Chameleon96 has two GPIO pins to control the reset of the mentioned USB chips, with a fixed configuration on the USB 2513B (the I2C interface is not exposed). With my version (U-Boot 2025.07-gd4f268660a70-dirty and Linux 6.12.33-g3234b1ed8956), the USB OTG is detected and the hub registered with logs like the following: [ 0.883275] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 0.890619] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 0.898034] dwc2 ffb40000.usb: Configuration mismatch. dr_mode forced to host [ 0.905721] dwc2 ffb40000.usb: DWC OTG Controller [ 0.910454] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 0.917571] dwc2 ffb40000.usb: irq 32, io mem 0xffb40000 [ 0.923324] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, b2 [ 0.931588] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 0.938800] usb usb1: Product: DWC OTG Controller [ 0.943509] usb usb1: Manufacturer: Linux 6.12.33-g3234b1ed8956 dwc2_hsotg [ 0.950362] usb usb1: SerialNumber: ffb40000.usb [ 0.955682] hub 1-0:1.0: USB hub found [ 0.959499] hub 1-0:1.0: 1 port detected but the connected USB hub never shows up. Similarly 'usb start' from the U-Boot prompt just shows something called U-Boot Root Hub: => usb start starting USB... USB DWC2 Bus usb@ffb40000: 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Older u-boot versions (and linux) are able to detect the USB hub after 'usb start'. In this case, the root hub is named DWT OTC RootHub, and I don't know if this is just a change of naming somewhere or something wrong is also happening while detecting the USB3300 Hub: SOCFPGA_CHAMELEON96 # usb start (Re)start USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_CHAMELEON96 # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | DWC OTG RootHub | +-2 Hub (480 Mb/s, 2mA) the linux kernel (4.1.33-ltsi-altera) is also able to detect the USB Hub as can be seen in these logs: [ 0.913203] ffb40000.usb supply vusb_d not found, using dummy regulator [ 0.919864] ffb40000.usb supply vusb_a not found, using dummy regulator [ 0.957196] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRM [ 1.817295] dwc2 ffb40000.usb: DWC OTG Controller [ 1.822011] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.829076] dwc2 ffb40000.usb: irq 44, io mem 0x00000000 [ 1.834617] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.841394] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 1.848596] usb usb1: Product: DWC OTG Controller [ 1.853282] usb usb1: Manufacturer: Linux 4.1.33-ltsi-altera-svn260 dwc2_hsog [ 1.860481] usb usb1: SerialNumber: ffb40000.usb [ 1.865670] hub 1-0:1.0: USB hub found [ 1.869457] hub 1-0:1.0: 1 port detected ... [ 2.367190] usb 1-1: new high-speed USB device number 2 using dwc2 [ 2.577385] usb 1-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.584069] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.591939] hub 1-1:1.0: USB hub found [ 2.595782] hub 1-1:1.0: 3 ports detected I think I've ported all the needed configuration to the u-boot sources (basically resetting the USB hub using the attached GPIOs, and I also tried the reset sequence manually from U-Boot with the gpio command) and I'm not able to figure out how to find where the issue might be. I've forked u-boot sources here: https://github.com/teiram/u-boot-socfpga/, using the socfpga_chameleon96_defconfig configuration. Could you please support me in order to troubleshoot what the issue might be? I tried to backport my changes to some different branches on u-boot-socpfga but got the same results or even worse (no boot at all). I also have sources for a working U-Boot but they are quite old and the configuration changed sensibly since. I think all the needed options are set. Cheers, Manuel
Why do I intermittently see reboot failure in the u-boot stage when running the Arria 10?
Hello, We are seeing intermittent failures in u-boot on warm reboot. U-Boot version: 2023.01Device: Arria10 To reproduce: Power on the system and let it boot. In the shell type the `reboot` command. U-boot gets stuck at the RAM ECC scrub stage (see output below). Reproducibility is about 50% of reboots. We have never seen this in a power on; we have only seen this on reboot during warm reboot (type the `reboot` command in the shell). U-boot only gets this far: U-Boot SPL 2023.01-26421-g0fa4e757b5-dirty (Jun 20 2023 - 00:59:09 +0000) U-Boot SPL 2023.01-26421-g0fa4e757b5-dirty (Jun 20 2023 - 00:59:09 +0000) DDRCAL: Success DDRCAL: Scrubbing ECC RAM (2048 MiB). This knowledge base article seems very relevant to this issue: https://community.altera.com/kb/knowledge-base/why-do-i-intermittently-see-reboot-failure-in-the-u-boot-stage-when-running-the-/339226 If so, is there a fix? Is that a fix in Quartus release as mentioned in the article? If so is there a release that fixes this issue? Is this a bug in the boot loader? If so, is there a version of the boot loader to fix this issue? Thank you!
Agilex 5 with HPS
Hi, I have a question regarding Agilex 5 with HPS. I intend to deliver to the client a device based on Agilex 5 and HPS, but initially the HPS must remain fully offline. In other words, once the device is shipped, I need to ensure with 100% certainty that no software or program can be executed on the HPS, and that there is no possible way for the client to interact with or enable it prematurely. At the same time, I need to retain the ability to remotely deploy a new FPGA bitstream at a later stage, which will enable the HPS once the HPS software development is completed. Is such a workflow achievable on this platform?
Agilex 5/3 FreeRTOS SDK
Stable Version: v25.4 Quartus Version: 25.3 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4 Release Date: January 16, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS in Agilex 5/3 devices are now available for public. visit the GitHub page for instructions on how to get started. Features and comments Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Feature Agilex3 Agilex5 Supported features Limitations/ Known issues A55 boot Yes Yes Single core boot SMP not supported A76 boot NA Yes Single core boot SMP not supported QSPI boot Yes Yes SD boot Yes Yes eMMC boot Yes Yes NAND boot No No Clk mngr driver Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Write, read and interrupt support Timer driver yes yes User defined and free running modes UART driver yes yes Full duplex Tx and Rx DMA not supported I2C driver Yes Yes Master mode write and read Standard and fast modes DMA not supported I3C driver Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported SPI driver Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes QSPI flash read/write/erase NAND driver No No SDM mailbox driver Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support 100mbps and 1gbps operation USB 2.0 stack NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT yes USB mass storage operation WDT driver Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Error injection and detection Bridge driver NT Yes Enable, Disable Reboot mngr Yes Yes Warm/Cold reboot FPGA manager Yes Yes FPGA configuration Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
Agilex 5 Multiboot SPL Fails to Probe QSPI
Dear all, I'm trying to activate the RSU Multiboot feature. Unfortunately it seems like the SPL can not probe the QSPI flash. So far I've been able to access QSPI from U-Boot and Linux. My set up: - Quartus 25.1.1 - Based on QPDS25.1_REL_GSRD_PR - HPS First - QSPI Ownership is HPS - U-Boot proper is stored on FAT partitions. Here is the console output: U-Boot SPL 2025.01-gcd3a9044d661-dirty (Jan 29 2026 - 16:45:35 +0000) Reset state: Cold MPU 1250000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 50000 kHz is_ddr_csr_clkgen_locked: ddr csr io96b_0 clkgenA is successfully locked io96b_cal_status: Calibration for IO96B instance 0x18400400 done at 0 msec! init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success io96b_mb_init: num_instance 1 io96b_mb_init: get memory interface IO96B 0 io96b_mb_init: IO96B 0 mem_interface 0: ip_type_ret: 0x1 io96b_mb_init: IO96B 0 mem_interface 0: instance_id_ret: 0x0 io96b_mb_init: IO96B 0: num_mem_interface: 0x1 DDR4: 2048 MiB ecc_enable_status: ECC enable status: 0 DDR: size check success DDR: firewall init success DDR: init success QSPI: Reference clock at 500000 kHz WDT: Started watchdog@10d00200 with servicing every 1000ms (11s timeout) Trying to boot from MMC1 RSU: Error - spi_flash_probe failed! ERROR: could not find u-boot proper(SSBL): SSBL.@xx! And here is the relevant dts section: &qspi { status = "okay"; flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,mt25qu256a", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <6250000>; m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; cdns,read-delay = <2>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Boot and fpga data"; reg = <0x00a10000 0x015f0000>; phandle = <0x53>; }; }; }; }; Kind Regards, Eric Opitz
HPS f2sdram read/write errors
I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic. I can perform read and write cycles and everything flows correctly. I get appropriate response from the f2sdram. however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error. i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. Anything common that I might have missed in my setup?