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Unique ID registers in Cyclone V
Hello everyone, I need to uniquely identify individual devices at runtime from the HPS (ARM Cortex-A9) side. Does the HPS side of the Cyclone V SoC have any built-in unique ID registers, such as: - A hardware serial number - A unique device ID - OTP (One-Time Programmable) fuses with unique identifiers - Any factory-programmed identification values What I've Tried: I've reviewed the Cyclone V documentation but haven't found clear information about unique ID registers accessible from the HPS side (unlike some other ARM SoCs that have dedicated UID registers). However I have seen Unique ID present in the FPGA side (https://www.intel.com/content/www/us/en/docs/programmable/683336/20-3/cores-user-guide.html), but this is not useful for my use case. Any guidance, documentation references, or code examples would be greatly appreciated! Thanks in advance!
Operating system kernel-level FPGA bridge communication
We are using a custom (Agilex 5) platform and need to access the FPGA bridges from the Linux kernel. We are unable to locate the corresponding device tree nodes or modifications required to access these memory-mapped regions. We're aware of the devmem2 package, but we want to access the FPGA from the kernel side without relying on it. Please guide us on how to configure the device tree and use kernel-level commands or interfaces to access the HPS-to-FPGA and Lightweight HPS-to-FPGA bridges. configuration from Linux. CONFIG_OF_RESOLVE y CONFIG_OF_OVERLAY y CONFIG_OF_CONFIGFS y CONFIG_FPGA_MGR_STRATIX10_SOC y CONFIG_FPGA_BRIDGE y CONFIG_FPGA_REGION y CONFIG_OF_FPGA_REGION y CONFIG_OVERLAY_FS y
Routing PL DDR to PS
We have an Arria 10 board with bad traces between the DDR memory and the hard memory controller for the PS. The PL has additional DDR memory not connected to the PS that works fine. Does a workaround exist that allows us to route the DDR memory connected to the PL and use it for Linux on the PS?Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel
We are now looking to validate ECC (Error Correction Code) functionality on our custom Agilex 5 System-on-Module (SOM) running Linux. Our objective is to ensure that ECC is correctly enabled and functioning across all relevant memory regions, and that error detection and correction mechanisms are properly integrated at the kernel level. Could you please provide guidance on the necessary kernel configurations, device tree modifications, and available tools or procedures to test and monitor ECC behavior on this platform? Any documentation or reference designs specific to Agilex 5 ECC support would be highly valuable.
HPS SDRAM Calibration Failed
To whom it may concern, The HPS of a Cyclone V SoC based board that I designed is failing the booting process. In which the following error message is outputted to the console: U-Boot SPL date and time SDRAM Calibration Failed. ERROR ### Please Reset the board ### I’m trying to determine the cause of the SDRAM calibration failure by enabling calibration reporting as indicated in: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/enabling-the-debug-report-for-arria.html https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/determining-the-failing-calibration.html but I’m only getting the above mentioned message without an indication of the failing SDRAM stage and cause. please advise on how to get the preloader to output debug insights to the console. Please note that the approach described in the link below was used to create the Preloader: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 Also, please advise on the sequence of failure messages that are outputted by the Preloader. Regards,To evaluate and monitor CPU frequency behavior in the Kernel OS
We need to verify CPU frequency behaviour straight from the Linux kernel because we are currently working with a customised Agilex 5 System-on-Module (SOM). Ensuring appropriate frequency scaling and governor functionality under a range of workloads is our aim. Would you kindly provide guidance regarding the device tree modifications, kernel configurations, and testing methods needed to enable and validate CPU frequency scaling on this platform? I would be very grateful for any advice or reference materials that are specific to Agilex 5.
SDRAM calibration failed.
Hello, after Enpirion stopped selling some of the parts we used on our board, we had to redesign it. We assembled ten boards, and on two of them, I’m now getting an SDRAM calibration error in U-Boot. I’d like to enable the SDRAM calibration report to understand the cause of the error. However, the described method of adding. #define RUNTIME_CAL_REPORT 1 in the sequencer_defines.h file didn’t work. I generated the files using the QTS filter script, but there was no change. Could you please tell me how to properly enable the SDRAM calibration report so I can debug the issue?
25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2025.10/ Major Features Released Support of GHRD 2.0 in Agilex™ 5 which includes foundational boot to Linux, ability to create compatible phase 2 bitstreams, parameterized HPS for maximum performance and best practices. Support of GSRD 2.0 Yocto layers for the Agilex 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Agilex 5 GSRD Development User Experience Improvement through KAS using a graphical/text interface to configure a limited number of high-level options on top of simplified Yocto recipes. - GSRD 2.0 with Kas Build System Support for running Agilex 5 Simics Simulation under the GSRD 2.0 framework. Booting from SD Card and QSPI is supported. - Exercising Simics Simulation from GSRD 2.0 Support GHRD and GSRD for Agilex™ M-Series PRQ HBM2e for DK-Sl-AGM039EA development kit. The GSRD is capable of booting to Linux. - Build the GSRD for DK-DEV-AGM039EA Hypervisor Multi-OS Support Example, demonstrating Linux and Zephyr running side-by-side in the HPS cluster. - HPS Xen Hypervisor GSRD System Example Design: Agilex™ 3 FPGA and SoC C-Series Development Kit Support for monitoring of SEU errors from the SDM in the HPS in Agilex™ 7. Add capability to measure the latency of Linux SMC calls. Support Nios V Lockstep application with a fail-safe mechanism