Featured Content
Forum Widgets
Recent Discussions
Agilex 5E HPS and Linux
Hi. 1. Is there a simple method to run two Linux systems on HPS, i.e.: Linux 1 - 2xA55 and Linux 2 - 2xA76 with different sets of peripherals? 2. Is it possible to use one Ethernet port by these two Linux systems. 3. Is there a simple method for communication between these two Linux systems?LWH2F Throughput
Dear all, I'm facing the issue that the throughput on the Agilex 5 LWH2F interface appears to be lower compared to Cyclone 5. - I have two custom boards, one is based on Cyclone 5, the other on Agilex 5. - I use a linux OS. The code runs in a linux kernel driver. The code for the driver is the same for both devices. - The memory is mapped using ioremap(), i.e. it is mapped as device memory. - I measure performance by taking a timestamp with ktime_get_ns(), then read/write 10000 uint32 values, then take another timestamp. - I've measured the follwing values - Cyclone5 board read: 47.2 MB/s (million bytes per second or 11.8 million words à 4 byte per second) - Cyclone5 board write: 73.1 MB/s - Agilex5 board read: 24.8 MB/s - Agilex5 board write: 18.8 MB/s - I've noticed that performance varies, depending on the CPU that the process is running on (when measuring in userspace I can explicitly set the cpu affinity; For the kernel driver I've noticed that it is sometimes slower than above, presumably because it's running on a different cpu). - There is a slight difference in the QSYS design: - The Cyclone5 based board: - drives the AXI bus with a 64 MHz clock. - uses the Avalon MM Slave Translator. - The Agilex5 based board: - drives the AXI bus with a 200 MHz clock. - uses the Avalon Memory Mapped Pipeline Bridge Intel FPGA IP. - Our FPGA takes one 64/200 MHz cycle to process the read (readdatavalid). For a write our FPGA doesn't generate a writeresponsevalid, this is handled by the IP block. - I'm using Quartus 25.1.1 for the Agilex 5 design. I'm aware that the LWH2F interface is not intended for high throughput. Also, since the memory is mapped as "Device Memory", every load/store is processed separately and we're not taking advantage of AXI bursts, etc. I'm aware that we could improve performance by using the H2F interface and mapping the memory as normal memory. That said, we have a prooven design and are reluctant to change it unless absolutely neccessary. So I have the following questions: - Is a higher latency expected on Agilex5? (E.g. due to a different architecture of the interconnect) - Have you measured the performance of the LWH2F interface? Can you give me a number on how many transactions per second we can expect? Kind Regards, Eric OpitzUSB Device Issue on Cyclone V / HPS
Hello, Please find below a description of the USB issue we are experiencing with our Cyclone V / HPS board. To test our USB interface, we integrated the TinyUSB library into our existing firmware and enabled FreeRTOS support. Since the Cyclone V is not natively supported, I implemented the missing functions using Altera's hwlib, which we already use in our project (source file attached). The USB is used only in Device mode. I tested the following four configurations: Full-Speed with Slave mode Full-Speed with Simple DMA High-Speed with Slave mode High-Speed with Simple DMA The behavior is identical in all four cases: Connecting our board to a Windows or Linux host is correctly detected. The SETUP transaction is successfully received, and the host receives the device descriptor in response. When the IN transfer complete interrupt is triggered, the USB controller is configured to receive a zero-length packet on OUT0. However, the USB protocol analyzer shows that the device continuously responds with NAK to this packet. The host retries for approximately 5 seconds, but the device keeps responding with NAK. The register values immediately after configuring the reception of the OUT0 packet are: Gotgctl = 0xd00c0 Gintsts = 0x4000020 (PTxFEmp, NPTxFEmp) Gdfifocfg = 0x1f802000 Dctl = 0 Dcfg = 0x8100001 Dsts = 0x18702 Doepctl0 = 0x80008000 Doepint0 = 0 Doeptsiz0 = 0x80000 Grxfsiz = 0x50 After a few milliseconds, I observe that DOEPINT0.NAKINTRPT = 1, which seems to confirm that the device is sending NAKs. However, I do not understand why the OUT packet is not being accepted, since the receive FIFO is not full and both DCTL.GOUTNAKSTS = 0 and DOEPCTL0.NAKSTS = 0.Intermittent DE10-Standard error starting GDB server with quartus_hps
Hello, We have 15 DE10-Standard boards being used with Quartus 18.1 and the associated version of Altera Monitor Program on Ubuntu 24.04 (amd64). Generally the boards work without issue, however in the Monitor Program we occasionally see 'Download System - Partial Success: The system has successfully downloaded onto the board, but HPS components could not be configured.' Power cycling the board doesn't seem to resolve the error, nor does swapping the board to a different desktop. After a number of tries the error will go away. We haven't been able to isolate an exact pattern but issue doesn't appear random either, it will keep showing up for certain boards, and then go away, then show up on other boards. Another symptom we see is that when a board downloads the systems successfully, during the final step of the process the JTAG TX LED on the board appears to turn solid green. On the boards that hang and fail, the same LED flashes rapidly while the process hangs. The monitor program logs show the following commands are run before the error appears: $ /home/$USER/DE10/monitorprogramtutorial/ $ make clean # The board name in quotes below is variable and appears to be unique to each board or connection $ /opt/intelFPGA_lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [1-10]" --auto $ quartus_pgm -c "DE-SoC [1-10]" -m jtag -o "P;/opt/intelFPGA_lite/18.1/University_Program/Computer_Systems/DE10-Standard/DE10-Standard_Computer/verilog/DE10_Standard_Computer.sof@2" $ quartus_hps --cable="DE-SoC [1-10]" -o GDBSERVER --gdbport0=3212 --preloader=/opt/intelFPGA_lite/18.1/University_Program/Monitor_Program/arm_tools/u-boot-spl.de10-standard.srec --preloaderaddr=0xffff14f0 Running these commands manually results in the final command either: 1. Starting a GDB server very quickly: >>Resetting HPS. >>Downloading preloader....... >>Program loaded. PC set to program entry (0xFFFF0000) >>Setting vector base address register to: 0xffff0000 >>Running preloader.. >>Preloader successfully run. Starting GDB Server. Listening on port 3212 for connection from GDB 2. Hanging for a long time when 'Downloading preloader.......' and then failing at the 'Running preloader...................' stage and hanging indefinitely. Ending the process with Ctrl+C shows: Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to enable DEBUG feature Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Failed to load program. Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Encounter JTAG AJI error while reading Control/Status Register Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 0 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to write to MPU Module Reset Register Error: Engine failed to set down the hardware Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings Error: Peak virtual memory: 187 megabytes Error: Processing ended: Tue Aug 11 11:44:38 2026 Error: Elapsed time: 00:05:05 Error: Total CPU time (on all processors): 00:00:01 Any thoughts or suggestions are greatly appreciated.
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10HPS First Boot Configuration for Agilex 7
Dear Community, I'm developing a design using Agilex 7 on Quartus Pro 24.2. I'm a bit confused on the parameter settings I need for the HPS (and its EMIF) and my Quartus project settings in order to have HPS-First boot (Called HPS Early Release in former Quartus versions). For that, I'd like to generate .core.rbf and .periph.rbf files. I tried generating the .rbf files in two different ways given below, none succeeded. #1) Having the below pfg command in a text file and sourcing it in my .qsf --convert --hps -o bitstream_compression=on output_files/ProjectName.sof output_files/ProjectName.rbf #2) Using the Programming File Generator tool of Quartus I can generate .sof programming file, but converting that to .rbf fails with the following error when I did either given above. "sof is incomplete. Hps is present but bootloader information is missing". When doing case #2, I even add a bootloader .hex file that I could find on Rocketboards' webpage. Could anyone support me to have an HPS-first boot on Agilex 7 ? Thanks in advance!
