U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation
I am reaching out for technical assistance regarding a reproducible boot failure on the Terasic Atum A5 Rev B development board (Agilex 5) when using Quartus Prime Pro 24.3. I am attempting to compile a custom design that utilizes the Lightweight HPS-to-FPGA (lwhps2fpga) bus. My current workflow is as follows: Compile the project in Quartus 24.3 to generate the .sof file. Merge the .sof with the official Terasic FSBL .hex file. Use the Programming File Generator (PFG) to create a .jic file. Flash the .jic to the QSPI. The Issue: When flashing the .jic generated by this workflow, the boot process fails during the main U-Boot phase. The U-Boot SPL and ATF (BL31) load successfully. However, after U-Boot attempts to load the environment, the system crashes with a "Synchronous Abort" handler (esr 0x96000010, far 0x108d2000). This triggers a CPU reset with the message ### ERROR ### Please RESET the board ###. (I have attached the full UART terminal log of the boot sequence for reference). Isolation Testing: To isolate the issue from my custom logic, I applied this exact same compilation and .jic generation workflow to the official Terasic GHRD bundled with the board. The result was identical—the GHRD .jic generated by Quartus 24.3 crashes at the exact same U-Boot Synchronous Abort. Conversely, when I bypass compilation and simply flash the original, pre-compiled .jic provided in the Terasic resource package, the board boots into Linux flawlessly. This confirms the physical hardware is fully functional and the issue is strictly isolated to the .jic files being generated by the 24.3 workflow. Questions: Is there a known issue or missing step in the Quartus 24.3 workflow when merging the FSBL or configuring the .jic for the Agilex 5 that would cause U-Boot to encounter a Data Abort (likely when probing the AXI bridges)? What are the exact PFG parameters or required patches to successfully generate a booting .jic for this board under the 24.3 release? I look forward to your guidance on resolving this workflow issue
Agilex5 HPS2FPGA usage
Hello, I have an Agilex 5E 065B devkit board with Part Number A5ED065BB32AE6SR0. I have created a design in quartus that uses HPS2FPGA communication. I tested the design extensively and now want to configure the FPGA. However, it is not clear to me how the workflow has to be in that case after reading the documentation: https://docs.altera.com/r/docs/814550/current/agilextm-5-fpga-e-series-065b-premium-development-kit-user-guide/overview . Below I list my worklfow (which was not working out): Phase 1: Resotre GSRD I have a compiling quartus design I download the official GSRD JIC from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz In quartus I open the JTAG programmer and connect the device to my local machine. I power on the device with SW27 set to OFF-OFF-OFF-OFF. After clicking "auto-detect", I right click my FPGA device and click "change file" and select the freshly downloaded jic file. I click "start" and wait till process is completed sccessfully. I insert the HPS board's SD card into my local machine and download the GSRD SD image from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/sdimage.tar.gz I rename the .wic file to a .img file. Then I use Win32DiskImager to flash the image to the SD card. After completion I insert the SD card back into the HPS board. I connect the vertical HPS board pin to my local machine and open PUTTY to target the COM port. A window opens, which stays blank. I set SW27 to OFF-ON-ON-OFF and power on the board. In PUTTY I can see the linux boot logs. I can log in as root without password. Phase 2: I download the U-BOOT hex that matches my device from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/u-boot-spl-dtb.hex I open a NIOS shell and create a .jic file based on my designs rbf, by typing the command: quartus_pfg -c <my_project>.sof <my_project>.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AR0 -o hps_path=<hex_file_path> -o mode=ASX4 -o hps=1 This created a .hps.jic file. I set SW27 back to OFF-OFF-OFF-OFF and connect to my local machine and power on the board. In quartus I again configure my newly created jic to the board via JTAG chain. After completion I power off the board and set SW27 back to OFF-ON-ON-OFF. I open a PUTTY window and power on the board. However, this time the PUTTY window stays quiet even after several minutes. So I guess the boot is not happening correctly. I would like to know if there is a substantial error in my workflow or, if there might be a problem in my quartus settings maybe (I have set configuration order to HPS first). I would be very glad if someone could help me with that. Feel free to tell me if any kind of log or additional information is required for understanding the error.
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
Agilex 5E - PCIE PERST# pin - failing compilation
Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 lanes to bank 4B. I have checked the pin assignments several times but I keep getting failed compilation with the error attached bellow. Any suggestions on what can cause the issue. I have also attached the pin assignments. Thank youS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!Agilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!
HPS f2sdram read/write errors
I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic. I can perform read and write cycles and everything flows correctly. I get appropriate response from the f2sdram. however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error. i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. Anything common that I might have missed in my setup?
