Agilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
HPS f2sdram read/write errors
I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through the AXI4 bus on the hps_subsys, I exported the f2sdram (AXI4 Subordinate) and connected to my custom logic. I can perform read and write cycles and everything flows correctly. I get appropriate response from the f2sdram. however, on both read and write cycles, the f2sdram responds with the RRESP/BRESP of b11, decode error. i have tried to read/write to addresses of 0x0000000000, 0x8800000000, and 0xffff000000 and still get the same response error code. Anything common that I might have missed in my setup?Agilex5 HPS2FPGA usage
Hello, I have an Agilex 5E 065B devkit board with Part Number A5ED065BB32AE6SR0. I have created a design in quartus that uses HPS2FPGA communication. I tested the design extensively and now want to configure the FPGA. However, it is not clear to me how the workflow has to be in that case after reading the documentation: https://docs.altera.com/r/docs/814550/current/agilextm-5-fpga-e-series-065b-premium-development-kit-user-guide/overview . Below I list my worklfow (which was not working out): Phase 1: Resotre GSRD I have a compiling quartus design I download the official GSRD JIC from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz In quartus I open the JTAG programmer and connect the device to my local machine. I power on the device with SW27 set to OFF-OFF-OFF-OFF. After clicking "auto-detect", I right click my FPGA device and click "change file" and select the freshly downloaded jic file. I click "start" and wait till process is completed sccessfully. I insert the HPS board's SD card into my local machine and download the GSRD SD image from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/sdimage.tar.gz I rename the .wic file to a .img file. Then I use Win32DiskImager to flash the image to the SD card. After completion I insert the SD card back into the HPS board. I connect the vertical HPS board pin to my local machine and open PUTTY to target the COM port. A window opens, which stays blank. I set SW27 to OFF-ON-ON-OFF and power on the board. In PUTTY I can see the linux boot logs. I can log in as root without password. Phase 2: I download the U-BOOT hex that matches my device from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/u-boot-spl-dtb.hex I open a NIOS shell and create a .jic file based on my designs rbf, by typing the command: quartus_pfg -c <my_project>.sof <my_project>.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AR0 -o hps_path=<hex_file_path> -o mode=ASX4 -o hps=1 This created a .hps.jic file. I set SW27 back to OFF-OFF-OFF-OFF and connect to my local machine and power on the board. In quartus I again configure my newly created jic to the board via JTAG chain. After completion I power off the board and set SW27 back to OFF-ON-ON-OFF. I open a PUTTY window and power on the board. However, this time the PUTTY window stays quiet even after several minutes. So I guess the boot is not happening correctly. I would like to know if there is a substantial error in my workflow or, if there might be a problem in my quartus settings maybe (I have set configuration order to HPS first). I would be very glad if someone could help me with that. Feel free to tell me if any kind of log or additional information is required for understanding the error.
MSGDMA ST-to-MM: Linux Driver Necessity & F2SDRAM Path Feasibility
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow
Hi, I recently acquired an Arria 10 SoC dev kit but I'm really struggling to run either the examples on embedded-software/bare-metal or the ones included in SoC EDS pro 20.1, trying to follow the instructions for both of them, they seem to rely on a old version of SoC EDS which included within ARM DS-5 and the toolchain, but now SoC EDS & ARM DS are separated and I cannot build the examples. With the new applications the flow for using this examples should remain the same? I mean: use Pogrammer to program the included .sof inside ghrd (or generate a updated one) -> open ARM-DS from SoC-EDS with environmental variables assigned and build with new toolchain arm-none-eabi -> run from ARM-DS (can i without license?) Seems like most of the tools used for running this examples have been discontinued (for example ) so at this point I don't know which workflow should I actually follow. PD: finally I was able to generate de application.axf from this example Altera-SoCFPGA-HardwareLib-16550-CV-GNU with an old toolchain but I don't know how to program it without a license, for now I don't want to debug anything, just do some simple tests printing by uart
Agilex 5 EMAC GMII loopthrough: signals are not toggling in Fabric
I am trying to route GMII signals through the Agilex5 HPS to the Fabric. In the .dts I am using, I have the following settings for the two EMACs: &gmac0 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; // must be added, and if no PHY, then add fixed link //phy-handle = <&emac0_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac0_phy0: ethernet-phy@0 { reg = <0>; }; }; }; &gmac1 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; //phy-handle = <&emac1_phy0>; max-frame-size = <9000>; fixed-link { speed = <1000>; full-duplex; }; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac1_phy0: ethernet-phy@0 { reg = <0>; }; }; }; In the RTL I am connecting the two EMACs as followed: logic user_clk_pll_125, user_clk_pll_25, user_clk_pll_2_5; // 1G / 100M / 10M (* noprune *) logic [7:0] tx_dummy_counter; (* noprune *) logic emac0_mac_tx_clk_o_wire, emac0_mac_tx_clk_i_wire, emac0_mac_rx_clk_wire, emac0_mac_rst_tx_n_wire, emac0_mac_rst_rx_n_wire; (* noprune *) logic emac0_mac_txen_wire, emac0_mac_txer_wire, emac0_mac_rxdv_wire, emac0_mac_rxer_wire, emac0_mac_col_wire, emac0_mac_crs_wire; (* noprune *) logic [7:0] emac0_mac_rxd_wire; (* noprune *) logic [2:0] emac0_mac_speed_wire; (* noprune *) logic [7:0] emac0_mac_txd_o_wire; (* noprune *) logic [7:0] rx_dummy_counter; (* noprune *) logic emac1_mac_tx_clk_o_wire, emac1_mac_tx_clk_i_wire, emac1_mac_rx_clk_wire, emac1_mac_rst_tx_n_wire, emac1_mac_rst_rx_n_wire; (* noprune *) logic emac1_mac_txen_wire, emac1_mac_txer_wire, emac1_mac_rxdv_wire, emac1_mac_rxer_wire, emac1_mac_col_wire, emac1_mac_crs_wire; (* noprune *) logic [7:0] emac1_mac_rxd_wire; (* noprune *) logic [2:0] emac1_mac_speed_wire; (* noprune *) logic [7:0] emac1_mac_txd_o_wire; assign emac0_mac_rx_clk_wire = emac1_mac_tx_clk_o_wire; // 1G assign emac1_mac_rxdv_wire = emac0_mac_txen_wire; assign emac1_mac_rxer_wire = emac0_mac_txer_wire; assign emac1_mac_rxd_wire = emac0_mac_txd_o_wire; assign emac1_mac_col_wire = 1'b0; assign emac1_mac_crs_wire = 1'b0; assign emac0_mac_rx_clk_wire = emac0_mac_tx_clk_o_wire; // 1G assign emac0_mac_rxdv_wire = emac1_mac_txen_wire; assign emac0_mac_rxer_wire = emac1_mac_txer_wire; assign emac0_mac_rxd_wire = emac1_mac_txd_o_wire; assign emac0_mac_col_wire = 1'b0; assign emac0_mac_crs_wire = 1'b0; The GMII signals are exported from the Agilex HPS as followed: When the system boots, the following can be seen is dmesg: [ 1.443647] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0 [ 1.450679] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found [ 1.457291] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found [ 1.463542] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping [ 1.469741] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported [ 1.477398] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.484534] socfpga-dwmac 10810000.ethernet: XGMAC2 [ 1.489489] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported [ 1.496943] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported [ 1.504396] socfpga-dwmac 10810000.ethernet: COE Type 1 [ 1.509603] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported [ 1.516623] socfpga-dwmac 10810000.ethernet: TSO supported [ 1.522089] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.530076] socfpga-dwmac 10810000.ethernet: device MAC address 42:ca:f5:1e:55:80 [ 1.537533] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.544737] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.551847] socfpga-dwmac 10810000.ethernet: TSO feature enabled [ 1.557831] socfpga-dwmac 10810000.ethernet: SPH feature enabled [ 1.563815] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues [ 1.570665] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width [ 1.581335] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1 [ 1.588338] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found [ 1.594945] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found [ 1.601179] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping [ 1.607380] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported [ 1.614905] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.622027] socfpga-dwmac 10820000.ethernet: XGMAC2 [ 1.626982] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported [ 1.634436] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported [ 1.641890] socfpga-dwmac 10820000.ethernet: COE Type 1 [ 1.647097] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported [ 1.654117] socfpga-dwmac 10820000.ethernet: TSO supported [ 1.659583] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.667568] socfpga-dwmac 10820000.ethernet: device MAC address 3e:47:0a:4f:7b:96 [ 1.675024] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.682221] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.689330] socfpga-dwmac 10820000.ethernet: TSO feature enabled [ 1.695314] socfpga-dwmac 10820000.ethernet: SPH feature enabled [ 1.701298] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues [ 1.708147] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width [ 1.718293] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2 [ 1.725245] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found [ 1.731850] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found [ 1.738075] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping [ 1.744242] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported [ 1.751730] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31 [ 1.758854] socfpga-dwmac 10830000.ethernet: XGMAC2 [ 1.763807] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported [ 1.771261] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported [ 1.778712] socfpga-dwmac 10830000.ethernet: COE Type 1 [ 1.783917] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported [ 1.790936] socfpga-dwmac 10830000.ethernet: TSO supported [ 1.796400] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 1.804372] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16) [ 1.811565] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10) [ 1.818673] socfpga-dwmac 10830000.ethernet: TSO feature enabled [ 1.824656] socfpga-dwmac 10830000.ethernet: SPH feature enabled [ 1.830639] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues [ 1.837487] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width ... [ 11.730428] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 11.747001] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 11.770275] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 11.778338] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 11.782322] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 11.787412] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 11.790998] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 11.796018] socfpga-dwmac 10830000.ethernet eth2: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 11.813781] fpga_manager fpga0: Stratix10 SOC FPGA Manager registered [ 11.913063] socfpga-dwmac 10830000.ethernet eth2: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL) [ 11.913393] socfpga-dwmac 10830000.ethernet eth2: No Safety Features support found [ 11.913478] socfpga-dwmac 10830000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported [ 12.001908] socfpga-dwmac 10830000.ethernet eth2: registered PTP clock [ 12.007839] socfpga-dwmac 10830000.ethernet eth2: FPE workqueue start [ 12.007940] socfpga-dwmac 10830000.ethernet eth2: configuring for phy/rgmii-id link mode [ 12.155854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.159161] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.180998] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.191086] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.199787] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.208205] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.218464] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.229854] socfpga-dwmac 10820000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.247722] socfpga-dwmac 10820000.ethernet eth1: No Safety Features support found [ 12.247967] socfpga-dwmac 10820000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported [ 12.331440] socfpga-dwmac 10820000.ethernet eth1: registered PTP clock [ 12.332900] socfpga-dwmac 10820000.ethernet eth1: FPE workqueue start [ 12.332987] socfpga-dwmac 10820000.ethernet eth1: configuring for fixed/gmii link mode [ 12.343803] socfpga-dwmac 10820000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off [ 12.344209] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 12.449807] of-fpga-region soc:base_fpga_region: FPGA Region probed [ 12.469882] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 [ 12.479649] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1 [ 12.482568] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2 [ 12.490255] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3 [ 12.493314] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4 [ 12.501735] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5 [ 12.514200] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6 [ 12.536765] socfpga-dwmac 10810000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7 [ 12.582718] socfpga-dwmac 10810000.ethernet eth0: No Safety Features support found [ 12.583005] socfpga-dwmac 10810000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported [ 12.591157] socfpga-dwmac 10810000.ethernet eth0: registered PTP clock [ 12.601012] socfpga-dwmac 10810000.ethernet eth0: FPE workqueue start [ 12.601201] socfpga-dwmac 10810000.ethernet eth0: configuring for fixed/gmii link mode [ 12.611650] socfpga-dwmac 10810000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 12.615095] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready ... (this log was from testing 100M, but the same occurs for 1G) In signal tap, no wires are toggled (even though it seems the output clocks are fine) Please help!
