How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
USB Blaster II Problem
Hello, I’m having a persistent issue with my USB-Blaster II programmer. No matter what I try, the programmer is detected only as a USB-Blaster variant, without the TCK speed option, and it does not work ... Occasionally, I can get it working by removing the installed driver and reinstalling it. However, after unplugging the programmer or restarting the computer, it reverts back to being detected as the USB-Blaster variant. Then I have to repeat the process: remove the driver, reinstall it, restart the JTAG server, or sometimes restart the whole computer. Even when it works, it only lasts for a single session. I have tried several Quartus Programmer versions, but the issue remains the same. The strange part is that I do not have this problem on my personal laptop or on my colleagues’ computers, so it seems specific to this machine. IT Helpdesk was also was not able to solve this problem Has anyone encountered this issue before or found the root cause? This is especially frustrating because I need to program a Cyclone GX device, and other programmers do not work for this use case. Any suggestions would be appreciated. Thank you!
Cascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packets
Hello community, I have a DSP system with 32 independent 256-bit output channels using Avalon-ST (or AXI-Stream) on an AGX FPGA. To transfer packetized data to the HPS, I implemented a cascaded Avalon Streaming Multiplexer architecture. The 32 channels are divided into two groups of 16. Each group connects to a 16-to-1 Avalon-ST Multiplexer IP. The outputs of these two multiplexers are then connected to a final 2-to-1 Avalon-ST Multiplexer IP, forming an overall 32-to-1 mux structure. At the output of the final 2-to-1 mux, I also added another 2-to-1 Avalon-ST mux with a selectable input for a data packet emulator. Using the emulator path, I verified that the FPGA-to-HPS data path is functioning correctly. However, after switching from the emulator path to the DSP output path, I only receive packets from channel 0. No packets from the other DSP channels are observed by the HPS. For debugging, I intentionally generated valid packets on non-zero channels. In SignalTap, I observed that channel 28 was asserting valid packet data (valid = 1) while ready = 0. This capture was taken at the input of the second 16-to-1 mux, since channel 28 belongs to the upper 16-channel group. Next, I changed the SignalTap trigger condition to the rising edge of the output valid signal of the second 16-to-1 mux. However, the trigger condition was never met, even after repeated acquisitions. The ready signals throughout the mux stages remain asserted, which suggests there is no downstream backpressure from the FIFO path to HPS. The downstream FIFO status also indicates that it is empty. The confusing part is the following: After enabling channel 0 again, both channel 0 and channel 28 should have had valid packets simultaneously. In this case, packets from channel 0 were forwarded correctly to the HPS. I verified this by reading 8 words from the memory FIFO and reconstructing the original packet; all received packets contained the channel ID corresponding to channel 0. However, after disabling channel 0 again, no new packets were received from any channel, including channel 28. Based on these observations, it appears that the internal round-robin scheduler of the Avalon-ST mux may not be operating correctly. The two 16-to-1 muxes and the final 2-to-1 mux are all configured identically in Platform Designer. Does anyone have suggestions on what could cause this issue, or recommendations on how to further debug the Avalon-ST mux behavior? I noticed an interesting behavior on channel 28 related to the Avalon-ST handshake. The ready signal for channel 28 remains asserted during idle cycles, but it becomes deasserted exactly when valid is asserted. In other words: | Cycle | valid | ready | | ---------- | ----- | ----- | | Idle | 0 | 1 | | Data cycle | 1 | 0 | | Next cycle | 0 | 1 | This differs from channel 0, where both valid and ready are asserted simultaneously, forming a successful Avalon-ST handshake. My DSP source currently only pulses `valid` for one cycle when data is available. Could the Avalon-ST Multiplexer scheduling size setting (Scheduling Size = 2) contribute to this behavior? Specifically, can the mux arbitration latency caused by the scheduling configuration prevent non-zero channels from completing a handshake if valid is only asserted for one cycle? Thank you very much.List of available patches for specific Quartus version
@Altera support: It is difficult and time consuming to find if there exist patch for specific issue/defect of Quartus Prime on Knowledge Base and/or Forums. It would be great to have simple page, which contain list of all publicly available patches for specific version of Quartus xx.x Lite/Standard/Pro with links to descriptions what is fixed by particular patches and download links. BR, Martin
A5EG013BB18A OPN is visible in Quartus but not listed in Program File Generator
Hi everyone, I am currently working on programming an SCM FPGA board using Intel Quartus 25.1 . Our target FPGA OPN is A5EG013BB18A. I need to generate a .jic file from a .sof file by using the Program File Generator. However, when I try to select the FPGA Device in the Program File Generator, we cannot find A5EG013BB18A in the device list. The strange thing is that A5EG013BB18A can be seen in other places within Quartus, but it is not shown only in the Program File Generator device selection list. I have attached screenshots and related files showing: 1. The device can be seen in Quartus 2. The Program File Generator FPGA Device selection list 3. The content of .ini file and the .qsf file Could anyone help confirm the following? Is A5EG013BB18A supported in the Program File Generator? 2. Is there any specific .ini file setting or placement required for the Program File Generator to show this OPN? 3. Is a specific Quartus version or device package required? 4. Is there any known limitation where an OPN is visible in Quartus but not available in the Program File Generator? Any advice or reference would be appreciated. Thank you.SSLC Login Issue – "You need to enroll" loop after OTP verification
Hi, I am facing an issue with the Altera Self Service Licensing Center (SSLC). Problem: - I enrolled at licensing.altera.com successfully - I receive the OTP verification code on my email - After entering the OTP correctly, it shows: "Access to the SSLC portal requires registration Register here to get started." - This creates an infinite loop and I cannot access the portal at all I need to generate a free Questa Intel FPGA Starter Edition (SW-QUESTA) license for use with Quartus Prime Lite 24.1. Things I already tried: - Enrolled with two different email IDs - Tried Chrome, Edge, and Incognito mode - Cleared cookies and cache. Could you please either: 1. Fix my account access, OR 2. Manually generate and send the license.dat file to my email My registered email: Sailakshmi1872006@gmail.com Thank you.
Recommendations for Quartus Prime File Cloud Storage
Hi All, Currently users in our organization are able to use Box Drive to backup and store Quartus files in the cloud. We are unfortunately getting rid of Box Drive and moving users over to OneDrive. With the known issues with Quartus Prime and OneDrive I wanted to see if anyone had any recommendations for alternative cloud storage platforms that work with Quartus Prime. The idea is to have a cloud location that we are able to backup projects to.
