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Agilex-5 supported Transceivers
I am currently evaluating the capabilities of the Altera Dev Board DK-A5E065AB32AEA. As most SFP+ and QSFP+ Transceivers are often vendor-locked, is there a list of qualified Transceivers available? Intel E10GSFPSR and another Xcvr marketed as support for Nvidia did not work in my case, as I attempted to do the initial Testing using BTS App as per document D554638 Which transceivers were used by Intel(Altera) for qualifiying/testing the development board DK-A5E065AB32AEA ?
Looking for example testbench for Cyclone-V Transceiver Custom_PHY IP from UG-01080-1.7
Hi, I am looking into the Altera Transceiver PHY IP Core User Guide, UG-01080-1.7 (June 2012). I followed section 7, “Custom PHY IP Core” to generate a custom PHY core using the Quartus 23.1-based MegaWizard and IP Catalog for my Cyclone-V FPGA. I have all Verilog files generated for the custom PHY IP in a new folder tst_xcvr_phy_custom. Next, I tried to do a basic loopback simulation of this custom PHY core. Page 7-28 in the user guide states : ............ However when I try the "Altera wiki" link I get .... not sure why I get this, I do have an active Altera account. Perhaps this Altera-Wiki has been migrated to a Github Altera Transceivers (PHY IP) examples repo ? Can someone help me get an example testbench for the Cyclone-V custom PHY IP ? I have QuestaSim and ModelSim for simulating with it.
Agilex™ 7 I-Series FPGA Transceiver SoC Development Kit GSRD Build
I am attempting to build the GSRD using the Intel® Agilex™ 7 I-Series FPGA Transceiver SoC Development Kit (4x F-Tile) DK-SI-AGI027FA. Quartus Version: 24.3.1 Reference Document: https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/ When running the "Build Hardware Design" procedure according to the instructions: make BOARD_TYPE=devkit_fm87 BOARD_PWRMGT=linear QUARTUS_DEVICE=AGIB027R31B1E1V ENABLE_HPS_EMIF_ECC=1 FPGA_SGPIO_EN=1 HPS_F2S_IRQ_EN=1 generate_from_tcl all It throws the following log error and fails to proceed: make[1]: *** [Makefile:817: qsys_generate_qsys] Error 1 make[1]: Leaving directory '/home/nict/p.agilex7_gsrd/gsrd.dk_si_agi027fa/agilex_soc_devkit_ghrd' make: *** [Makefile:833: generate_from_tcl] Error 2 Could you please advise what might be causing this issue, or let me know which logs (such as QSYS/Platform Designer logs) I should check?
Tranceiver Enhanced PCS Basic mode questions
Hello Guys, We used Arria GX and Straitx IV GX devices before, now we switch to use Cyclone 10 GX FPGA. I have several simple questions about XCVR's control port/signal. Why I can't see rx_control and tx_control ports when I make "Enable simplified data interface" ON? In basic or custom mode, 1 bit control signal corresponding 8-bit parallel data bits. I read XCVR user guide, it seems that only LSB 2-bits of the control bus will be used to recognize/indicate data word or control word?
LTPI IP - any plan to support OCP LTPI Revision 1.2? (MAX 10)
Hi, We are planning to purchase the Altera LTPI IP, targeting MAX 10 (Quartus Prime Standard Edition). The LTPI IP User Guide states the IP is compliant with OCP DC-SCM 2.1 LTPI revision 1.1, version 1.1 specifications. Meanwhile the OCP LTPI reference implementation has moved to Revision 1.2 (release 1.20, 12 Dec 2025), which adds extended CRC/error handling with a new Frame Lost error, renames LTPI Version to LTPI Revision (CSR packages regenerated), and changes the Link Speed timeout and Link Lost conditions. Is there a plan to update the LTPI IP to Revision 1.2? Thanks.Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Team, Quartus: Quartus Prime Pro 26.1.0 I am currently working on an Agilex 7 F-Tile transceiver configuration for a 46.6944 Gbps PAM4 application. Please find my query (Read file) as attached and provide advise.. Regards amolkumar
GTS Reset Sequencer IP o_refclk_on_ack
Hi, I am using Quartus ver 26.1 PRO Edition and investigating the GTS Reset Sequencer IP. In the figure below, o_refclk_on_ack is described as a pulse. Is there a specified minimum pulse width for this signal? For example, would it be safe to sample this pulse with a 100 MHz clock, or is there a possibility that the pulse width could be shorter than that? 3.7.6. Guidelines for Obtaining the Real-Time GTS TX PLL Lock Status
Stratix 10 fPLL is cascade source mode doesn't lock
Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal. After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1. Is there any known issue about fPLL is cascade source mode? Any suggestions about how to overcome this issue are welcomed.
