Recent Discussions
Technical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay Calibration
I am currently implementing the "single-trip delay calibration" feature using the Intel CPRI IP core. According to the User Guide (ID: 683595, Version: 2021.11.11), this feature requires the Dynamic Phase Control Unit (DPCU) block. The documentation states that "Intel provides the DPCU block with the CPRI IP." However, I am having difficulty locating this specific module. Could you please clarify where this DPCU block is located or how it should be instantiated? My design environment is as follows: Quartus Prime Version: 20.4 Pro Device Part Number: Arria 10 (10AS032H2F34I2SG) CPRI IP Version: 19.4.0 Reference Document: CPRI Intel FPGA IP User Guide (ID: 683595) Best regards!
JESD240B - No license
Hi, I am running the ADC on the Arrow DevKit – Agilex 5 E-Series AXE5 Eagle Development Platform. The converter is the EVAL-AD9695, which uses the JESD204B interface. I initially used ‘Generate Example Design’ and then adapted it for this converter. However, after making the changes and assigning the pins, I wanted to generate the final output file, but I encountered the following license error: On the licensing page, I do not see any entry for JESD204B anywhere. “What can I do to test the design? I previously worked with the Arria 10 GX, and I did not have such problems there.
Regarding MIPI CSI 2 TX
Hi, In my Project, I have to generate test pattern data and send it to MIPI CSI 2 via AXI stream, and MIPI CSI 2 will send the pixel data to link_0 of MIPI DPHY IP , but when i try to simulate the design(includes MIPI CSI 2 and MIPI DHPY IP interconnected), mipi_dphy_0/LINK0_CK_Stopstate is constantly high, I guess this signal is supposed to go low after T INT time, and also ready Singal from axi_stream is asserted low after being high for three clock cycles, i didn't understand why. Any help is appreciated.
CXL IP type2 ED failed at the final assembler stage due to unlicensed IP in Ver 25.1
Hi supprot teams, I installed Quartus Prime Pro V25.1 and generate tool lic & CXL type1/2/3 lic in SSLC. And I create a project of CXL type2 ed. After click compile button, everything goes fine until the assembler state, the report tells: Error (23714): Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com Warning (115005): Unlicensed IP: "CXL IP for Device Type 2 with Device coherency (6AF7 0185)" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/root_partition/25.1.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/root_partition/25.1.0/final/1/names.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/auto_fab_0/25.1.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/auto_fab_0/25.1.0/final/1/names.model" Error: Quartus Prime Assembler was unsuccessful. 1 error, 6 warnings And I check the license status in output_files/cxltyp2_ed.asm.rpt : +----------------------------------------------------------------------------------------+ ; Assembler Encrypted IP Cores Summary ; +------------+------------------------------------------------------------+--------------+ ; Vendor ; IP Core Name ; License Type ; +------------+------------------------------------------------------------+--------------+ ; Intel FPGA ; CXL IP for Device Type 2 with Device coherency (6AF7 0185) ; Unlicensed ; ; Intel FPGA ; Signal Tap (6AF7 BCE1) ; Licensed ; ; Intel FPGA ; Signal Tap (6AF7 BCEC) ; Licensed ; ; Intel FPGA ; Unknown (6AF7 FFFF) ; Licensed ; +------------+------------------------------------------------------------+--------------+ But in Tools -> License Setup，I can see feature "6AF7 0185" is valid. So how can I solve this problem. Regards Joseph
Agilex 7 R-Tile CXL IP Support for QoS DevLoad and PCIe ATS
Device: DK-DEV-AGI027RBES (Power Solution 2) Software Version: Quartus Prime Pro 24.3 IP Core: CXL Type-2 Hard IP Issue Description We have two questions regarding feature support in the Agilex 7 R-Tile CXL IP. 1. CXL QoS Device Load (DevLoad) According to the CXL 2.0 Specification, Section 3.3.2 (QoS Telemetry for Memory), CXL.mem supports reporting QoS Device Load (DevLoad). In the CXL IP example design, we observe that the DevLoad-related signal exists, but it is not actively used and appears to be statically tied to 0. • Is CXL.mem QoS Device Load reporting supported in the current CXL Type-2 Hard IP? • What is the expected host CPU behavior when DevLoad is asserted (e.g., bandwidth throttling, scheduling changes, or telemetry only)? 2. PCIe ATS (Address Translation Service) Requests We would like to issue PCIe ATS requests to the host using the CXL.io interface. • Does the Agilex 7 R-Tile CXL Type-2 Hard IP support generating PCIe ATS request packets? • If supported, are there any specific configuration requirements or interface signals needed to enable ATS transactions through CXL.io?
F-Tile Ethernet Hard IP Design Example - Testbench
I have a question regarding this Ftile Ethernet hard IP example Design. I am able to generate this example design for 400gbe. I am able to load this design (sof) to MA2700Kit. I was able to run tcl script and internal loopback test was successful. I was also able to run testbench basic_avl_tb_top.sv and VSIM run was successful. I have following questions and areas where I need help. At line 144 and 145 in basic_avl_tb_top.sv I can see that Tx outputs are assigned Rx input pins. I would like to understand reason for doing this? I mean shouldn’t the RX lines driven by tasks/function to simulate incoming packets over the ethernet link? I want to modify the testbench to simulate Receiving of a particular 98 byte ethernet frame, and check how mac segmented interface is behaving to communicate this frame; So i can write my custom RTL block to receive it properly. I need help developing tasks/function to simulate incoming packets over the ethernet link. Thank youF-tile-ethernet-hard-ip TX/RX MAC Segmented Client Interface
https://docs.altera.com/r/docs/683023/25.1.1/f-tile-ethernet-hard-ip-user-guide/tx-mac-segmented-client-interface "i_tx_mac_inframe" signal is explained as " Indicates valid data in each segment for specific rate. Along with the previous segment's inframe signal, this signal indicates the SOP and EOP location." i dont understand the underlined part of explanation. how does i_tx_mac_inframe indicates start of packer (SOP) and end of packet (EOP). can someone please elaborate on this with a couple of examples also another question is how to interpret i_tx_mac_data signals if i_tx_mac_valid == 1'b1 and i_tx_mac_inframe [15:0] == 16'h0 ?
