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Agilex FPGA PCIe Gen5 Example Design Simulation Error
Unsing Quartus Prime Pro Edition 21.2. Generated PCIe Gen5 1x16 native endpoint Example design. When compiling in Modelsim Intel FPGA Starter Edition 2021.1, I get the following error: Top level modules: # pcie_ed_tb # End time: 15:25:41 on Nov 08,2021, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # [exec] elab_debug # vsim -voptargs="+acc" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L tennm_ver -L tennm_hssi_ver -L tennm_hssi_f0_ver -L tennm_hssi_r0_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L tennm -L tennm_hssi -L intel_rtile_pcie_tbed_100 -L dut_pcie_tb_ip -L altera_avalon_onchip_memory2_1930 -L pcie_ed_MEM0 -L altera_s10_user_rst_clkgate_1932 -L pcie_ed_resetIP -L intel_pcie_pio_1024_191 -L pcie_ed_pio0 -L intel_rtile_pcie_ast_200 -L pcie_ed_dut -L altera_merlin_master_translator_191 -L altera_merlin_slave_translator_191 -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_avalon_sc_fifo_1930 -L altera_merlin_router_1920 -L altera_avalon_st_pipeline_stage_1920 -L altera_merlin_burst_adapter_1920 -L altera_merlin_demultiplexer_1921 -L altera_merlin_multiplexer_1921 -L altera_mm_interconnect_1920 -L pcie_ed -L pcie_ed_tb pcie_ed_tb.pcie_ed_tb # Start time: 15:25:42 on Nov 08,2021 # Loading pcie_ed_tb.pcie_ed_tb # ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_f0_ver' at "tennm_hssi_f0_ver". # No such file or directory. (errno = ENOENT) # ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_f0_ver' at "tennm_hssi_f0_ver". # No such file or directory. (errno = ENOENT) # ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver". # No such file or directory. (errno = ENOENT) # ** Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver". # No such file or directory. (errno = ENOENT) # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Instantiation of 'rtile_s20_v0' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /pcie_ed_tb/pcie_ed_inst/dut/dut File: ../../../../ip/pcie_ed/pcie_ed_dut/intel_rtile_pcie_ast_200/sim/pcie_ed_dut_intel_rtile_pcie_ast_200_arwqpni.sv Line: 63027 # Searched libraries: # C:/Pci_test/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/pcie_ed_tb/sim/mentor/libraries/intel_rtile_pcie_ast_200 # C:/Pci_test/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/pcie_ed_tb/sim/mentor/libraries/work # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/220model # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/tennm # C:/intelFPGA_pro/21.2/modelsim_ase/altera/verilog/tennm_hssi_all Seems like 'rtile_s20_v0' file is missing. Also , Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver". Error (suppressible): (vsim-19) Failed to access library 'tennm_hssi_r0_ver' at "tennm_hssi_r0_ver". Please suggest on how to fix this error?
Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
This is an issue sharing: When inserted Arria 10 PCIe Gen3 design endpoint card into a Gen4 capable Host/CPU, the PCIe link might keep cycling between L0->Recovery.Rcvlock->Recovery.Rcvconfig->Recovery.Idle->L0->Recovery.Rcvlock..... Description: Data Link Feature Exchange is not part of PCIe Gen3.0 specification, and it is an optional feature per PCIe Gen4.0 Specification. The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC. When this happens, no error is reported by the Intel® Arria® 10 FPGA. This is an expected behaviour. Resolution: To work around this problem, disable the Data Link Feature Exchange in PCIe 4.0 system BIOS [Base spec 4.0 chapter 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware.
Workflow tips in Simullink
Finally figured this out today. If you have a branching signal that you want to delete only a portion of, paste a simple block, like a sample delay, in the spot you want to snip the signal. Then delete the block. This will split the signal. If there is a better way to do this let me know. Another workflow tip. If you want to swap out two versions of a subsystem with the same inputs and outputs, use Ctrl-x to cut the first one out. Then you can drag the other one in and all the signals will automatically reconnect. This saves time over disconnecting and re-connecting each signal manually. I commonly keep multiple variations of a subsystem commented out to test changes. Anyone have similar tips?Using registers to debug in SignalTap
I've been using this technique for several months, and I'm curious if anyone else does the same or if there is a better way. When I want to track a signal in SignalTap, I do the following: Add a RegOut block to my model and give it a name like "DebugFIFODataOut". Generate DSP Builder, Qsys, and run Synthesis In SignalTap, search for *debugfifodataout* with filter set to Design Entry (all names). Drill down to the busSlaveFabric_* Insert the in_AMMregisterPortData* and in_AMMregisterPortWriteEn* Add meaningful Aliases to the signals Note that you can use the write signal on the register as well as you are not actually concerned with register itself.Qsys Avalon-MM Master BFM Tutorial for SystemVerilog and VHDL Testbenches
Hi all, I've created a tutorial showing how to use the Avalon-MM Master BFM within SystemVerilog and VHDL testbenches. https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.zip Feedback welcome! Cheers, Dave PS. If any SystemVerilog Gurus read this, Appendix A has a question for you :)DisplayPort: Transferring I2C data on AUX channel
I'd like to manage an I2C device via DisplayPort AUX channel. I connected an I2C device at the EDID I2C output of a DisplayPort sink. From the NIOSII of the DisplayPort source (using Cyclone V GX) I sent a I2C string with the command btc_dptx_aux_i2c_write(). In the nios2-terminal I can see the I2C data but the sent data are not given out at the sink I2C interface. Has anyone tried to transmit I2C data from a DP source to a DP sink via AUX channel? Are there any hints how to realize such a application?
How do I know which megafunctions require a license?
I've just downloaded and installed Quartus Prime V20.1. I'm creating a new design in System Verilog and looking at the available IP Catalog. I understand that simple functions like lpm_add, lpm_mult, altlvds_tx, altlvds_rx & altpll are free, but, there are others there which I would think are not free. Looking at the list, how do I determine which are free and which aren't? For example, is the ALTFP_MULT free? It's in the list. What about the DDR3 SDRam controller? It's also in the list and I can start it up. What's warning me if I start a design and generate/insert these cores into my project that I wasted my time and should have used something else?pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv segfault?
Start time: 17:39:56 on Dec 15,2017vlog pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017 ** Fatal: Unexpected signal: 11. ** Error: pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv(12): in protected region End time: 17:39:56 on Dec 15,2017, Elapsed time: 0:00:00 Did anybody experience this with modelsim ase in 17.1?
