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Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer?
Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does Arria® 10 HPS IP generation fail with missing mgc_common_axi.sv in Quartus® Prime Pro 24.1/24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, Arria® 10 HPS IP generation may fail with an error similar to: Error: add_fileset_file: no such file .../ip/altera/mentor_vip_ae/axi3/bfm/mgc_common_axi.sv This occurs because AXI3 Mentor Graphics BFM collateral was removed starting in Quartus Prime Pro 24.1, while the Arria 10 HPS generation flow still referenced the removed AXI3 BFM file. Associated Quartus Suite bug: QS-569165. Resolution To resolve this issue, upgrade to Quartus Prime Pro Edition Software version 24.3, regenerate the Platform Designer system/IP output files, and rerun compilation.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why am I observing .sof generation failure when selecting VSR_MODE_HIGH_LOSS in F-Tile JESD204B IP Design Examples?
Description The VSR_MODE_HIGH_LOSS option is available in the dropdown menu of the IP GUI for F-Tile JESD204B IP Design Examples. However, starting from Quartus® Prime Pro Edition Design Software version 25.3, this option is deprecated and no longer supported. With the updated F-Tile firmware starting in Quartus® Prime Pro Edition Design Software version 25.3, VSR_MODE_HIGH_LOSS and VSR_MODE_LOW_LOSS are treated equivalently. As a result, selecting VSR_MODE_HIGH_LOSS for hardware testing (e.g., on a development kit) allows the Design Example to compile successfully, but the SOF generation fails. Resolution Users should select VSR_MODE_LOW_LOSS. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.Why Does the Simplex RX/TX Design Example Fail During HSSI Support Logic Generation with a QHIP_IP_PROPERTY Case Sensitivity Error in F-Tile JESD204B IP?
Description Due to a problem in Quartus® Prime Pro Edition Design Software Version 25.3, the F-Tile JESD204B IP Simplex RX/TX example design may fail with the following error in compilation: "Cannot find QHIP_IP_PROPERTY tile_ip_sip_instances with value …..." Resolution To work around this compilation error, manually remove the QHIP_IP_PROPERTY assignment from the .qip file in the Design Example folder. Steps: Navigate to the following path in the Design Example directory: intel_jesd204b_gts_<data path>/example_design/ed_synth/ip/jesd_gts_ss<data path>/jesd_gts_ss_<data path>intel_jesd<data path>/ Open the QIP file: jesd_gts_ss_<data path>intel_jesd<data path>.qip Locate and remove the line containing the QHIP_IP_PROPERTY assignment. Save the file and retry the compilation. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.What should I consider when designing a system board using Schmitt trigger inputs on MAX® 10 FPGAs?
Description When designing a system board that uses Schmitt trigger inputs on MAX® 10 FPGAs, board-level noise, power integrity, and signal integrity can significantly affect the effective hysteresis behavior. Factors such as power supply noise, input signal noise, and PCB layout practices may cause the observed switching thresholds to deviate from their typical values. This article outlines key considerations to help minimize noise sensitivity when using Schmitt trigger inputs in a system-level design Resolution When designing a system board that uses Schmitt trigger inputs, consider the following: Follow the recommendations in the MAX® 10 FPGA Design Guidelines, especially sections related to power distribution network (PDN) and signal integrity. Minimize power supply noise by using proper decoupling, grounding, and PCB layout practices. Note: The MAX® 10 FPGA 10M08 Evaluation Kit is intended for low-cost application testing and is not designed for DC or PDN characterization. It should not be used to measure intrinsic transistor switching thresholds.Why does U-Boot fail to boot from SD Card in SD High-Speed mode in Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is different than 200 MHz in release 26.1?
Description Due to the default SD Combo Phy timing parameters assigned in the U-Boot device tree (socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex5_socdk_013b-u-boot.dtsi ) for release 26.1, U-Boot may fail to boot from the SD Card in SD-HS mode on Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is not 200 MHz (i.e. using 50 MHz). The problem lies in the fact that those default parameters are calculated using a soft PHY clock default value of 200 MHz, but the required timing parameters may differ for any other frequencies. This problem is observed mainly when the U-Boot FSBL fails to load the u-boot.itb from the SD Card, but it may also be observed when U-Boot SSBL fails to load Linux* from the SD Card. Resolution To workaround this problem, you need to enable a tuning mechanism from within the Cadence SDHCI driver by applying the attached U-Boot patch (enable_hs_tuning.patch). This tuning mechanism consists of a runtime calibration process to find the optimal data sampling point. The conditions in which this mechanism is active are: The boot device is a SD Card (no eMMC) The operation mode is SD-HS cdns,sd-hs-tuning parameter is enabled in the device tree The CONFIG_MMC_SUPPORTS_TUNING config is enabled The attached enable_hs_tuning.patch lists the updates needed to enable the tuning mechanism for a 50 MHz SOFT PHY clock. This is a temporary workaround that you could use until a proper software fix gets released. Note: The patch provided is for the Agilex® 5 DK-A5E013BM16AEA development kit (using socfpga_agilex5_socdk_013b-u-boot.dtsi). For other Agilex® 5 or Agilex® 3 FPGA production development kits, the patch solution is the same, users are recommended to apply the updates to the respective device tree file ( i.e. socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex3_socdk-u-boot.dtsi). The source code to support the tuning mechanism will be included in a future release.Why the Error Injection using Linux* debugfs interface does not work for SDMMC ECC Port B?
Description Due to a problem in the EDAC (Error Detection and Correction) driver, the Error Injection using Linux* debugfs interface on SDMMC ECC Port B is not functioning. The error injection command below does not write to INIT test register as intended. echo C > /sys/kernel/debug/edac/sdmmca-ecc/altr_trigger As comparison, when writing directly to the INITTEST register, single bit error interrupt is shown to be working. root@agilex7dksiagf014eb:~# devmem2 0xFF8C8C26 h 0x1 ----- /dev/mem opened.[ 1785.685802] EDAC DEVICE6: CE: Altera ECC Manager instance: sdmmcb-ecc0 block: sdmmcb-ecc0 count: 1 'sdmmcb-ecc' This issue is impacting Agilex® 7 SoC FPGA devices and Quartus® Prime software of version 25.3.1 and older. Resolution To workaround this issue, apply the patch by following the instructions below: git clone the repo https://github.com/altera-fpga/linux-socfpga/commits/socfpga-6.18.2-lts/ run: git format-patch-1 Make sure the commit is included in the patch: https://github.com/altera-fpga/linux-socfpga/commit/be94a41dfaf7e124a5547ac8948b36f097a73c90 Use “git am” to apply the patch onto your source code. Additional Information This issue is fixed in Quartus Prime software version 26.1 onwards.
