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Why is there a mismatch in the PFC width between the theory calculation and the hardware measurement in the GTS Ethernet Hard IP design?
Description You might observe a mismatch in the PFC width between the theory calculation and hardware measurement at max PFC quanta. This is due to the alignment marker (AM) pulse window within the PCS data, which is causing this variation. Resolution Estimating the deviation of the PFC width from the expected value is not feasible. Quanta variation is not quantifiable, and the variation is expected. There is no plan to fix this problem.Why is the o_rx_pfc port enabled for longer durations than expected with 10/25GE designs using the GTS Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description When operating the GTS Ethernet FPGA Hard IP for 10/25GE with PFC enabled, the o_rx_pfc port stays asserted beyond the configured quanta time whenever all of the following conditions are fulfilled: During the processing state of “PAUSE”, if new oversized frame is received Frame size larger than configured “maximum frame size” during the design generation in GTS Ethernet Hard IP. “Enforce maximum frame size” option is enabled in GTS Ethernet FPGA Hard IP GUI. The typical effect is an extended pause prior to resuming packet flow Resolution When enabled the “Forward RX pause requests” option in GTS Ethernet Hard IP GUI, disable the “enforce maximum frame size” option. There is no plan to fix this problem.Why does the GTS JESD204B IP and GTS JESD204C IP with HVIO PLL clocking mode enabled failed the Quartus® Fitter compilation?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may observe the following error during Fitter compilation: "One or more blocks are configured incorrectly and will not have the desired functionality. --bcm instance name: hvio_1_1" This error occurs because Quartus® automatically assigns the hvio_refclk* port to an illegal location during placement. Resolution To work around this problem, you can manually assign the hvio_refclk* port to a HVIO bank. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the Quartus® Logic Generation Tool report the TX Equalizer settings as 'Ignored' when creating a Tx-only example design for F-Tile JESD204C IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.4, you may observe the Quartus Logic Generation Tool incorrectly reports the TX Equalizer settings as 'Ignored' when creating a TX-only example design for F-Tile JESD204C IP. Resolution To work around this problem, you can manually configure the analog parameter instances in the .qsf file. set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=<parameters value>” -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to tx_serial_data[*] set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=< parameters value >" -to "tx_serial_data_n[*]" set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=< parameters value >" -to "tx_serial_data_n[*]" This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1.Why are the SDC constraints for link clocks generated by the GTS JESD204B FPGA IP inaccurate?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may observe incorrect SDC constraints for link clocks generated by the GTS JESD204B FPGA IP. Resolution To work around this problem, update the value of period in the following constraints in ip/intel_jesd204b_gts_phy_<version>/synth/j204b_gts.sdc: create_clock -name "rxlink_clk" -period <period>ns [get_ports rxlink_clk] create_clock -name "txlink_clk" -period <period>ns [get_ports txlink_clk] where <period> is the calculated value of 1/(data rate/40). This problem has been fixed in the Quartus® Prime Pro Edition software version 24.3.1.Why do I see the wrong IP parameter in Agilex™ 5 FPGA E-Series GTS HDMI IP file after generation from GUI?
Description You may see wrong ipxact parameter (PIXELS_PER_CLOCK/HDMI21_VARIANT) in IP file Resolution Workaround is to open the IP file by text editor and change the ipxact parameter (PIXELS_PER_CLOCK/HDMI21_VARIANT) as attached file and generate the IP again.What is the difference between SDI configuration compared to SDI_NATIVE and SDI_STATIC configurations in the F-tile PMA/FEC Direct PHY IP and F-tile PMA/FEC Direct PHY Multirate IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, the F-tile PMA/FEC Direct PHY IP and F-tile PMA/FEC Direct PHY Multirate IP has incorrectly displayed the SDI_NATIVE and SDI_STATIC configuration as part of the FGT PMA configuration rules parameter options. These options are not applicable and should not be used when you are operating configuration rules in SDI mode. Resolution To work around this problem in the Quartus Prime Pro Edition software version 25.3.1, you should select the SDI configuration under the F-tile PMA/FEC Direct PHY IP and F-tile PMA/FEC Direct PHY Multirate IP and apply the below HSSI QSF assignment in your Quartus Setting Files (.qsf). Ensure the correct HSSI QSF assignment is being added following the parameters/configurations listed in the table. FGT PMA Configuration Rules PMA Mode Adaptation Mode Action required for user: Update HSSI QSF Assignment in .qsf file SDI TX Simplex RX Simplex Duplex Manual (for Data Rate <7Gbps i.e. 1.485/1.4835 Gbps 2.97/2.967 Gbps 5.94 Gbps) Update QSF file to add in RX_TUNING_HINT_SDI_STATIC tuning hint. This HSSI QSF assignment need to be set for every F-tile PMA/FEC Direct PHY IP instances in the design for all TX Simplex instances, RX Simplex instances or Duplex instances. set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=TX_TUNING_HINT_SDI_STATIC" -to <instance> set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_SDI_STATIC" -to <instance> exm: set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_SDI_STATIC" -to rx_inst|sdi_mr_rx_sys_inst|rx_phy|rx_phy|U_sec_profile2|sec_profile_2|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Native (for Data Rate > 7Gbps i.e. 11.880 Gps) 1. Update QSF file to add in RX_TUNING_HINT_SDI_NATIVE tuning hint. This HSSI QSF assignment need to be set for every F-tile PMA/FEC Direct PHY IP instances in the design for every TX Simplex instances, RX Simplex instances or Duplex instances. set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=TX_TUNING_HINT_SDI_NATIVE" -to <instance> set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_SDI_NATIVE" -to <instance> exm: set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_SDI_NATIVE" -to rx_inst|sdi_mr_rx_sys_inst|rx_phy|rx_phy|U_base_profile|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx 2. Update QSF file to add in rxeq_vga_gain=37 setting. This HSSI QSF assignment is required to be set for every F-tile PMA/FEC Direct PHY IP RX Simplex instances or Duplex instances. set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=37" -to <instance> exm: set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=37" -to rx_inst|sdi_mr_rx_sys_inst|rx_phy|rx_phy|U_base_profile|directphy_f_0 |dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.What is the difference between HDMI configuration compared to HDMI_NATIVE and HDMI_STATIC configurations in the F-tile PMA/FEC Direct PHY IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, the F-tile PMA/FEC Direct PHY IP has incorrectly displayed the HDMI_NATIVE and HDMI_STATIC configuration as part of the FGT PMA configuration rules parameter options. These options should not be used when you are operating in HDMI mode. Resolution To work around this problem In the Quartus Prime Pro Edition software version 25.3.1, you should select the HDMI configuration under the F-tile PMA/FEC Direct PHY IP and apply the below HSSI QSF assignment in your Quartus Setting Files (.qsf). Ensure the correct HSSI QSF assignment is being added following the parameters/configurations listed in the table. FGT PMA Configuration Rules PMA Mode Adaptation Mode Action required for user: Update HSSI QSF Assignment in .qsf file HDMI RX Simplex TX Simplex Manual (for Data Rate: 3Gbps, 6Gbps) Update QSF file to include add in TX/RX_TUNING_HINT_HDMI_STATIC tuning hint. This HSSI QSF assignment need to be set for every F-tile PMA/FEC Direct PHY IP instances in the design for every TX Simplex instance or RX Simplex instance in your design. set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=RX_TUNING_HINT_HDMI_STATIC" -to <instance> set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=TX_TUNING_HINT_HDMI_STATIC" -to <instance> exm: set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=TX_TUNING_HINT_HDMI_NATIVE" -to u_hdmi_tx_top|gxb_tx_inst|u_tx_phy_3|tx_phy_6g|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -entity agx_hdmi21_frl_demo exm: set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_HDMI_NATIVE" -to u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_3|rx_phy_6g|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity agx_hdmi21_frl_demo Native (for Data Rate: 8Gbps, 10Gbps, 12Gbps) 1. Update QSF file to add in TX/RX_TUNING_HINT_HDMI_NATIVE tuning hint. This HSSI QSF assignment need to be set for every F-tile PMA/FEC Direct PHY IP instances in the design for every TX Simplex instance or RX Simplex instance in your design. set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=RX_TUNING_HINT_HDMI_NATIVE" -to <instance> set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=TX_TUNING_HINT_HDMI_NATIVE" -to <instance> exm: set_instance_assignment -name HSSI_PARAMETER "TX_TUNING_HINT=TX_TUNING_HINT_HDMI_NATIVE" -to u_hdmi_tx_top|gxb_tx_inst|u_tx_phy_0|tx_phy_12g|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx -entity agx_hdmi21_frl_demo exm: set_instance_assignment -name HSSI_PARAMETER "RX_TUNING_HINT=RX_TUNING_HINT_HDMI_NATIVE" -to u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity agx_hdmi21_frl_demo 2. Update QSF file to add in rxeq_vga_gain=37 setting. This HSSI QSF assignment need to be set for every F-tile PMA/FEC Direct PHY IP instances in the design for every RX Simplex instances. set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=37" -to <rx_instance>. exm: set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=37" -to u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity agx_hdmi21_frl_demo This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why aren’t HSSI analog parameter values set in the GTS PMA registers when these values are enabled and set in the PMA/FEC Direct PHY IP GUI?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, HSSI analog parameter values listed below aren’t reflected in the GTS PMA registers even you set these analog parameters in the GTS PMA/FEC Direct PHY IP GUI. Enable RX P&N Invert, Enable TX P&N Invert RX External Coupling Mode Selects value of RX On-chip Termination Resolution To overcome the problem, you can use the QSF setting methodology to set the analog parameters in your .qsf file for both the RX on-chip termination and RX External Coupling Mode settings. For TX and RX polarity inversion pins, you can follow the PMA/FEC Direct PHY IP User Guide on the GTS Attribute access method to change the TX and RX polarity pins. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.Why does the Multi Channel DMA for PCI Express* FPGA IP fail to upgrade in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a name change in the PIO Example Design from “PIO using MQDMA Bypass mode” to “PIO using MCDMA Bypass mode”, designs that include the Multi Channel DMA for PCI Express* FPGA IP created in Quartus® Prime Pro Edition Software versions earlier than 25.3 may fail to generate HDL when performing an automatic IP upgrade. When this problem occurs, the following system error messages appear in the IP Parameter Editor Pro window: Error: intel_pcie_ftile_mcdma_0.intel_pcie_ftile_mcdma_0: "Based on parameterization, the generated example design for PCIe0 will be" (select_design_example_hwtcl) "PIO using MQDMA Bypass mode" is out of range: "Device-side Packet loopback", "PIO using MCDMA Bypass mode", "Packet Generate/Check", "AVMM DMA", "Traffic Generator/Checker", "External Descriptor Controller", "BAM SRIOV" Resolution Workaround: To work around this problem, follow the steps below: Manually update the .ip file in your project by replacing all instances of “PIO using MQDMA Bypass mode” with “PIO using MCDMA Bypass mode.” Save the updated .ip file. Reopen the modified .ip file in the Quartus® IP Parameter Editor. Depending on your use case, click “Generate Example Design” or “Generate HDL.”