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Why USB-Blaster II does not work after closing the Quartus® Programmer Hardware Setup window?
Description When using Quartus® Prime Standard Edition to program a MAX® 10 FPGA device with a USB-Blaster II, changing the Hardware Setup frequency from the default 24 MHz to 16 MHz and then closing the Hardware Setup window with the Close button may cause the USB-Blaster II to stop functioning. Resolution Here are some practical solutions you can try to resolve the issue: 1. Restart the JTAG server. jtagserver --stop jtagserver --start 2. Unplug and replug the USB-Blaster II. 3. Kill lingering processes such as the JTAG server or Quartus Programmer process. jtagserver.exe quartus_pgm.exe 4. Change the clock frequency of the USB-Blaster II download cable to lower frequency like 16Mz and 6Mz. Related KDB: How do I change the clock frequency of the USB-Blaster II download cable? | Altera Community - 342304 5. Avoid USB conflicts by disconnecting other USB serial devices, especially FTDI or USB-UART adapters, and avoid opening COM ports or serial terminal applications while programming. 6. Try a different USB port and connect the USB-Blaster II directly to the PC instead of through a USB hub. 7. Reinstall the driver from the Quartus installation folder or try an older or known-stable driver version. 8. Avoid mixing drivers from multiple Quartus versions. 9. If a USB hub is required, avoid poor-quality or legacy USB 1.0 hubs. 10. If a clone USB-Blaster is being used, replace it with a known-good cable. 11. If none of the above steps recover the problem, reboot the system. Possible root causes: 1. JTAG server gets stuck and keeps the USB-Blaster II claimed. The device can appear normal in the operating system but remain inaccessible from Quartus Programmer. Restarting Quartus alone often does not recover the cable. Fix: jtagserver --stop jtagserver --start Or kill the process via Task Manager. 2. USB or driver conflicts with other devices. Conflicts with other devices, especially FTDI or USB-UART adapters, can break the USB-Blaster II mid-session. Opening a serial terminal can trigger the failure. This behavior is reported more often on Windows 64-bit systems. Fix: Disconnect other USB serial devices. Avoid opening COM ports or serial terminal applications while programming. Try a different USB port with a direct connection instead of a USB hub. 3. Driver bugs or Quartus version mismatches. Driver bugs or Quartus version mismatches can prevent Quartus Programmer from detecting the cable. Known bad driver versions or incompatible Quartus releases can cause the Programmer to lose the cable or prevent the standalone Programmer from detecting it. Fix: Reinstall the driver from the Quartus installation folder. Try an older or known-stable driver version. Avoid mixing drivers from multiple Quartus versions. 4. USB hub or signal quality problems. USB hub or signal quality problems can cause the USB-Blaster II to disappear after use. This is reported more often with poor-quality hubs or legacy USB 1.0 hubs. Fix: Plug the USB-Blaster II directly into the PC. Avoid poor-quality or legacy USB 1.0 hubs. 5. Clone USB-Blaster hardware. Clone USB-Blaster hardware can be unstable due to timing issues, firmware quirks, or driver incompatibilities. Fix: Replace the clone USB-Blaster with a known-good cable. 6. Closing Quartus Programmer leaves the cable in a bad state. Closing Quartus Programmer can leave the JTAG server running. It can leave the device handle locked. It can trigger USB re-enumeration issues on the USB stack. When Quartus Programmer is reopened, it may not be able to reattach to the already claimed cable. Fix: Unplug and replug the USB-Blaster II. Kill lingering JTAG server or Quartus Programmer processes. Reboot the system if the cable is still not detected.Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the R-tile AXI Multichannel DMA IP for PCI Express* Example Design (AXI-S Packet Generate/Check variant) generation fail with Enable User MSI-X IP is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3, 25.3.1 and 26.1, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User MSI-X option is selected under the PCIe Settings --> MCDMA Settings tab The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: add_connection GEN_CHK_M0.usr_msix DUT.user_msix: Cannot connect GEN_CHK_M0.usr_msix to DUT.user_msix. Error: Failed to generate example design example_design to: <path> This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User MSI-X option is selected. Resolution To work around this problem, do not select the Enable User MSI-X option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* Example Design. There is no other workaround for Quartus Prime Pro Edition Software versions 25.3, 25.3.1, and 26.1. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example with the Packet Generate/Check variant may fail when using the Siemens Questa* simulator. The failure is observed after the DMA queue reset sequence finishes, and a PIO register write is issued. Simulation then stalls with no further activity and terminates with an inactivity timeout after some time. An example of the messages observed in the simulation log is shown below: INFO: 43000 ns H2D: Got Status for Channel 0 INFO: 43000 ns D2H: Performing Channel 0 Queue Reset INFO: 47000 ns D2H: Channel 0 Queue Reset...done INFO: 47000 ns PIO_WRITE_REG 8000000100001000 FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! ** Note: $stop : ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v(146) Time: 4 ms Iteration: 3 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/u1/rp/inst/apps/genblk1/drvr Break at ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v line 146 This issue affects simulation only and does not impact hardware functionality. Resolution To work around this problem, generate the F-Tile Multi Channel DMA FPGA IP for PCI Express Design Example (Packet Generate/Check variant) and run simulation using Quartus® Prime Pro Edition Software version 25.1.1. The problem is not observed in that release. There is no other workaround for Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design generation fail with Enable User FLR is selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3 and later, Example Design generation fails for the R-Tile AXI Multichannel DMA IP for PCI Express* when: AXI-S Packet Generate/Check mode is selected Enable User FLR option is selected under the PCIe Settings --> MCDMA Settings tab. The problem is observed a few minutes after clicking the Generate Example Design button. Quartus® Prime Pro Edition Software reports an error in the Generate Example Design Completed window and the Example Design is not generated successfully. An example of the message observed in the Generate Example Design Completed window is shown below: Error: pcie_axi_mcdma_0: Fail .qsys synthesis generation Error: pcie_axi_mcdma_0: Unable to generated HDL Files for the system .qsys Error: Failed to generate example design example_design to: <path> Generate Example Design: completed with errors. This problem applies only to the AXI-S Packet Generator/Checker variant of the Example Design. The AXI Multichannel DMA IP itself can still be generated successfully when the Enable User FLR option is selected. Resolution To work around this problem, do not select the Enable User FLR option when generating the R-Tile AXI Multichannel DMA IP for PCI Express* AXI-S Packet Generate/Check Example Design. There is currently no other workaround for Quartus® Prime Pro Edition Software versions 25.3 and later. This problem is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Agilex® 7 FPGA M-Series fail to launch U-Boot proper after a Warm reset in release 25.3.1 and later?
Description Due to corruption in the device tree on the Warm reset flow in the Agilex® 7 FPGA M-Series device, the resolution of the u-boot,spl-boot-order = &mmc node fails at the re-entry of the U-Boot SPL, resulting in the loading of the U-Boot proper failing. The error observed is the following: Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # reset -w resetting ... Do warm reset now... U-Boot SPL 2025.10 (Dec 11 2025 - 10:49:42 +0000) Reset state: Warm (Triggered by MPU 0) MPU 1350000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 50000 kHz HBM: SDRAM init in progress ... HBM: Calibration success HBM: Warning: DRAM size from device tree (2048 MiB) mismatch with hardware (4096 MiB). HBM: 2048 MiB HBM: size check success HBM: firewall init success HBM init success board_boot_order: no valid element spl-boot-order list SPL: failed to boot from all boot devices ERROR ### Please RESET the board This problem is observed regardless of the method used to apply the Warm reset, and this is present in release 25.3.1 and later. Resolution There is no workaround for this problem. This will be fixed in a future release.Why does the simulation of my Altera® AXI BFMs fail?
Description In the Quartus® Prime Pro Edition Software, a VHDL testbench generated by Visual Designer Studio or Platform Designer using Altera® AXI BFM will error out. The Altera AXI BFMs only support testbenches generated in Verilog HDL or System Verilog HDL. In the Siemens* Questa* Simulator, the error message may be similar to this: ** Error: <file name>.vhd: (vcom-1598) Library "<library name>" not found. Resolution To avoid this problem, generate the testbench in Verilog HDL or System Verilog HDL.Why is Agilex® 5 FPGA HPS IP's Auto-Place IP failed to place the selected peripheral after Apply Selections ?
Description When assigning peripherals to the HPS IO, you may encounter a placement limitation due to the peripheral cannot fit into the available unused IO locations. The error message is not displayed in the Parameterization Messages but appears in the Messages window after running Auto-Place IP. This snapshot is an example: Resolution This problem is plan to be fix in Quartus® Prime Pro Edition Software v26.1.Why do I get Error (169059) when compiling for MAX® 10 FPGA (Dual Supply) B610 package with 1.0 V I/O standard?
Description In Quartus® Prime Standard Edition 25.1 and earlier, compiling a design targeting MAX® 10 dual power supply devices of the B610 package fails when the design uses a 1.0 V I/O standard assignment. Observed error: Error (169059) The MAX® 10 FPGA General Purpose I/O User Guide indicates that the 1.0 V LVCMOS I/O standard is available only for specific device combinations, and the dual power supply devices of the B610 package are part of that. Resolution This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
