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Why am I observing .sof generation failure when selecting VSR_MODE_HIGH_LOSS in F-Tile JESD204B IP Design Examples?
Description The VSR_MODE_HIGH_LOSS option is available in the dropdown menu of the IP GUI for F-Tile JESD204B IP Design Examples. However, starting from Quartus® Prime Pro Edition Design Software version 25.3, this option is deprecated and no longer supported. With the updated F-Tile firmware starting in Quartus® Prime Pro Edition Design Software version 25.3, VSR_MODE_HIGH_LOSS and VSR_MODE_LOW_LOSS are treated equivalently. As a result, selecting VSR_MODE_HIGH_LOSS for hardware testing (e.g., on a development kit) allows the Design Example to compile successfully, but the SOF generation fails. Resolution Users should select VSR_MODE_LOW_LOSS. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.Why Does the Simplex RX/TX Design Example Fail During HSSI Support Logic Generation with a QHIP_IP_PROPERTY Case Sensitivity Error in F-Tile JESD204B IP?
Description Due to a problem in Quartus® Prime Pro Edition Design Software Version 25.3, the F-Tile JESD204B IP Simplex RX/TX example design may fail with the following error in compilation: "Cannot find QHIP_IP_PROPERTY tile_ip_sip_instances with value …..." Resolution To work around this compilation error, manually remove the QHIP_IP_PROPERTY assignment from the .qip file in the Design Example folder. Steps: Navigate to the following path in the Design Example directory: intel_jesd204b_gts_<data path>/example_design/ed_synth/ip/jesd_gts_ss<data path>/jesd_gts_ss_<data path>intel_jesd<data path>/ Open the QIP file: jesd_gts_ss_<data path>intel_jesd<data path>.qip Locate and remove the line containing the QHIP_IP_PROPERTY assignment. Save the file and retry the compilation. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1.What should I consider when designing a system board using Schmitt trigger inputs on MAX® 10 FPGAs?
Description When designing a system board that uses Schmitt trigger inputs on MAX® 10 FPGAs, board-level noise, power integrity, and signal integrity can significantly affect the effective hysteresis behavior. Factors such as power supply noise, input signal noise, and PCB layout practices may cause the observed switching thresholds to deviate from their typical values. This article outlines key considerations to help minimize noise sensitivity when using Schmitt trigger inputs in a system-level design Resolution When designing a system board that uses Schmitt trigger inputs, consider the following: Follow the recommendations in the MAX® 10 FPGA Design Guidelines, especially sections related to power distribution network (PDN) and signal integrity. Minimize power supply noise by using proper decoupling, grounding, and PCB layout practices. Note: The MAX® 10 FPGA 10M08 Evaluation Kit is intended for low-cost application testing and is not designed for DC or PDN characterization. It should not be used to measure intrinsic transistor switching thresholds.Why does U-Boot fail to boot from SD Card in SD High-Speed mode in Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is different than 200 MHz in release 26.1?
Description Due to the default SD Combo Phy timing parameters assigned in the U-Boot device tree (socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex5_socdk_013b-u-boot.dtsi ) for release 26.1, U-Boot may fail to boot from the SD Card in SD-HS mode on Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is not 200 MHz (i.e. using 50 MHz). The problem lies in the fact that those default parameters are calculated using a soft PHY clock default value of 200 MHz, but the required timing parameters may differ for any other frequencies. This problem is observed mainly when the U-Boot FSBL fails to load the u-boot.itb from the SD Card, but it may also be observed when U-Boot SSBL fails to load Linux* from the SD Card. Resolution To workaround this problem, you need to enable a tuning mechanism from within the Cadence SDHCI driver by applying the attached U-Boot patch (enable_hs_tuning.patch). This tuning mechanism consists of a runtime calibration process to find the optimal data sampling point. The conditions in which this mechanism is active are: The boot device is a SD Card (no eMMC) The operation mode is SD-HS cdns,sd-hs-tuning parameter is enabled in the device tree The CONFIG_MMC_SUPPORTS_TUNING config is enabled The attached enable_hs_tuning.patch lists the updates needed to enable the tuning mechanism for a 50 MHz SOFT PHY clock. This is a temporary workaround that you could use until a proper software fix gets released. Note: The patch provided is for the Agilex® 5 DK-A5E013BM16AEA development kit (using socfpga_agilex5_socdk_013b-u-boot.dtsi). For other Agilex® 5 or Agilex® 3 FPGA production development kits, the patch solution is the same, users are recommended to apply the updates to the respective device tree file ( i.e. socfpga_agilex5_socdk-u-boot.dtsi, socfpga_agilex3_socdk-u-boot.dtsi). The source code to support the tuning mechanism will be included in a future release.Why the Error Injection using Linux* debugfs interface does not work for SDMMC ECC Port B?
Description Due to a problem in the EDAC (Error Detection and Correction) driver, the Error Injection using Linux* debugfs interface on SDMMC ECC Port B is not functioning. The error injection command below does not write to INIT test register as intended. echo C > /sys/kernel/debug/edac/sdmmca-ecc/altr_trigger As comparison, when writing directly to the INITTEST register, single bit error interrupt is shown to be working. root@agilex7dksiagf014eb:~# devmem2 0xFF8C8C26 h 0x1 ----- /dev/mem opened.[ 1785.685802] EDAC DEVICE6: CE: Altera ECC Manager instance: sdmmcb-ecc0 block: sdmmcb-ecc0 count: 1 'sdmmcb-ecc' This issue is impacting Agilex® 7 SoC FPGA devices and Quartus® Prime software of version 25.3.1 and older. Resolution To workaround this issue, apply the patch by following the instructions below: git clone the repo https://github.com/altera-fpga/linux-socfpga/commits/socfpga-6.18.2-lts/ run: git format-patch -1 Use “git am” to apply the patch onto your source code. Additional Information This issue is fixed in Quartus Prime software version 26.1 onwards.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why are some simulation library files missing when compiling for Questasim*?
Description Due to a problem in Simulation Library Compiler in the Quartus® Prime Standard Edition Software 23.1 and later, you may see some Quartus® Simulation Library source files not included for compilation for Siemens* Questasim* Tool selection. This problem persists on both EDA Simulation Library Compiler GUI and command line versions. This problem only exists in Quartus® Prime Standard Edition and does not affect Quartus® Prime Pro Edition versions. Resolution To work around this problem, follow these steps: 1. Edit file: <QUARTUS INSTALLATION DIRECTORY>/quartus/common/tcl/internal/simlib_comp.tcl 2. Replace: set gl(primary_tool,questasim) questasim With: set gl(primary_tool,questasim) modelsim This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why do I see CRC Error for the Agilex® 5 HPS EMAC when operating at -40°C
Description When operating the Agilex® 5 FPGA Device at temperature of -40°C, you may see consistent CRC Error for Hard Processor EMAC, this is due to the uncalibrated IO Delay value for the the EMAC and the PHY. Resolution The IO Delay between the EMAC and PHY would require calibration as the values varies for different board design. Please follow the workflow summary to identify the optimal timing margin: (Applicable to all OPN supporting different voltage and temperature range) Configure Delay: Write the desired delay value to the IO Delay control registers for the Transmit and Receive Clock pins of the RGMII interface. (refer to schematic or design to identify the IO pins) Verify Link: Ensure the Ethernet interface is up (supports 10/100/1000 Mbps). Ethernet Data Transfer Test: Perform a data transfer (e.g., a ping test with a high packet count). Analyze Errors, check for: Packet Loss: Dropped packets during transit. CRC Errors: Integrity issues in the received data. Repeat: Iterate through all possible delay combinations to identify the "passing window". Select: Choose a setting in the center of the passing range to ensure maximum hardware margin. Additional Information For more details or help on the calibration workflow, please contact Altera® technical support.9Views0likesWhat is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1?
Description The latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1 can be downloaded from the following links. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 1.33fw: Fixed race condition in handling SHA isr and resumption of FPGA data blocks.Drain DMA post a configuration/PR to flush out left over data if any. Firmware version 1.22fw: Enabled 85 Ohm Rx Termination for PCIe designs. Resolved problem related to Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT having link up issue Resolved problem related to IEEE 802.3-2022 50GBASE-KR compliance testing marginality during Link Training (LT). Resolved problem related to FGT transceivers using certain FGT Attribute Access method sequence hanging. Firmware version 1.15fw: Added Safe SEU error injection mailbox command. Please also see the following links: Updating the SDM Firmware in the Agilex® FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.Why are Toolkit instances (ETK, TTK) not detected for Agilex® 7 F-Tile Ethernet Hard IP in System-console after device configuration?
Description In designs using multiple instances of the Agilex® 7 F-Tile Ethernet Hard IP with Toolkit support enabled (ETK and TTK), the Toolkit instances may sometimes not be detected in the System Console GUI after programming the FPGA with the design .sof file. This behavior is caused by a problem in the F-Tile Ethernet Hard IP configuration. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 25.3.1. Download and apply attached patch 1.32, which restores Toolkit visibility in the System Console GUI for the F-Tile Ethernet Hard IP. This problem is scheduled to be fixed in a future release of Quartus Prime Pro Edition software.
