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Why is Agilex® 5 and Agilex® 3 FPGA External Memory Interfaces (EMIF) IP missing from the BSP Linker when the Nios® V processor Board Support Package is generated?
Description Due to a problem in the Quartus ® Prime Pro Edition starting since software version 24.1, the Agilex ® 5 and Agilex ® 3 FPGA EMIF IP is missing from the BSP Linker when generating the Board Support Package. This might occur for Nios ® V processor designs targeting Agilex 5 FPGA or Agilex 3 FPGA, that uses EMIF IP. This is because Agilex 5 and Agilex 3 FPGA EMIF IP are missing the isMemoryDevice agent information. Refer to Nios® V Processor Software Developer Handbook - Memory-Mapped Slave Information (PDF) for information about isMemoryDevice agent information. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 5 FPGAs and SoCs (PDF) for information Agilex ® 5 FPGA EMIF IP. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 3 FPGAs and SoCs (PDF) for information Agilex ® 3 FPGA EMIF IP. Resolution To work around this problem in the Quartus ® Prime Pro Edition in all the affected software version, apply either one of the following workarounds: Workaround 1: Manually add isMemoryDevice to the EMIF IP (in Platform Designer only) Select the s*_axi4 signal (mainband AXI4 from fabric to controller) that connects to the Nios ® V processor’s instruction/data manager. Right-click, and click Edit Component Instantiation ... Select s*axi4 and edit the Assignments. Enter new Key as embeddedsw.configuration.isMemoryDevice, and Value as 1. Save the new assignment. Generate a new BSP. Workaround 2: Manually define EMIF IP linker memory device Refer to the Nios V Embedded Processor Design Handbook - Defining Address Span Extender Linker Memory Device. The example demonstrates how to manually define Address Span Extender linker memory device. For this problem, apply the same procedure but on the EMIF IP directly. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software. Related Articles LPDDR4 not available in NIOS® V/g linker script - Agilex® 5 FPGA, Quartus® 26.1 Pro Issue with BSP Creation for Nios® V/m Using LPDDR4 on Agilex® 5 FPGA (Quartus® 24.1 & 24.3.1)Why does the GTS AXI Multichannel DMA IP for PCI Express* IP send Completion Data (CplD) with a length exceeding the Maximum Payload Size (MPS) set?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the GTS AXI Multichannel DMA IP for PCI Express* IP sends Completion with Data (CplD) lengths that exceed the negotiated Maximum Payload Size (MPS) set. Resolution Patches are available to fix this problem for the Quartus Prime Pro Edition Software version 26.1 versions. Download and install patch below. Quartus Prime Pro Edition Software v26.1 Patch 0.20 This problem is currently scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why do I see a simulation failure with the F-Tile Multi Channel DMA IP for PCI Express* Design Example using the Quartus® Prime Pro Edition Software version 26.1 ?
Description Due to a problem in the Quartus Prime Pro Edition Software version 26.1, you may encounter simulation errors with the F-Tile Multi Channel DMA IP for PCI Express* Design Example. Synopsys VCS/VCS-MX: Error-[SE] Syntax error Following verilog source has syntax error : "./../..//pcie_ed_sim_tb.v", 2015: token is ')'... Error-[TMENF-IL] Top Module/Entity not found Top module/entity/config "pcie_ed_sim_tb.pcie_ed_sim_tb" is not found in library "PCIE_ED_SIM_TB". Error-[NM] No modules defined No modules defined in current design file(s). Siemens Questasim: ** Error: /mentor/questasim/2025.3/linux64/linux_x86_64/qrun failed. Error in macro ./run_msim_setup.tcl line 52 Cadence Xcelium: xmelab: *E,NOUNIT: Unable to find a unit named 'pcie_ed_sim_tb.pcie_ed_sim_tb' in the libraries. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_sim_tb.pcie_ed_sim_tb' does not exist in the libraries. Aldec Riviera-Pro: Error: VCP2000 .../pcie_ed_sim_tb/pcie_ed_sim_tb/sim/pcie_ed_sim_tb.v : (1951, 6): Syntax error. Unexpected token: ). This problem is attributed to a limitation in the provided simulation testbench within this software release. It is important to note that this behavior is confined to the simulation environment and does not impact the functionality or performance of the design on hardware. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer?
Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does Arria® 10 HPS IP generation fail with missing mgc_common_axi.sv in Quartus® Prime Pro 24.1/24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, Arria® 10 HPS IP generation may fail with an error similar to: Error: add_fileset_file: no such file .../ip/altera/mentor_vip_ae/axi3/bfm/mgc_common_axi.sv This occurs because AXI3 Mentor Graphics BFM collateral was removed starting in Quartus Prime Pro 24.1, while the Arria 10 HPS generation flow still referenced the removed AXI3 BFM file. Associated Quartus Suite bug: QS-569165. Resolution To resolve this issue, upgrade to Quartus Prime Pro Edition Software version 24.3, regenerate the Platform Designer system/IP output files, and rerun compilation.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
