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Why does the Linux shows "Cannot enable. Maybe the USB cable is bad?" error message when a USB 3.1 thumb-drive is plugged-in?
Description In Quartus® Prime software of version 25.3 and older, you may see the error message “Cannot enable. Maybe the USB cable is bad?” when a USB 3.1 thumb-drive is plugged-in. This is due to an incorrect Phase Locked-Loop Bandwidth configuration in PMA direct mode for USB, which caused the instability in USB 3.1 link layer when reaching the U0 state. This issue has been fixed in the newer Quartus® software releases. Resolution To solve this issue, upgrade your Quartus® software to Quartus® Prime Pro 25.3.1 version or newer versions.What does the i_txclkdivrate input port in the GTS PMA/FEC Direct PHY IP do when SATA/SAS configuration rules are selected?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, the i_txclkdivrate input port to be unintentionally exposed when SATA/SAS mode is selected via the PMA configuration rules in the GTS PMA/FEC Direct PHY IP. This port does not require user control when operating in SATA/SAS mode. Resolution To work around this problem, you can tie this port to GND (ground) when operating in SATA/SAS mode. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. The port will be removed and will be controlled internally by the GTS PMA/FEC Direct SIP.Why does the slew rate value become unset after upgrading External Memory Interfaces (EMIF) IP in Agilex™ 7 FPGA F-Series and I-Series devices?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, the slew rate values in the FPGA I/O tab of External Memory Interfaces (EMIF) IP might change to unset after upgrading the IP to a newer version. Resolution To work around this problem, follow these steps: Toggle the Use default I/O settings checkbox. Change slew rate to desired settings. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1.Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see hold timing violations during Timing Analyzer when using the SPI (4 Wire Serial) IP. The SPI IP generates an SDC file that includes the following incorrect constraint: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This constraint can cause hold timing violations between the spi_gen_clk and the external clock, making timing closure difficult—especially in designs with multiple SPI instances. This problem does not occur in the Quartus® Prime Standard Edition Software, where such an SDC constraint is not generated for the SPI IP. Resolution To work around this problem: Remove the incorrect constraint from the IP-generated SDC file: Delete the following line: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Internal Error: Sub-system: QPR, File: /quartus/comp/qpr/qpr_route_mask_generator_details.h, Line: 594
Description Due to a problem in Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, you might see this internal error at the fitter stage when compiling a Partial Reconfiguration (PR) implementation that uses a global reset on fast input/output registers. The base revision compiles successfully, the error occurs only in PR implementations with this global reset usage. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v25.1.1 or v25.1, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Error(24244): Found an error when generating the IBIS Output File for board analysis
Description Due to a problem is Quartus® Prime Pro Edition Software version 25.3, you might see this error when generating this IBIS files. This problem only occurs on Windows* OS. This problem occurs because the quartus_py.exe file has changed location in the installation directory but the IBIS writer still calls the file from the previous location. Resolution To work around this problem, copy the file quartus_py.exe from this directory \altera_pro\25.3\qcore\bin64\quartus_py.exe to this one \altera_pro\25.3\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Where can I find an LT PowerPlay project file which has been used to program the NVM of an LTC3888 for usage with Agilex™ 7 FPGA devices?
Description You can find an LT PowerPlay project file which has been used to program the Non-Volatile Memory (NVM) of the LTC3888 voltage regulator module for usage with Agilex™ 7 FPGA devices in the Installer Package for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile). Resolution The Installer Package for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile) can be downloaded here : Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile) The LT PowerPlay project file is located in the directory \board_design_files\main_board\LTpowerplay\boardname_LTpowerplay_with_fpga.projError(11219): Device <Agilex™ 5 FPGA Part Number> does not support HPS IOCSR
Description Due to a problem in Quartus® Prime Pro Edition software version 25.3 and earlier, when using Agilex™ 5 SoC devices you may see this error when trying to generate a Hard Processor System (HPS) Remote System Update (RSU) .jic file from encrypted and/or signed .rbf files for Agilex™ 5 SoC devices using the Programming File Generator / quartus_pfg tool. Resolution This issue is fixed starting from Quartus® Prime Pro Edition software version 25.3.1.Why does the start_basic_test procedure fail when running the GTS JESD204B FPGA IP Design Example on the Agilex™ 5 FPGA hardware?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you may observe intermittent failures when running the start_basic_test procedure with the GTS JESD204B FPGA IP Design Example. Resolution To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install the patch below. After installing the patch, do the following: Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤ RX Adaptation mode: Manual: if data rate <= 7Gbps Auto: if data rate > 7Gbps Regenerate the design example. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Where to get the MAX® 10 FPGA Variable Pitch Ball-Grid Array(VPBGA) 610-pin Package Information?
Description The MAX® 10 VPBGA 610-pin Package Information is not being listed in the FPGA Packaging Device Information. Resolution Download the MAX® 10 VPBGA 610-pin Package Information from the Altera® FPGA 04r-00549-00 Package Mechanical Drawing