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Why does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the completion buffer reaches a specific threshold. In hardware, this problem may manifest as data corruption when the outstanding completion data reaches the same threshold. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387Why do the Configuration Intercept Interface, Control Shadow Interface, Configuration Extension Bus Interface, and VirtIO features not operate as expected when Configuration via Protocol is enabled in the GTS AXI Streaming IP for PCI Express*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 and earlier, enabling the Configuration via Protocol (CvP) feature in the GTS AXI Streaming IP for PCI Express* automatically disables the Configuration Intercept feature within the IP. As a result, all features that rely on the Configuration Intercept Interface, or that internally utilize it, are also affected. Consequently, Vendor‑Specific Extended Capabilities (VSEC) implemented through the Configuration Extension Bus (CEB) Interface cannot be discovered during PCIe enumeration, VirtIO capabilities are not enumerated, and the Control Shadow Interface does not output configuration information as expected. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhich Protocols Support Spread Spectrum Clocking (SSC) on Agilex® 5 and Agilex® 3 FPGA Devices?
Description In the Agilex® 5 and Agilex® 3 FPGA device families, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort Hard Processor System (HPS) USB 3.1 Gen1 SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using GTS transceivers, SSC is enabled by setting the "Spread Spectrum" option to "ENABLE", while keeping the “Enable TX FGT PLL fractional mode” option disabled in the GTS PMA/FEC Direct PHY IP. Resolution N/AWhy does boundary scan fail or report length mismatches when including F-Tile FHT transceivers in the scan chain of Agilex® 7 FPGA devices when using Quartus® Prime Pro software version 26.1 or earlier?
Description Boundary scan of F-Tile FHT transceiver channels is not supported in Agilex® 7 FPGA devices when using the Quartus® Prime Pro software version 26.1 or earlier. Resolution To work around this problem, you can bypass the F-Tile FHT transceiver channels in your boundary scan chain. This problem will be fixed in a future version of the Quartus Prime Pro software.Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, you may encounter setup and minimum pulse width timing violations in the LVDS SERDES IP Design Example. This issue is caused by an incorrect value of the vco_data_rate_ratio parameter used in the LVDS SERDES IP, which leads to improper timing constraints and resulting violations. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, follow the steps below: Step 1: In the auto-generated file intel_lvds_core10_ph2_hw_ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sv, Original: .vco_data_rate_ratio(0), Change to: .vco_data_rate_ratio(<correct_vco_data_rate_ratio>), Step 2: In the auto-generated file ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sdc, add this SDC constraint set ip_params(vco_data_rate_ratio) <correct_vco_data_rate_ratio> Step 3: Re-compile the design The correct vco_data_rate_ratio parameter value based on the LVDS SERDES IP data rate (Mbps) shown in table below: Use the appropriate vco_data_rate_ratio based on the LVDS SERDES IP data rate: data_rate >= 600 Mbps 1 600 Mbps > data_rate >= 300 Mbps 2 data_rate < 300 Mbps 4 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core: LVDS SERDES IPWhy does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?
Description Due to an issue in Quartus® Prime Pro Edition Software version 25.1, the readdatareordering_depth property of the ACCT IP AXI4 interface is not configured correctly. As a result, the interconnect is not set up to handle out‑of‑order responses. In this scenario, the Agilex® 5 FPGA Hard Processor System (HPS) may issue out‑of‑order responses during ACCT IP operations when translating AXI4 transactions to ACE5‑LITE. Because the interconnect is not configured to accommodate this behavior, the system may hang. Resolution This issue is scheduled to be fixed in Quartus® Prime Pro Edition Software version 26.1.Why does the Nios® V processor without data cache hang during a flash read operation using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read operation on a flash device using the GSFI IP HAL driver, a Nios® V processor configured without a data cache may hang and stop functioning correctly due to an issue in the HAL driver. The HAL driver attempts to flush the data cache even when no data cache is present. This incorrect behavior places the processor into a non-deterministic state, which can cause the system to freeze. Resolution To work around this issue, update the following line in the intel_gsfi_read() function. Original: alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); Change to: #if ALT_CPU_DCACHE_SIZE > 0 alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); #endif This modification ensures that the data cache flush operation is performed only when a data cache is present. This issue will be fixed in a future Quartus® Prime Software release.Why does the read/write HAL API fail when the access length reaches the last byte of flash memory when using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read or write operation on a flash memory device using the GSFI IP HAL read/write API, the API may incorrectly return an EINVAL error code. This issue occurs because the operation end address is miscalculated. As a result, the GSFI IP HAL API incorrectly determines that the operation end address exceeds the valid flash memory range and flags the access length as invalid. For example, when reading or writing the entire 1 GiB flash device, the operation reaches the last byte with an access length of 2147483648 bytes. In this case, the GSFI IP HAL API miscalculates the operation end address as 0x80000000, which exceeds the flash end address of 0x7FFFFFFF. Consequently, the access length is incorrectly treated as invalid, and a false EINVAL error code is returned. This issue does not occur when reading from or writing to other addresses that do not include the last byte of the flash memory. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, update the following line in the intel_gsfi_validate_read_write_arguments() Original: end_address = start_address + length; Change to: end_address = start_address + length - 1; This correction ensures the calculated end address does not exceed the valid flash memory range. This issue will be fixed in a future Quartus® Prime Design Software release.
