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Why is there an "unrecognized device" error when using quartus_jli to configure or program a JAM file for flash devices of 2 GB or larger?
Description In any versions of Altera® Quartus® Prime Pro Edition Software, the quartus_jli command may report an “unrecognized device” error when a JAM file targets a flash device that is 2 GB or larger. This behavior is specific to JAM files used with large flash devices and does not occur with smaller flash sizes. Resolution Use the following workaround to avoid the error: Run the jtagconfig command to detect the connected JTAG hardware. After the hardware is detected, run quartus_jli to configure or program the JAM file. There is currently no plan to fix this behavior in a future Quartus® Prime release.Why are my high fanout cells not duplicated?
Description Due to an problem in the Quartus® Prime Pro Edition Software versions 24.3 and later, duplication of cells with high fanout is prevented even when duplication assignments such as DUPLICATE_REGISTER or DUPLICATE_SYNC_FANIN are defined explicitly. This behavior affects cells that have a driver in a different partition, including both signals and clocks. For example, a register in partition A that has its clock coming from the root partition will not be duplicated despite having the appropriate assignment. Resolution To work around this problem, remove the partitions or ensure that the affected cells are not driven by other cells in different partitions. If removing partitions from your design is not feasible, patches are available to work around this problem. Download and unzip the zip file that matches your Quartus® Prime Pro version and operating system from this KDB. Quartus® Prime Pro Edition Version Patch number 24.3 [0.36|^quartus-24.3-0.36.zip] 24.3.1 [1.30|^quartus-24.3.1-1.30.zip] 25.1 [0.38|^quartus-25.1-0.38.zip] 25.1.1 [1.29|^quartus-25.1.1-1.29.zip] 25.3 [0.28|^quartus-25.3-0.28.zip] 25.3.1 [1.07|^quartus-25.3.1-1.07.zip] Patches for versions 25.3 and 25.3.1 also address additional problems; refer to the README files for more information. This problem is fixed beginning with the Quartus® Prime pro Edition Software version 26.1.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_2
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the error above when using the I/O PLL Parameterizable Macro (ipm_iopll). The error only occurs when using non-integer values for the VCO Clocks and Output Clocks in the I/O PLL Parameterizable Macro. Resolution To work around this problem, use non‑integer values for the VCO Clocks and Output Clocks in the IOPLL IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the mailbox Client IP and FreeRTOS because the driver software of the IP doesn't support FreeRTOS. Resolution The driver software supports Hardware Abstraction Layer(HAL) and uCOS-II. Please select one of them when generating Nios® V BSP.Why do the F2H (FPGA2HPS) subordinate signals showing "zzzzz"?
Description Due to a problem with the QuestaSim* SE on Quartus ® Prime Pro Edition Software version 25.1.1, when using the BFM testbench on F2H (FPGA2HPS) AXI4 and ACE-lite bridge, subordinate signals may appeared to have “zzz” or “ZZ” in the readings. Example of signal waveform in QuestaSim with “zzz” or “ZZ”: Impact: In QuestaSim, a "zzz" or "ZZ" signal usually indicates a high-impedance state (floating) or uninitialized value in the VHDL simulation, often appearing in the Wave window when signals are not being driven or have not received a value. Resolution Possible workarounds: Add Missing Pull-up/Pull-down resistors: If the signal is intended to be high or low when not driven, ensure a pull-up or pull-down resistor is properly modeled. Fix Unconnected Port: Ensure signal in the waveform is connected correctly in the testbench. Optimization Issues: Design optimization can cause signals to appear missing or in an incorrect state. Try adding +acc to the vsim command to improve visibility, e.g. vsim -voptargs=+acc <top_module> This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.Why does Quartus® Prime Pro Edition version 25.1.1 and later add a phased_clk_lock_interface conduit to the altera_eth_1588_tod IP when targeting Agilex® 7 FPGA devices?
Description In Quartus® Prime Pro Edition software version 25.1.1 and later, when targeting Agilex® 7 FPGA devices, the altera_eth_1588_tod IP exposes an additional phased_clk_lock_interface conduit. This interface conduit was not present in earlier Quartus® Prime Pro Edition versions. As a result, designs that were originally created and validated using Quartus® Prime Pro Edition version 25.1 or earlier may encounter connectivity issues or appear broken when migrated to newer software versions, due to the unexpected addition of this required conduit. Resolution To fix this problem in Quartus@ Prime Pro software version 25.3.1, install patch 1.23 below for the correct OS (Operating System) Readme: quartus-25.3.1-1.23-readme.txt Linux: quartus-25.3.1-1.23-linux.run Windows: quartus-25.3.1-1.23-windows.exe This problem is scheduled to be fixed in a future release of the Quartus@ Prime Pro Software.Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Error: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(38): in protected region
Description Due to a problem in the Quartus® Prime Standard Edition Software, you might see this error message when simulating the ASMI (Active Serial Memory Interface) Parallel IP for Arria® 10 FPGA devices. This is due to the simulation libraries for the ASMI Parallel IP is missing in the Quartus® Prime Standard Edition Software. Resolution To work around this problem, upgrade the design to the Quartus® Prime Pro Edition Software. The simulation libraries for the ASMI Parallel IP are available in the Quartus® Prime Pro Edition Software. This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software. Related IP Core ASMI Parallel IPInternal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,
