Recent Content
Why does the Altera® Advanced Link Analyzer Crash or Produce Incorrect Results on Microsoft Windows 11* 25H2 Virtual Machines?
Description The Altera® Advanced Link Analyzer may crash or produce incorrect simulation results on Microsoft® Windows 11 version 25H2 virtual machines configured with ABI‑based virtual CPU models. This problem occurs because the Intel® Math Kernel Library (MKL) depends on hardware‑faithful x86 CPU execution semantics, which are not fully guaranteed by ABI‑based vCPUs in Microsoft Windows 11 25H2. Resolution To work around this problem, you can configure virtual machines as follows: Microsoft Windows* 11 version 25H2 Use a hardware-faithful vCPU (for example, VMware ESXi* or VMware Workstation* default vCPU) On KVM/QEMU platforms, enable host CPU passthrough Microsoft Windows Server 2022, Windows Server 2025, and Windows 11 version 24H2 or earlier ABI-based virtual CPUs are supported; no changes required Additional Information This problem only affects Microsoft Windows 11 version 25H2 virtual machines using ABI‑based virtual CPU models. Other Windows versions and hardware‑faithful virtual CPUs are not affected.Why ECC protection does not work in F-Tile Dynamic Reconfiguration Suite IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you will observe the Enable ECC protection parameter in the F-Tile Dynamic Reconfiguration Suite IP does not function as expected. Even though you set Enable ECC protection parameter as ON, the ECC protection could not be enabled. Resolution There is no workaround available. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I see configuration failure "Error(18948): Error while sending VOUT_MODE command" if the PMBus Slave device type is set as XDPE12284C or PXE1410CDM_G005 for Agilex® 7 FPGA in Quartus® Prime Pro Edition Software version prior to 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version prior to 26.1, when you select the "Slave device type" as XDPE12284C or PXE1410CDM_G005 in the Power Management & VID settings page in your design, you may see the following error while programming SOF file with Quartus® Prime Pro Edition Programmer: Error(18948): Error message received from device: Error while sending VOUT_MODE command Resolution In Quartus® Prime Pro Edition Software version prior to 26.1, if you are using XDPE12284C or PXE1410CDM_G005 as the PMBus Slave device for Agilex® 7 FPGA, select the "Slave device type" as "others" in the Power Management & VID settings page as shown in the table below. Voltage Regulator Slave device type Voltage output format Coefficient Voltage value unit XDPE 12284C (IMVP9 mode) Others Direct m=1, b=-200, r=-1 millivolt PXE1410CDM_G005 Others Direct m=2, b=-490, r=-1 millivolt This problem has been fixed in Quartus® Prime Pro Edition Software version 26.1.Why does PTP accuracy error go beyond +/- 1.5ns during dynamic reconfiguration between GTS Ethernet Hard IP and Triple-Speed Ethernet IP in Quartus® Prime Pro Edition version 26.1 and earlier?
Description When using the GTS Dynamic Reconfiguration Controller IP flow in Quartus® Prime Pro Edition version 26.1 or earlier to perform dynamic reconfiguration between the GTS Ethernet Hard IP and the Triple-Speed Ethernet (TSE) IP, the PTP (Precision Time Protocol) accuracy error for the GTS Ethernet Hard IP may exceed ±1.5ns in this scenario. This PTP accuracy problem does not occur with the TSE IP in this case. Resolution No workaround is available so far. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the Single Floating Point Variable Streaming Reverse FFT IP produce an incorrect output when the input order is set to Natural?
Description Due to a problem in the Quartus® Prime Software version 25.3.1 and earlier, the "Natural" option for setting "Input Order" is incorrectly available for selection and unsupported when generating the FFT IP. This option is available when using the following parameters: Direction: "Reverse", Data Flow: "Variable Streaming", Representation: "Single Floating Point". Resolution This problem is scheduled to be fixed in release 26.1 of the Quartus® Prime Software with the removal of the unsupported “Natural” option. Additional Information This problem affects the FFT IP in Quartus® Prime Software versions 17.0 to 25.3.1.Why does Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 turns compiler warnings into errors?
Description In the Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and later, you might see compilation error related to the following errors: Implicit int types (-Werror=implicit-int) Implicit function declarations (-Werror=implicit-function-declaration) Typos in function prototypes (-Werror=declaration-missing-parameter-type) Incorrect uses of the return statement (-Werror=return-mismatch) Using pointers as integers and vice versa (-Werror=int-conversion) Type checking on pointer types (-Werror=incompatible-pointer-types) This is due to an update in GCC 14 – GNU: Certain warnings are now errors, which affects future GCC versions. For more information, Ashling* RiscFree* IDE for Altera FPGAs software version 25.3.1 (1 st August 2025) is using GCC 13.2. Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is using GCC 15.2. Thus, Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and future versions are affected. Note that Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is paired with Quartus ® Prime Pro Edition software version 26.1. Resolution GNU recommends resolving all the new errors for better code quality. If necessary, you may refer to the workaround – GNU: Turning errors back into warnings. In Board Support Package Editor, add "-fpermissive" in hal.make.cflags_user_flags.Why does simulation elaboration fail with port width mismatch for the F-tile Ethernet Hard IP 400GE-8 DR example design generated with VHDL when using QuestaSim* or Riviera-PRO* simulator?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, when running simulation for the F-Tile Ethernet Hard IP 400GE-8 Dynamic Reconfiguration (DR) Example Design generated with VHDL and using Questa* Sim or Riviera-PRO* simulator, you may observe the following port width mismatch error during elaboration: # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # ** Fatal: (vsim-3363) The array length (4) of VHDL port 'anlt_link' does not match the width (8) of its Verilog connection (1st connection). # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/eth_f_hw/IP_INST[0]/hw_ip_top/dut File: ./eth_f_hw_ip_top_400g.sv Line: 707 # FATAL ERROR while loading design # Error loading design Error loading design This occurs due to a mismatch between the array length of the VHDL port and the width of its Verilog connection in the generated design. Resolution To work around this problem, you may use one of the following methods: Update the MAX_ETHPORT parameter in the eth_f_hw_ip_top module to 4: parameter MAX_ETHPORT = 4; (Change the value to 4 as shown above.) Use the following suppress switch in the vsim do file: elab -suppress 3363 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.14Views0likesWhy does the maximum observed channel-to-channel skew exceed 2 UI + 125 ps in an E-Tile transceiver under NRZ mode, even when TX PMA bonding is enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may observe channel-to-channel skew exceeds 2 UI + 125 ps in E-Tile transceivers under NRZ mode even when TX PMA bonding is enabled. Resolution There is no workaround currently, and there is no plan to fix this problem.Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe* functional failures after performing a CvP update, as the PCIe interface becomes non-functional. During the CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe Hard IP is not reset. This issue occurs because the R-Tile RTL is unable to handle the handshaking between the PCIe Hard IP and the fabric after the CvP update. Note that this issue does not cause the PCIe link to go down. This issue affects designs using R-Tile with both CvP and PCIe. Designs using R-Tile without CvP are not affected. This issue occurs in the following flow: CvP Periphery image CvP Initialization CvP Update PCIe activity Issue observed The following sequences will not trigger the problem: A CvP update without PCIe activity after CvP Initialization PCIe activity without a CvP Update after CvP Initialization Resolution To work around this problem, reconfigure the FPGA. Note that this fix may introduce a few seconds of additional delay during the CvP update in the teardown process. This delay occurs after the core.rbf file is transferred during every CvP update. During teardown, the CvP driver polls the CVP_CONFIG_READY bit in the CvP Status Register until CVP_CONFIG_READY equals 0, which accounts for the additional delay. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1. Related IP R-Tile Avalon Streaming IP for PCI Express Multi Channel DMA IP for PCI Express AXI Streaming IP for PCI ExpressCritical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see this critical warning during the Assembler stage when assigning the I/O Standard to the negative differential pins of the Agilex® 5 FPGA devices and Agilex® 3 FPGA devices. This is due to the I/O Standard of the negative differential pin is not reflected in the Quartus® .qsf file even though the I/O Standard had been assigned to the negative differential pin in the Pin Planner. Resolution To work around this problem, add the assignment below in the .qsf: set_instance_assignment -name IO_STANDARD "<I/O_Standard>" -to "<negative_differential_pin_name>" -entity <entity_name> This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
