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Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.Why do I see rx_ready not asserting, or incorrect TX data rates in Agilex® 7 F‑Tile or Agilex® 5/3 FPGA GTS device transceiver simulations using the Quartus® Prime Pro 25.3.1 or earlier software with Siemens QuestaSim® Altera Edition software?
Description Due to a bug in the Quartus® Prime Pro 25.3.1 and earlier software for Agilex® 7 F‑Tile or Agilex ® 5/3 FPGA GTS devices, you may see the rx_ready signal not asserting, or incorrect TX data rates when simulating with the Siemens QuestaSim* Altera® Edition software. Resolution To work around this problem, you can update your design to the Quartus Prime Pro software version 26.1 and create a script that sets the following environment variables and then calls the Quartus Prime Pro software generated msim_setup.tcl file. set QUARTUS_SIM_LIB_DIR <quartus_installation>/quartus/eda/sim_lib2 set DEVICES_SIM_LIB_DIR <quartus_installation>/devices/sim_lib2 set ENABLE_QE_LIBRARY_COMPILATION "true" source msim_setup.tcl This problem will be fixed in a future version of the Quartus Prime Pro software.Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 with the Agilex® 5 FPGA E‑Series 065B Modular Development Kit (Production) MK‑A5E065AB32AEA development kit preset in the GTS AXI Streaming IP for PCI Express, you may see the following error messages when configuring the development kit using a programming file generated from the PCIe design example using that preset. Error(18939): Unexpected error in JTAG server: Internal error Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(18947): Device not responding Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(209012): Operation failed Resolution To work around this problem, replace the following settings in pcie_ed.qsf file of the GTS AXI Streaming IP for PCI Express Design Example set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 set_global_assignment -name USE_CONF_DONE SDM_IO12 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_INIT_DONE SDM_IO10 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF with the following settings set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ After that, recompile the design to generate a new programming file. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the completion buffer reaches a specific threshold. In hardware, this problem may manifest as data corruption when the outstanding completion data reaches the same threshold. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387Why do the Configuration Intercept Interface, Control Shadow Interface, Configuration Extension Bus Interface, and VirtIO features not operate as expected when Configuration via Protocol is enabled in the GTS AXI Streaming IP for PCI Express*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 and earlier, enabling the Configuration via Protocol (CvP) feature in the GTS AXI Streaming IP for PCI Express* automatically disables the Configuration Intercept feature within the IP. As a result, all features that rely on the Configuration Intercept Interface, or that internally utilize it, are also affected. Consequently, Vendor‑Specific Extended Capabilities (VSEC) implemented through the Configuration Extension Bus (CEB) Interface cannot be discovered during PCIe enumeration, VirtIO capabilities are not enumerated, and the Control Shadow Interface does not output configuration information as expected. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Which Protocols Support Spread Spectrum Clocking (SSC) in Agilex® 7 Devices?
Description In the Agilex® 7 FPGA device family, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using FGT transceivers in F-tile, SSC is enabled by selecting the “Enable Spread Spectrum Clocking” option, while keeping the “Enable TX FGT PLL fractional mode” option disabled in the F-Tile PMA/FEC Direct PHY IP. Resolution N/AWhich Protocols Support Spread Spectrum Clocking (SSC) on Agilex® 5 and Agilex® 3 FPGA Devices?
Description In the Agilex® 5 and Agilex® 3 FPGA device families, the Spread Spectrum Clocking (SSC) feature is supported only for specific protocol-based applications and can be optionally enabled for the following protocols: PCI Express (PCIe*) DisplayPort Hard Processor System (HPS) USB 3.1 Gen1 SATA/SAS (configured through the PMA/FEC Direct PHY IP) When using GTS transceivers, SSC is enabled by setting the "Spread Spectrum" option to "ENABLE", while keeping the “Enable TX FGT PLL fractional mode” option disabled in the GTS PMA/FEC Direct PHY IP. Resolution N/AWhy does boundary scan fail or report length mismatches when including F-Tile FHT transceivers in the scan chain of Agilex® 7 FPGA devices when using Quartus® Prime Pro software version 26.1 or earlier?
Description Boundary scan of F-Tile FHT transceiver channels is not supported in Agilex® 7 FPGA devices when using the Quartus® Prime Pro software version 26.1 or earlier. Resolution To work around this problem, you can bypass the F-Tile FHT transceiver channels in your boundary scan chain. This problem will be fixed in a future version of the Quartus Prime Pro software.
