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Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Error: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(38): in protected region
Description Due to a problem in the Quartus® Prime Standard Edition Software, you might see this error message when simulating the ASMI (Active Serial Memory Interface) Parallel IP for Arria® 10 FPGA devices. This is due to the simulation libraries for the ASMI Parallel IP is missing in the Quartus® Prime Standard Edition Software. Resolution To work around this problem, upgrade the design to the Quartus® Prime Pro Edition Software. The simulation libraries for the ASMI Parallel IP are available in the Quartus® Prime Pro Edition Software. This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software. Related IP Core ASMI Parallel IPInternal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,What is the maximum memory clock frequency for DDR4 in Arria® 10 FPGAs and SoC FPGAs?
Description In Quartus® Prime Pro Edition software version 24.3, users can configure the memory clock frequency to 1333 MHz in the External Memory Interfaces Arria® 10 FPGA IP. However, the External Memory Interfaces Arria 10 FPGA IP User Guide specifies a maximum supported configuration of 1200 MHz. Resolution Users may choose to operate the External Memory Interfaces Arria 10 FPGA IP beyond the published specifications, including overclocking, at their own risk.Why do accuracy errors occur when using the GTS Dynamic Reconfiguration Controller IP with the protocol set to “COMBO (PTP/CPRI MR)” in Quartus Prime Pro Edition software versions 25.3.1 and earlier?
Description Due to an issue in the support logic generated for driving clock sources, accuracy errors may be observed when the COMBO (PTP/CPRI MR) protocol is selected in the GTS Dynamic Reconfiguration Controller IP when using Quartus® Prime Pro Edition software version 25.3.1 and earlier. This issue affects designs in which the COMBO protocol is configured in the GTS Dynamic Reconfiguration Controller IP for: 10GE‑1 Ethernet IP with PTP enabled, and 25GE‑1 Ethernet IP with PTP enabled. Resolution There is no workaround available for this issue in Quartus Prime Pro Edition software version 25.3.1 and earlier. This problem is resolved beginning with Quartus Prime Pro Edition software version 26.1.Warning(24076): PLL instance "iopll_0|tennm_ph2_iopll" is configured with parameters that differ from the calculated optimal settings
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1 and earlier, when compiling a design with IOPLL FPGA IP targeting an Agilex® 5 FPGA E-Series in speed grade -6, you may see this warning, with a suggestion to change the PLL settings that would result in a VCO frequency that is greater than what is supported by the target device speed grade. For example, the compiler may suggest settings that result in a VCO frequency of 3000 MHz, but the maximum supported VCO frequency in that speed grade is 2400 MHz. Resolution You may ignore this warning when targeting an Agilex® 5 FPGA E-Series in speed grade -6. This issue will be fixed in a future version of the Quartus® Prime Pro Edition software.Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.Why do I see rx_ready not asserting, or incorrect TX data rates in Agilex® 7 F‑Tile or Agilex® 5/3 FPGA GTS device transceiver simulations using the Quartus® Prime Pro 25.3.1 or earlier software with Siemens QuestaSim® Altera Edition software?
Description Due to a bug in the Quartus® Prime Pro 25.3.1 and earlier software for Agilex® 7 F‑Tile or Agilex ® 5/3 FPGA GTS devices, you may see the rx_ready signal not asserting, or incorrect TX data rates when simulating with the Siemens QuestaSim* Altera® Edition software. Resolution To work around this problem, you can update your design to the Quartus Prime Pro software version 26.1 and create a script that sets the following environment variables and then calls the Quartus Prime Pro software generated msim_setup.tcl file. set QUARTUS_SIM_LIB_DIR <quartus_installation>/quartus/eda/sim_lib2 set DEVICES_SIM_LIB_DIR <quartus_installation>/devices/sim_lib2 set ENABLE_QE_LIBRARY_COMPILATION "true" source msim_setup.tcl This problem will be fixed in a future version of the Quartus Prime Pro software.
