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Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,What is the maximum memory clock frequency for DDR4 in Arria® 10 FPGAs and SoC FPGAs?
Description In Quartus® Prime Pro Edition software version 24.3, users can configure the memory clock frequency to 1333 MHz in the External Memory Interfaces Arria® 10 FPGA IP. However, the External Memory Interfaces Arria 10 FPGA IP User Guide specifies a maximum supported configuration of 1200 MHz. Resolution Users may choose to operate the External Memory Interfaces Arria 10 FPGA IP beyond the published specifications, including overclocking, at their own risk.Why do accuracy errors occur when using the GTS Dynamic Reconfiguration Controller IP with the protocol set to “COMBO (PTP/CPRI MR)” in Quartus Prime Pro Edition software versions 25.3.1 and earlier?
Description Due to an issue in the support logic generated for driving clock sources, accuracy errors may be observed when the COMBO (PTP/CPRI MR) protocol is selected in the GTS Dynamic Reconfiguration Controller IP when using Quartus® Prime Pro Edition software version 25.3.1 and earlier. This issue affects designs in which the COMBO protocol is configured in the GTS Dynamic Reconfiguration Controller IP for: 10GE‑1 Ethernet IP with PTP enabled, and 25GE‑1 Ethernet IP with PTP enabled. Resolution There is no workaround available for this issue in Quartus Prime Pro Edition software version 25.3.1 and earlier. This problem is resolved beginning with Quartus Prime Pro Edition software version 26.1.Warning(24076): PLL instance "iopll_0|tennm_ph2_iopll" is configured with parameters that differ from the calculated optimal settings
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1 and earlier, when compiling a design with IOPLL FPGA IP targeting an Agilex® 5 FPGA E-Series in speed grade -6, you may see this warning, with a suggestion to change the PLL settings that would result in a VCO frequency that is greater than what is supported by the target device speed grade. For example, the compiler may suggest settings that result in a VCO frequency of 3000 MHz, but the maximum supported VCO frequency in that speed grade is 2400 MHz. Resolution You may ignore this warning when targeting an Agilex® 5 FPGA E-Series in speed grade -6. This issue will be fixed in a future version of the Quartus® Prime Pro Edition software.Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY
Description Due to a problem in the Quartus® Prime Pro edition software version 26.1 and earlier, you may see this problem when using Synopsys VCS* or VCSMX* simulators to simulate the PIO with MCDMA Bypass Mode example design of F-tile Multichannel DMA IP for PCI Express* in Native Endpoint port mode and Multichannel DMA user mode with either AVMM or AVST interface for MCDMA settings. Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Error! Unknown INTENDED_DEVICE_FAMILY=DEVICE_FAMILY. Time: 0 Instance: pcie_ed_sim.dut.dut.mcdma.dma_mode.mcdma_inst.PROTECTED Resolution No workaround is available. This issue will be fixed in a future release of Quartus® Prime Pro edition software.Why is PTP enabled F-Tile Ethernet FPGA Hard IP design using Quartus® Prime Pro Edition showing an error when the PTP enabled F-Tile Ethernet FPGA Hard IP design is connected to System PLL1 clock or System PLL2 clock?
Description Due to a limitation in the Quartus® Prime Pro Edition Software, the F-Tile Ethernet FPGA Hard IP shows an error when PTP enabled design is connected to system PLL 1 clock. This problem is seen in designs that have multiple IPs and when the IP with PTP enabled is connected to System PLL 1 clock or System PLL2 clock. Resolution The workaround for this limitation is to connect PTP enabled F-Tile Ethernet FPGA Hard IP to System PLL0 clock only.Why do I see rx_ready not asserting, or incorrect TX data rates in Agilex® 7 F‑Tile or Agilex® 5/3 FPGA GTS device transceiver simulations using the Quartus® Prime Pro 25.3.1 or earlier software with Siemens QuestaSim® Altera Edition software?
Description Due to a bug in the Quartus® Prime Pro 25.3.1 and earlier software for Agilex® 7 F‑Tile or Agilex ® 5/3 FPGA GTS devices, you may see the rx_ready signal not asserting, or incorrect TX data rates when simulating with the Siemens QuestaSim* Altera® Edition software. Resolution To work around this problem, you can update your design to the Quartus Prime Pro software version 26.1 and create a script that sets the following environment variables and then calls the Quartus Prime Pro software generated msim_setup.tcl file. set QUARTUS_SIM_LIB_DIR <quartus_installation>/quartus/eda/sim_lib2 set DEVICES_SIM_LIB_DIR <quartus_installation>/devices/sim_lib2 set ENABLE_QE_LIBRARY_COMPILATION "true" source msim_setup.tcl This problem will be fixed in a future version of the Quartus Prime Pro software.Why can’t the Agilex® 5 FPGA E‑Series 065B Modular Development Kit be configured using the configuration file generated from the GTS AXI Streaming IP for PCI Express* design example?
Description Due to a problem in the Quartus® Prime Pro Edition software version 26.1 with the Agilex® 5 FPGA E‑Series 065B Modular Development Kit (Production) MK‑A5E065AB32AEA development kit preset in the GTS AXI Streaming IP for PCI Express, you may see the following error messages when configuring the development kit using a programming file generated from the PCIe design example using that preset. Error(18939): Unexpected error in JTAG server: Internal error Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(18947): Device not responding Error(18939): Unexpected error in JTAG server: Invalid OPEN_ID Error(209012): Operation failed Resolution To work around this problem, replace the following settings in pcie_ed.qsf file of the GTS AXI Streaming IP for PCI Express Design Example set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO16 set_global_assignment -name USE_CONF_DONE SDM_IO12 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name USE_INIT_DONE SDM_IO10 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1 set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF with the following settings set_global_assignment -name USE_PWRMGT_SCL SDM_IO14 set_global_assignment -name USE_PWRMGT_SDA SDM_IO11 set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 74 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ" set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4" set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ After that, recompile the design to generate a new programming file. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does the BAM (Bursting Avalon‑MM Master) module of the GTS AXI Multichannel DMA IP for PCI Express* fail to generate Completion TLPs in a PCIe Root Port implementation?
Description Due to a problem in Quartus® Prime Pro Edition software version 26.1, the BAM in the AXI Multichannel DMA IP for PCI Express* may fail to return Completion TLPs in simulation once the completion buffer reaches a specific threshold. In hardware, this problem may manifest as data corruption when the outstanding completion data reaches the same threshold. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387
