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Why does the example design fail to generate when "Dual Simplex Applied on JESD204B PHY" is selected with "Enable Manual F" enabled and the F value greater than 4?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, you may observe the Dual Simplex (DS) PHY wrapper example design for GTS JESD204B IP fails to generate when the JESD204B DS Wrapper option is used with "Dual Simplex applied on JESD204B PHY" selected in the IP GUI, "Enable Manual F" is enabled, and the F value is set greater than 4. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.3.1.Why do the Resource Utilization results remain the same for the Agilex® 3 GTS JESD204B IP Core with either ECC_EN On or Off?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may observe the resource utilization results remain the same in Agilex® 3 GTS JESD204B IP core with either ECC_EN On or Off Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition version 25.1.1.When using the R-Tile Avalon Streaming IP for PCI Express* how should the CPL Always Grant option be used?
Description CPL Always Grant is a new option in the GUI for the R-Tile Avalon Streaming IP for PCI Express. If the parameter is turned on, internally generated TLPs (completion and message) will check for available credits at the link partner (i.e., total credit) and will not be limited to the locally allocated credit of 1, 4, or 16, depending on the scale factor used. If the parameter is turned off, which is the default: Consider that there are 100 completion credits available and we allocated 4 credits for internally generated completions. After 4 config reads are received and after the Hard IP has sent 4 completions in response, the 5th config read received will not result in a completion being transmitted by the Hard IP until a credit update is received from the Root Port, even though the Hard IP still has 96 credits available for completions. This behaviour applies only to configuration requests which require completions to be generated by the PCIe Hard IP. Internally generated messages are posted and do not require completions to be generated. The FC_Update check is not bypassed when the CPL Always Grant option is turned on. The Hard IP keeps track of available credits at the link partner and prevents any TLPs (internal or user- generated) from being transmitted through the link enough credits are not available. For header and data, the credits reserved for internal IP usage are 1, 4, and 16 for scaling factors of 1, 4, and 16 respectively. Header credits and data credits have their own allocation. For new designs targeting an interoperable vendor-neutral system architecture, Altera recommends that this option be enabled. Resolution This information is scheduled to be included in a future release of the R-Tile Avalon Streaming IP for PCI Express User Guide.Does the Agilex® 7 FPGA F-Series (2 × F-Tiles) Development Kit support CvP over the PCIe* 4.0x16 Gold Fingers?
Description The Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) do not support CvP over the PCIe* 4.0x16 Gold Finger Card Edge connector. CvP is supported over the MCIO x4 interface. Resolution CvP is not supported over the PCIe* 4.0x16 Gold Finer Card Edge Connector on the Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023). This problem will not be fixed in a future release as the problem is due to the physical location of the PCIe* 4.0x16 F-Tile being located on the Right Hand Side of the device. CvP is only supported on the Left Had Side Tile of this device.CONSTRA error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb'
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the following or similar simulation error message when simulating a design targeting an Agilex® 7 FPGA M-Series device or an Agilex® 3 FPGA C-Series device: CONSTRA (ed_sim.phylite_ph2_0_example_design.phylite_ph2_0_example_design.core.arch_inst.phylite_clocking_inst.iopll_inst.tennm_ph2_iopll_encrypted_inst): error: Failed to open file 'C:\altera_pro\26.1\devices/10nm/sm7revb/hviowr_pllwrap_bf_rbc_constraints.ddb' This CONSTRA error occurs because the SystemVerilog Constraint Solver executable file cannot find simulation files due to missing directories from the Quartus installation path, under the directory <Quartus_version>/devices/10nm. The missing directories are part of the Agilex® 5 FPGA device support files. Resolution To work around this problem: Download the Agilex® 5 FPGA device support file, according to the Quartus® Prime Pro Edition Software version and operating system. Install the downloaded Agilex® 5 FPGA device support file. Simulate your design again using a fresh simulation directory. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why do I see SEU errors being detected consistently on my Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) (DK-DEV-AGF023FA)?
Description Due to an issue with the settings of the Voltage Regulator LTC3888 used on the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (DK-DEV-AGF023FA), you may see SEU error being detected regularly when you enable SEU error check. The behavior occurs because the voltage required by Agilex™ 7 devices during operation, which can be between 0.7 V and 0.9 V, is over the VOUT_OV_WARN_LIMIT value programmed on LTC3888. Triggering the LTC388 to report an error back to the FPGA SDM. The SDM queues this error on the Error Message Queue (EMQ) which then asserts the SEU Error check. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Voltage Regulator using a Linear Technologies USB-to PMBus Controller (DC1613A) and Programming Adapter (DC2086A) and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following Voltage Regulator configuration file linked at the bottom of this article and follow the steps lay out below: 1. Open the LTpowerPlay on a Windows computer. 2. Connect dongles as shown in picture, power up the board 3. Start LTpowerPlay. It will show a window like below: 4. Click "Open Project", browse to the project file, select it and click "Open". 5. Go to Utilities > Programming Utility. 6. Press OK when asked 7. In the LT Device Programmer, browse again for the project file: 8. Click "Program and Verify System" 9. Application will confirm all was programmed fine: Loading this file will configure the LTC3888 Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to operate with getting assertions from false errors.Why is the FPGA To HPS bridge not functional in a non-HPS EMIF hardware design in Agilex® 5 FPGA device in 25.3.1 release and earlier?
Description Due to an incorrect configuration in the mpfe_config register in the System Manager, performed by the SDM FW, the FPGA-to-HPS transactions will fail to complete on the Agilex® 5 FPGA device in a hardware design that does not instantiate the HPS EMIF IP created with Quartus® Prime 25.3.1 and before. The problem resides in the incorrect value that the SDM FW assigns to the mpfe_config[f2soc_intfcsel] bit when the HPS EMIF is not instantiated. Under this scenario, it is expected that the f2soc_intfcsel field has a value of ‘1', but this is set to '0’ instead. Resolution To workaround this problem, you can set the mpfe_config[f2soc_intfcsel] bit to '1' in the FSBL. The following snippet shows an example of how to do it in U-Boot SPL: #define MPFE_CONFIG_F2SOC_INTFCSEL_BIT 0 void board_init_f(ulong dummy) { : setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(MPFE_CONFIG_F2SOC_INTFCSEL_BIT)); do_bridge_reset(1, RSTMGR_BRGMODRST_FPGA2SOC_MASK ); : } This needs to be done before the FPGA-to-HPS (F2H) bridge is released from reset. This problem will be fixed in a future release. Note: If your non-HPS EMIF design instantiates the Altera ACE5-Lite Cache Coherency Translator (CCT) and, after applying the above workaround, you observe that read transactions in the FPGA-to-HPS (F2H) bridge succeed, but after a write transaction, the system hangs, you may require an additional fix in the ACCT IP that will be released together with the mpfe_config[f2soc_intfcsel] configuration fix. Please refer to Why does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?Why is there an "unrecognized device" error when using quartus_jli to configure or program a JAM file for flash devices of 2 GB or larger?
Description In any versions of Altera® Quartus® Prime Pro Edition Software, the quartus_jli command may report an “unrecognized device” error when a JAM file targets a flash device that is 2 GB or larger. This behavior is specific to JAM files used with large flash devices and does not occur with smaller flash sizes. Resolution Use the following workaround to avoid the error: Run the jtagconfig command to detect the connected JTAG hardware. After the hardware is detected, run quartus_jli to configure or program the JAM file. There is currently no plan to fix this behavior in a future Quartus® Prime release.Why are my high fanout cells not duplicated?
Description Due to an problem in the Quartus® Prime Pro Edition Software versions 24.3 and later, duplication of cells with high fanout is prevented even when duplication assignments such as DUPLICATE_REGISTER or DUPLICATE_SYNC_FANIN are defined explicitly. This behavior affects cells that have a driver in a different partition, including both signals and clocks. For example, a register in partition A that has its clock coming from the root partition will not be duplicated despite having the appropriate assignment. Resolution To work around this problem, remove the partitions or ensure that the affected cells are not driven by other cells in different partitions. If removing partitions from your design is not feasible, patches are available to work around this problem. Download and unzip the zip file that matches your Quartus® Prime Pro version and operating system from this KDB. Quartus® Prime Pro Edition Version Patch number 24.3 [0.36|^quartus-24.3-0.36.zip] 24.3.1 [1.30|^quartus-24.3.1-1.30.zip] 25.1 [0.38|^quartus-25.1-0.38.zip] 25.1.1 [1.29|^quartus-25.1.1-1.29.zip] 25.3 [0.28|^quartus-25.3-0.28.zip] 25.3.1 [1.07|^quartus-25.3.1-1.07.zip] Patches for versions 25.3 and 25.3.1 also address additional problems; refer to the README files for more information. This problem is fixed beginning with the Quartus® Prime pro Edition Software version 26.1.Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_1_2
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see the error above when using the I/O PLL Parameterizable Macro (ipm_iopll). The error only occurs when using non-integer values for the VCO Clocks and Output Clocks in the I/O PLL Parameterizable Macro. Resolution To work around this problem, use non‑integer values for the VCO Clocks and Output Clocks in the IOPLL IP. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
