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Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1.8Views0likesWhy do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP.Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz.
Description You may see the following error when entering 805.664062 MHz into the GTS System PLL Clocks IP "Output frequency C0" field, to match the frequency requirement in the GTS Ethernet Hard IP when configured for 25G-1 Ethernet on Agilex TM 5 FPGA devices using the Quartus® Prime Pro software version 25.3.1 and earlier. Error: <filename>.intel_systemclk_gts_0: SystemPLL#0: Setting not found for output frequency 805664062.0 Hz. Error: <filename>.intel_systemclk_gts_0: "Refclk frequency" (refclk_xcvr_freq_mhz_0) "156.250000" is out of range: "33.109482", "44.145976", "57.547433", "66.218964", "88.291952", "99.328446", "110.364940", "115.094866", "132.437928", "154.510916", "165.547410", "172.642299", "176.583904", "198.656892", "220.729880", "230.189732", "231.766374", "242.802868", "264.875856", "286.948844", "287.737165", "297.985338", "309.021832", "331.094820", "345.284598", "353.167808", "364.204302" This problem is caused by the truncated display of the System PLL frequency in the GTS Ethernet Hard IP. Resolution To work around this problem you can enter 805.6640625 MHz into the “Output frequency C0" field of the GTS System PLL Clocks IP. This problem may be fixed in a future version of the Quartus® Prime Pro software.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why there is Missing location assignment warnings on hps_io interfaces (SDMMC, UART, I3C) in Quartus® Prime Pro Edition Software version 25.1.1 and earlier?
Description Due to a problem in Quartus® Prime Pro Edition Software v25.1.1 and earlier. You might see the warnings messages “Missing location assignment” on some of the hps_io interfaces due to the mismatch interface name. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.3.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why does Agilex™ 5 FPGA ES fails to boot from SDCard and eMMC devices in SDR104, HS400 and HS200 modes?
Description Due to a problem that is under investigation, the Agilex™ 5 FPGA ES (Engineering sample) devices may fail to boot from SD Card in SDR104 mode and from eMMC in HS400 and HS200 modes. The failure is observed in U-Boot and Linux*. In U-Boot, the signature of the failure can be seen from instability when loading any component from the device. In Linux, the failure signature is observed from ‘Buffer I/O Error on dev mmcblk0’ errors when accessing the device. Resolution At this time, there is no workaround for this problem, and it’s recommended to switch to the Agilex™ 5 FPGA Production device, in which this problem does not occur.Why are the R-Tile AXI Multichannel DMA IP Design Example DMA Queues stuck when the Gen5 IP configuration links downgrade to Gen4 or lower speeds?
Description Due to a problem in the Quartus® Prime Pro software version 25.3.1 and earlier, the AXI Multichannel DMA IP Queues will stick if the Gen5 configuration of the IP is link downgrades to Gen4 or lower. For example in the Gen5 IP is used in a Gen4 system. Resolution To fix this problem in Quartus® Prime Pro software version 25.3.1 please install patch 1.01 below. This problem is scheduled to be fix in a future release of the Quartus® Prime Pro software. IP Core AXI Multichannel DMA IP for PCI Express*Why do I see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled in the Quartus® Prime Pro Edition software version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled. This is because the Firecode FEC isn’t supported in F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.