Recent Content
Why doesn’t the CDR lock signal assert in simulation for some F Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition in the Quartus® Prime Pro Edition software version 25.3.1?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see simulation failure that CDR lock signal doesn’t assert for some F‑Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition. Resolution There is no workaround currently. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro edition software.Why is there a failure in the design if we are doing design migration for Agilex™ 3/Agilex™ 5 FPGA, with GTS Reset Sequencer from version 25.3 to 25.3.1?
Description Following an IP upgrade from version 25.3 to version 25.3.1 of the Quartus® Prime Pro Edition software, there is a port renaming involved for Agilex™ 3 FPGAS or Agilex™ 5 FPGA GTS Reset Sequencer IP. There are two ports that has been renamed for improvement purpose. Resolution For a workaround, you need to update the existing port name to the new ports that are available in the GTS Reset Sequencer IP. The existing ports that will require update are: i_src_rs_refclk_status_bus_out (25.3) --> i_src_rs_refclk_status_bus (25.3.1) o_src_rs_refclk_status_bus_in (25.3) --> o_src_rs_refclk_status_bus (25.3.1)Why is there a fitter failure when using reference clock from HVIO System PLL for FABRIC_USE_CASE in the Agilex™ 3/ Agilex™ 5 FPGA GTS System PLL Clocks IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, user will encounter fitter failure when they are using HVIO Reference Clock for Fabric_Use_Case. Resolution For a workaround, you need to set location assignment based on your selected devices in QSF assignment: Agilex™ 5 Family and Series Density Device Group Package Code Location Assignment A5E 013 A/B B23A/B32A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] A5E 028 A/B B23A/B23A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] 1B [SMHSSIPLLWRAP_X0_Y54_N1956] 4A [SMHSSIPLLWRAP_X121_Y7_N1956] A5E 065 A/B B23A/B32A 1A: [SMHSSIPLLWRAP_X121_Y7_N1956] 1B: [SMHSSIPLLWRAP_X0_Y54_N1956] 1C: [SMHSSIPLLWRAP_X0_Y101_N1956] 4A: [SMHSSIPLLWRAP_X185_Y7_N1956] 4B [SMHSSIPLLWRAP_X185_Y54_N1956] 4C [SMHSSIPLLWRAP_X185_Y101_N1956] A5D 064 A/B B32A 1A [SMHSSIPLLWRAP_X0_Y7_N2406] 1B [SMHSSIPLLWRAP_X0_Y15_N2406] 1C [SMHSSIPLLWRAP_X0_Y99_N2406] 1D [SMHSSIPLLWRAP_X0_Y107_N2406] 4A [SMHSSIPLLWRAP_X159_Y7_N2406] 4B [SMHSSIPLLWRAP_X159_Y15_N2406] 4C [SMHSSIPLLWRAP_X159_Y99_N2406] 4D [SMHSSIPLLWRAP_X159_Y107_N2406] This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the F-Tile JESD204C FPGA IP Example Design fail to generate when the data rate above 23 Gbps with a target development kit selected, showing an error requiring VSR_MODE_HIGH_LOSS even though this option is unavailable in the IP GUI?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, the VSR_MODE_HIGH_LOSS option was removed. User is expected to use VSR_MODE_LOW_LOSS instead, which provides the same functionality previously available in both modes. However, this change is not correctly reflected in the F-Tile JESD204C IP GUI. Resolution To work around this problem in the Quartus® Prime Pro Edition software version 25.3, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.Why is there a simulation failure when we are generating and running the Agilex ™ 5 FPGA Example Design 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence or 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence?
Description Due to a problem in the generated example design for 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence and 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence in Quartus® Prime Pro Edition software version 25.3.1, user will encounter failed simulation result. Resolution For a workaround, upon successfully generated example design, you need to follow the steps accordingly to resolve this problem. Step 1: you are required to go to the generated design example folder, which is: intel_directphy_gts_0_example_design/example_design/rtl_folder Step 2: Open the file top.sv, then make the modification to the reset_sequencer module, sss1 at line 542. Update the o_pma_cu_clk[0] --> o_pma_cu_clk [1:0] Step 3: Modify the pma_cu_clk[0] in line number 787 in the same file (top.sv) shown below from: i_pma_cu_clk(pma_cu_clk[0]) --> i_pma_cu_clk(pma_cu_clk[1:0]) Step 4: Rerun the compilation and simulation. The example design will be able to pass simulation. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346Why is there "sopcinfo2swinfo.exe: command not found" when running sopc-create-header-files under WSL, or Docker under Windows?
Description An error message like this: sopc-create-header-files: line 182: sopcinfo2swinfo.exe: command not found sopc-create-header-files: sopcinfo2swinfo.exe --input=./peripheral_subsys.sopcinfo --output=/tmp/sopc-create-header-files.1312.tmp.swinfo failed will be seen in the Quartus ® Prime Pro Edition Software version 25.3.1 and earlier, when using the sopc-create-header-files script within the Linux version of the Quartus ® Prime Pro Edition Software, running on the Microsoft* Windows operating system. The Linux version of the tools can be installed under Windows* using WSL, WSL2 or Docker. In all of these cases, the sopc-create-header-files script detects that it is running under Windows* and looks for an internal tool with the suffix “.exe”. However, since the Linux version has been installed, the tool does not have that suffix and so cannot be found by the sopc-create-header-files script. Resolution To work around the problem, either switch to using a Windows* installation of the Quartus® Prime Pro Edition Software, or follow these steps to continue using the Linux installation under Windows*: Under Linux, use the command “which sopc-create-header-files” to find the location of the script. Copy the script from this location to another location of your choice. Make the newly copied script version writable using the command: chmod +w <path to newly copied script> Modify your newly copied script version. Find the following line: windows_exe=.exe and either remove it or add a single # symbol at the start to comment it Use your newly modified version of the script instead of the installed version. This will now execute correctly.Why is the FFT IP missing when using a Agilex™ 5 FPGA device?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.2, you may not be able to find the FFT IP in the IP Catalog when choosing Agilex™ 5 FPGAs as the device. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.2. Download and install patch 0.48 below: Patch 0.48 for Windows (.exe) Patch 0.48 for Linux (.run) Readme for patch 0.48 (.txt) This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1.Why do I see Siemens QuestaSim* and Cadence Xcelium* simulation failure for the F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example?
Description Due to an issue with the Quartus® Prime Pro Edition software version 25.3.1, you may see ModelSim*– FPGA Edition and Xcelium* simulation failures for F-Tile 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Examples. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the EMIF and Ethernet IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and 24.3, you might see hold timing violations in Timing Analyzer when using the EMIF and Ethernet IPs. This problem only refers to Agilex™ 7 FPGA devices. Resolution This problem has been resolved in Quartus® Prime Pro Edition Software version 25.3.