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Why does the GTS HDMI IP Design Example fail to compile in Dual Simplex mode?
Description Due to an issue in Quartus® Prime Pro Edition Software version 25.1, the GTS HDMI IP Design operating in Dual Simplex mode on Agilex® 5 FPGA devices fails during the Analysis and Synthesis stage. This error occurs when an HDMI TX instance with a width of 4 is used together with an HDMI RX instance with a width of 3. Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|reset_sync_txclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|reset_sync_lsclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[2].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[0].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rxclk_sync_gen[1].reset_sync_rxclk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|scdc_i2c_gen.u_i2cslave_scdc|reset_sync_i2c_clk" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_hpd_hdlg|reset_sync" instantiates undefined entity "bitec_hdmi20_reset_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[3].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[2].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[1].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_tx_inst0__hdmi_gts_0__u_hdmi_tx|u_tx_core_phy_intf|TX_XCVR_CLK_SYNC[0].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[2].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[1].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Error(16045): Instance "my_ds_inst_1|my_hdmi_rx_inst0__hdmi_gts_0__u_hdmi_rx|u_rx_core_phy_intf|rx_xcvr_clk_sync[0].u_clock_sync" instantiates undefined entity "intel_hdmi_clock_sync" Resolution This problem is fixed beginning with version 25.1.1 of the Quartus® Prime Pro Edition Software.Why do the TX CLK and RX CLK show unexpected values in the F‑Tile Ethernet Toolkit?
Description The TX_CLK and RX_CLK frequencies are measured using the reconfig_clk in the F‑Tile Ethernet Hard IP. By default, the reconfig_clk runs at 100 MHz. If the user supplies a different reconfig_clk frequency, the values displayed in the Ethernet Toolkit will be inaccurate. Resolution User can calculate the real frequency from the displayed value: Real clock frequency = frequency value in ETK * frequency of reconfig_clk / 100MHzWhy does the Tensor FIR IP generation fail with a missing-file error?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you might see an error related to a missing file when performing Tensor FIR FPGA IP generation. Example error output Info: tensor: "Generating: tensor_tensor_fir_100_vs35orq" Error: add_fileset_file: No such file <user directory>/26.1/quartus/dspba/backend/include/cmd_tools/share/bp2_prog_c.h while executing "add_fileset_file "bp2_prog_c.h" OTHER PATH "$bepath/include/cmd_tools/share/bp2_prog_c.h"" (procedure "gen_files" line 327) invoked from within "gen_files $entity "VHDL"" (procedure "gen_sim_vhdl_files" line 2) invoked from within "gen_sim_vhdl_files tensor_tensor_fir_100_vs35orq" Info: tensor: Done "tensor" with 2 modules, 25 files Info: Finished: Create simulation model Error: SPD file was not generated: <user directory>/tensor/tensor.spd Error: Could not generate simulation scripts There are three operation modes for the Tensor FIR IP: Memory-Mapped non-Memory-Mapped Auto-Programming The missing -file error occurs when using modes 1 and 2. Mode 3 is not affected by the error. Resolution A patch is available to fix this problem in Quartus Prime Pro Edition Software version 26.1. Download and install patch 0.01dsp below. The error will be fixed in future versions of the Quartus Prime Pro Edition Software.Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why the pre-code setting doesn't work for F-Tile PMA and FEC Direct PHY IP on FGT channels?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, the pre-code function doesn’t work on FGT channels with F-Tile PMA and FEC Direct PHY IP. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the typical web server page is not displayed when using binaries created from the HPS Baseline and Legacy System Example Design in Agilex® 5/Agilex® 3 FPGA device in release 25.3.1 and 26.1?
Description Due to a problem in the HPS Baseline and Legacy System Example Design for Agilex® 5 FPGA and Agilex® 3 FPGA devices, the web server application just shows the “It works!” message instead of the typical view, in which it briefly describes the development kit, shows the state of some LEDs, and allows them to be controlled. This problem is observed in Quartus® Prime Pro Edition software version 25.3.1 and 26.1 releases. Resolution There is no workaround for this problem. This problem will be fixed in a future release.Why does FPGA core configuration fail in HPS early IO release mode of Arria® 10 SoC device?
Description In Arria® 10 SoC device HPS early IO release mode, you may see FPGA core configuration failure when you use the following command to generate core rbf. quartus_cpf --convert --hps -o bitstream_compression=off <sof_file> <rbf_file> This problem occurs because uncompressed core rbf file may be too large to cause configuration failure. Resolution To work around this problem, please use the following command to generate rbf files. quartus_cpf --convert --hps -o bitstream_compression=on <sof_file> <rbf_file>How to set current strength for Agilex® 7 FPGA HPS dedicated IO?
Description Due to a problem in Quartus® Prime Edition Software version 25.3.1 and prior, you may see the following error when you set current strength for HPS dedicated IO in qsf file or in assignment editor. Current strength logic option is set to 2/4/6/8mA for pin intel_agilex_hps_0_<IO_name>~pad， but setting is not supported by I/O standard 1.2-V. This problem occurs because HPS dedicated IOs in Agilex™ 7 device are configured to I/O standard 1.2-V by default in Quartus, instead of I/O standard 1.8-V. Resolution To work around this problem, please set the HPS IO to I/O standard 1.8-V in qsf file or in assignment editor, and then set current strength for the pins to make it work.Why do multiple pulses occur on flr_received signals when host do function level reset to an endpoint device of Scalable Switch IP for PCI Express*?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1 and later, you may see multiple pulses on flr_received signal of Scalable Switch IP in FLR operation. Resolution To work around this problem, you should respond to flr_completed signal for each pulse on flr_received. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does Nios® V/g processor experiences data corruption when it is enabled with TCM and ECC?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, data corruption might occur in Nios ® V/g processor designs with tightly coupled memory (TCM) and error correction code (ECC). Both features must be enabled to observe this problem. It is caused by an RTL bug in the processor, which renders failure when the processor executes sw (store word), followed by sh (store halfword) or sb (store byte) instructions. For example, # Initially, value of Y is 0x0001CCCC. li t0, 0x12345678 li t1, 0x200A sw t0, 0(Z) # Store 0x12345678 word into Z sh t1, 0(Y) # Store 0x200A into lower half of Y Result Final value of Y Description Expected 0x0001200A Upper-half of Y is preserved as 0x0001, while lower-half of Y is changed to 0x200A. Actual (Data Corruption) 0x1234200A Upper-half of Y is corrupted to 0x1234, while lower-half of Y is changed to 0x200A. The 0x1234 is from the previous Store Word (sw) instruction. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 26.1, apply either one of the solutions below: Disable TCM. Disable ECC. This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.
