Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.How do I address known software issues for Stratix V devices in the Quartus II software version 11.0?
Description There is a single patch available to address known software issues for Stratix® V devices in the Quartus® II software version 11.0. This patch will be updated periodically with the latest software fixes, so please check here periodically for updated files. You can refer to the readme file for the date the file was updated and a list of software fixes. Download and install the Stratix V software issue patch from the appropriate link below. Note that you should not install any non-Stratix V patches on Quartus II software version 11.0 after installing this patch. Download the version 11.0 Stratix V software issue patch for Windows (.exe) Download the version 11.0 Stratix V software issue patch for Linux (.tar) Download the Readme for the Quartus II software version 11.0 Stratix V software issue patch (.txt) Altera recommends upgrading to the Quartus II software 11.0 SP1 for designs targeting Stratix V devices.How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.1 SP1?
Description There is a single patch available to address known software issues for Stratix® V, Arria® V, and Cyclone® V devices in the Quartus® II software version 12.1 SP1. This patch will be updated periodically with the latest software fixes. Check here periodically for updated files. You can refer to the readme file for the date the file was updated and a list of software fixes. Resolution Download and install the Stratix V/Arria V/Cyclone V device patch 1.dp7 from the appropriate link below. You must install the Quartus II software version 12.1 SP1 before installing this patch. Note that you should not install any non-Stratix V/Arria V/Cyclone V patches on the Quartus II software version 12.1 SP1 after installing this patch. Patch 1.dp7 includes all the fixes from previously-released patches. You can install 1.dp7 over the previous device patches, but you do not need to install the previous device patches before installing 1.dp7. For Windows, users must install both part 1 and part 2 to apply all fixes for patch 1.dp7. For Linux, the single patch contains all fixes for patch 1.dp7. Download the version 12.1 SP1 patch 1.dp7 part 1 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp7 part 2 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp7 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp7 (.txt) To install a previously-released version of the Quartus II software version 12.1 SP1 Stratix V/Arria V/Cyclone V device patch, select the appropriate link below. Device patch 1.dp1 Download the version 12.1 SP1 patch 1.dp1 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp1 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp1 (.txt) Device patch 1.dp4 Download the version 12.1 SP1 patch 1.dp4 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp4 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp4 (.txt) Device patch 1.dp6 Download the version 12.1 SP1 patch 1.dp6 for Windows (.exe) Download the version 12.1 SP1 patch 1.dp6 for Linux (.tar) Download the Readme for the Quartus II software version 12.1 SP1 patch 1.dp6 (.txt) Related Articles Errata - Known Stratix V timing model issues in Quartus II software version 12.1 SP1 The .qip/.sdc files in the project .qsf are reordered when opening a project or re-generating IP in the Quartus II software version 12.1 SP1. Why is the dedicated transceiver refclk pin Vicm lower than the specification in the Arria V GX device datasheet when using Quartus II software versions 12.1sp1 and earlier? Error (170208): Cannot place <X> nodes into a single ALM Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen5_postproc.cpp, Line: 266 Internal Error: Sub-system: FSAC, File: /quartus/fitter/fsac/fsac_clkbuf_fix_atom_netlist.cpp, Line: 1698Why does IP generation fail for some IP cores in Intel® Quartus® Prime Standard 19.1?
Description Due to missing Perl libraries in the Intel® Quartus® Prime Standard Edition software version 19.1, you may see various errors when generating some Platform Designer IP Cores. Error and Info messages indicating missing Perl library: Error: " Failed to find modelu Error: qsys-generate failed with exit code 1 Info: Can't locate Getopt/Long.pm Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition software version 19.1. Download and install Patch from the appropriate link below. Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Windows (.exe) Download patch Intel® Quartus® Prime Standard 19.1 Patch 0.01 for Linux (.run) Download the Readme for Intel® Quartus® Prime Standard 19.1 Patch 0.01 (.txt)Error (10232): Verilog HDL error at bitec_dp_rx_ss_audio.v(420): index 64 cannot fall outside the declared range [63:0] for vector "fifo_data_x2chan_mux"
Description Due to a problem in the Quartus® II software version 14.0, you may see this error when compiling a design that contains the DisplayPort IP that has more that 2 Audio receive channels enabled. Resolution To work around this problem in the Quartus® II software version 14.0, replace the existing file <IP variation name>/bitec_dp/rx/ss/bitec_dp_rx_ss_audio.v with the attached version of this file. bitec_dp_rx_ss_audio.v This problem has been fixed starting in the v14.1 release of the Quartus® II software.How can I access the Stratix V ES device JTAG port on the Stratix V ES FPGA Development Kit using the FACTORY instruction?
Description The Stratix® V GX ES FPGA Development Kit contains a Stratix V ES device and MAX® V device in the JTAG chain. In order to issue the FACTORY instruction into the Stratix V ES device, the .jam file must be modified by changing the IRSCAN instruction to bypass the MAX V device. Since the MAX V is the second device in the JTAG chain, change the line from IRSCAN 10, 81; to IRSCAN 20, ; You can use this Jam STAPL file to issue the FACTORY instruction into the Stratix V ES device on the Stratix V GX ES FPGA development kit. Resolution You must issue the JTAG FACTORY instruction after each power up because powering down and powering up the device puts the device back into secure mode. To issue the JTAG FACTORY instruction, follow these steps: 1. Before powering up the board, press the S2 button (pgm_load). 2. While pressing S2, power up the board and issue the FACTORY instruction by executing the .jam file using quartus_jli with the following command: quartus_jli -c<cable> -aISSUE_FACTORY factory.jam 3. After step 2 is done, release the button S2. 4. You can now access the Stratix V ES device JTAG port.Error (210007): Can't locate programming file sfl_enhanced_5sgxma4k2.sof
Description You may be receiving the "Error (210007): Can\'t locate programming file sfl_enhanced_5sgxma4k2.sof" when trying to convert your Stratix ® V GX .sof file into a .jic file using the Quartus® II software version 12.0. This error is caused due to a missing sfl_enhanced_5sgxma4k2.sof file. Resolution To correct this issue you will need to download the sfl_enhanced_5sgxma4k2.sof file and place it into the \quartus\common\devinfo\programmer directory of your Quartus II software version 12.0 then regenerate your .jic file. Related Articles Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_devices.cpp, Line: 7672 Can not locate the SFL sof file: <filename>Why do I see hold time violations in Triple Speed Ethernet IP Core with Quartus II v15.0?
Description Due to a problem in Quartus® II software version 15.0, you may see marginal hold time violation especially in multi-channel Triple Speed Ethernet IP Core designs that target Arria® V, Arria® 10 , Cyclone® V and Stratix® V device families. Resolution To work around this issue, add the following Synopsys Design Constraint file (.sdc) constraints for Fitter into your project SDC file. if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] 0.0ns } else { set_min_delay -from [get_keepers {*<tse_entity_name>*}] -to [get_keepers {*<tse_entity_name>*}] <value> } *Note: Increase the “<value>” from “0.1ns” to “0.2ns” if the hold time violation persisted. Refer to “Table 2-2: Recommended Quartus II Pin Assignments” in Triple-Speed Ethernet MegaCore Function User Guide for other related recommendations. For TSE IP with IEEE 1588v2 feature enabled and target Arria V device family, apply the following patch in addition to the workaround above: Please download the appropriate Quartus® II software version 15.0 patch 0.14 from the following links: Download the version 15.0 patch 0.14 for Windows (.exe) Download the version 15.0 patch 0.14 for Linux (.run) Download the Readme for the Quartus II software version 15.0 patch 0.14 (.txt) This is scheduled to be fixed in a future release of the Quartus II software.Why don't I see an difference in simulation results when I change the Tx drive strength settings of the IBIS-AMI transceiver models?
Description You will not see any difference in drive strength of Altera® Tx IBIS-AMI models if only the Ivod IBIS-AMI parameter is changed. You also need to change the appropriate selected analog IBIS-AMI model. The following document details how to change the Tx drive strength. IBIS-AMI Drive Strength Process (Right-click, Save as)