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NiosV and juart-terminal
I had a project which works fine under niosII. I upgrade all the project with niosv and all seems fine except printing values in juart-terminal. Here is the main code : #include <stdio.h> #include "system.h" #include "altera_avalon_pio_regs.h" #include <altera_avalon_i2c.h> #include <unistd.h> #include <string.h> int main() { //* ALT_AVALON_I2C_DEV_t *i2c_dev; //pointer to instance structure alt_u8 txbuffer[20]; alt_u8 rxbuffer[20]; float co2Concentration = 0; float temperature = 0; float humidity = 0; alt_u32 co2U32 = 0; alt_u32 tempU32 = 0; alt_u32 humU32 = 0; ALT_AVALON_I2C_STATUS_CODE status; i2c_dev = alt_avalon_i2c_open("/dev/i2c"); //Ouverture du périphérique i2c et récupération d'un pointeur if (NULL==i2c_dev) { printf("Error: Cannot find /dev/i2c\n"); return 1; } //set the address of the device using alt_avalon_i2c_master_target_set(i2c_dev,0x61); //Définition de l'adresse du composant adressé 0x61 pour le SCD30 txbuffer[0]=0x00; txbuffer[1]=0x10; txbuffer[2]=0x00; txbuffer[3]=0x00; txbuffer[4]=0x81; //Remplissage du buffer pour configurer le SDC30 en Continous measurement status=alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 5,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL while(1) { txbuffer[0]=0x02; txbuffer[1]=0x02; //Remplissage du buffer pour déterminer si les données sont prêtes alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant rxbuffer[1]=0x00; usleep(3000); // Il faut attendre au moins 3ms avant de demander la réponse alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 3,ALT_AVALON_I2C_NO_INTERRUPTS); //Récupération de la réponse du composant si rxbuffer[1]==0x01 alors les données sont prêtes if(rxbuffer[1]==0x01) { txbuffer[0]=0x03; txbuffer[1]=0x00; //Remplissage du buffer pour la lecture des données alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2, ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer de lecture et récupération des données usleep(3000); //Wait 3ms before data available alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 18,ALT_AVALON_I2C_NO_INTERRUPTS); //Read datas co2U32 = (alt_u32)((((alt_u32)rxbuffer[0]) << 24) | (((alt_u32)rxbuffer[1]) << 16) | (((alt_u32)rxbuffer[3]) << 8) | ((alt_u32)rxbuffer[4])); tempU32 = (alt_u32)((((alt_u32)rxbuffer[6]) << 24) | (((alt_u32)rxbuffer[7]) << 16) | (((alt_u32)rxbuffer[9]) << 8) | ((alt_u32)rxbuffer[10])); humU32 = (alt_u32)((((alt_u32)rxbuffer[12]) << 24) | (((alt_u32)rxbuffer[13]) << 16) | (((alt_u32)rxbuffer[15]) << 8) | ((alt_u32)rxbuffer[16])); memcpy(&co2Concentration, &co2U32, sizeof(co2Concentration)); memcpy(&temperature, &tempU32, sizeof(temperature)); memcpy(&humidity, &humU32, sizeof(humidity)); } printf("---------------------------------------------------------\n"); printf("SCD30\n"); printf("Concentration de CO2 : %f ppm\n",co2Concentration); printf("Température : %.1f °C\n",temperature); printf("Humidité relative : %.1f %% \n",humidity); usleep(500000); } } I put a breakpoint just before the printf and the values are good : but when i print the values in the juart-terminal : I can't figure out why the printf does not work as i expect. Someone could help me to understand this problem ? Thanks Eric
Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger
Hello, I have to reopen another topic from last year: Arria 10: Remote Update may brick FPGA and Factory Fallback won't work | Altera Community - 315011 Opposed to my comments in the original thread, enabling the watchdog does not trigger a factory fallback if the application Image is wrongly aligned. This brings me back to this scenario of the original post: Invalid application load image location, i.e. start of application load is shifted by1-10 Byte (Manually induced error scenario) --> The reprogramming sequence starts but never completes and no fallback to the factory load is performed. => The FPGA is completely unresponsive unless programmed via JTAG It is obvious, that the this scenario might be an exotic error scenario, however we require a robust setup and have to make sure, that the FPGA remains accessible under any circumstances, so we need the Factory Fallback mechanism to work reliable! We have this boot procedure: Boot into factory image (0x20 as boot address in flash boot sector 0x00 to 0x1F). We have certain HW which is sensible to boot up timing so we need this to guarantee an identical and reliable boot up procedure. Boot from factory load into application image Check for power up boot: Read RU_RECONFIG_TRIGGER_CONDITIONS register for power up state (0) do not reconfigure if Bit 4,2,1,0 is set Set AnF bit: write "1" to RU_CONFIGURATION_MODE Set application image address RU_PAGE_SELECT Enable Watchdog Set RU_WATCHDOG_TIMEOUT & RU_WATCHDOG_ENABLE Reconfigure: write "1" to RU_RECONFIG In Application mode we only read the RU_RECONFIG_TRIGGER_CONDITIONS as status info We do not write the RU_WATCHDOG_ENABLE nor RU_RESET_TIMER registers I have run tests, with a Application Image being stored with an offset of -2 Bytes, i.e. the first 2 Bytes of the Application image are not stored in Flash Memory and the full image is shifted in its Flash storage. In this case, the FPGA gets stuck in an unresponsive state, when trying to load the application image. There is no fallback to the factory load happening, no CRC error, no watchdog triggering. As a best guess I could assume it might be related to this Note in 1.3.1. Remote System Configuration Mode that the factory fallback mechanism won't work for Arria 10 FPGAs if the last 576 Bytes of the bitstream are corrupted. Note: The fallback to the factory image does not work under the following conditions: If the last 576 bytes of an unencrypted application image bitstream are corrupted. Intel recommends that you examine the last 576 bytes of the unencrypted application image before triggering the application image configuration. But I have noticed that the binary images of the FPGA bitstream vary in size. So there is no way to check explicit memory locations for these 576 Bytes. Is there any way to identify this section? My Questions: Why is the factory configuration fallback mechanism not working in the above described scenario? The Factory load image is valid! How can I examine/validate a FPGA bitstream in flash memory before executing it? best regards Fabian
Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0
Hi, We are working with the following differential clock input pins: - CLK_[T,B]_2[A,B]_[0:1] (P/N) - CLK_[T,B]_3[A,B]_[0:1] (P/N) Could you please confirm the allowed common-mode voltage range for these differential clock inputs?
NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)
Hello, I have a problem with loading elf file. Signal dbg_reset_out (used for resetting HDL components) is inactive (low) when I'm using "niosv-download -r -g exeFile.elf" command (Q25.1 Std, v25.2.1 Ashling GDB Server, Linux OS, MAX10 device, NIOS V variant m). The same command for Q24.1 Std (previous version of Ashling GDB Server, the same OS and PC) works. For me temporary solution is using additional option -o (OpenOCD instead of Ashling ® RiscFree GDB Server). Is there any better solution?
Agilex 7 Decoupling capacitor scaling factor
Hi! I have got my power estimate from quartus prime based on our requirement, which is " board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , where would i get this value? is it related to FPGA part(AGFB027R24C2I2V) or the max current rating of my convertors? Thanks, Vigneswaran
licensing.altera.com never worked
Hi Altera, I need to apply Nios V free license, https://licensing.intel.com went to https://www.altera.com/SSLC , I signed in successfully, however the FPGA Self Service Licensing Center.never worked, I got the error "You do not currently have access to this site." for few weeks, see picture below. Please help fix this issue. Thanks.
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