Welcome to the Altera Community!

This post demonstrates a 200G-4 Ethernet link running on Agilex 7 FPGAs using F-Tile transceivers. It walks through the full link bring-up process, including Auto-Negotiation and Link Training, followed by stable high-speed data transmission using 53.125G PAM4 lanes over QSFP-DD. The demo provides real-time visibility into link status, signal integrity, and error metrics, and evaluates performance across loopback configurations and varying cable lengths. The result highlights reliable link initialization, consistent throughput, and robust operation under practical system conditions.

This post demonstrates how F-Tile Dynamic Reconfiguration in Agilex 7 FPGAs enables real-time switching between 400G and 4×100G Ethernet without system downtime. It explains how predefined configuration profiles, system-level data path reconfiguration (MAC, PCS, FEC, PMA), and software control enable predictable, production-ready transitions. The article also highlights support for multi-rate Ethernet, protocol flexibility, and continuous traffic validation, showing how FPGA-based systems can adapt dynamically to changing network conditions.

This blog recaps Altera’s presence at Mobile World Congress 2026, highlighting a shift in the wireless industry from experimentation to real-world deployment. It covers key announcements such as validated interoperability with Broadcom for 5G-Advanced and early 6G radio systems, production-ready massive MIMO reference designs, and growing momentum in satellite (NTN) communications. The post also showcases FPGA-based AI use cases running directly at the RAN edge and emphasizes the strength of Altera’s partner ecosystem. Overall, it presents practical advancements in scalable, power-efficient wireless infrastructure built on Agilex FPGAs.

This post explores a practical shift from a fixed-function ASSP to a programmable FPGA platform in response to evolving system requirements. As bandwidth demands, protocol diversity, and feature complexity increased, limitations in a 400G optical transport ASSP and uncertainty in vendor roadmap made continued reliance difficult. The team transitioned to an FPGA-based approach, enabling customization of protocols and features while aligning the system more closely with real usage needs. The article also highlights benefits such as design reuse, reduced hardware variants, simplified inventory management, and greater control over long-term system evolution.

This post explains how the definition of mid-range FPGAs has evolved from logic density to system-level capability. It highlights how Agilex 5 FPGAs address modern embedded and edge requirements by integrating compute, AI acceleration, memory, connectivity, and security into a single platform. The article also covers how Agilex 5 D-Series extends mid-range performance with higher logic density, increased bandwidth, and enhanced AI capabilities, enabling more complex and data-intensive workloads while maintaining efficiency and design simplicity.