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Agilex5 Eagle ES, NIOS-V + TSE IP
Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit. NIOS executes firmware and able to read the PHY registers. But when connecting the ethernet cable nothing seems to happen, status registers does not change and no link-up is reported. Does anyone know of any examples using the NIOS-V and TSE with RGMII interface that I can look at to troubleshoot the issue ?20Views0likes1CommentOnce again about CTRL+L
Hello. Consider this message as mere feedback. I moved from Quartus 20.1 to 25.1 and discovered that now what Ctrl+L does depends on the focus: it deletes a line if in the text editor and starts the compilation in other cases. That's quite inconvenient, if you ask me. And there was already a thread dedicated to this peculiarity. From my standpoint, the keyboard shortcut must do one and only one thing. :-) Maybe developers will take that into account for that in the future. Also, if there is a possibility to fine-tune shortcuts — point me in that direction. I failed to find that.64Views0likes8CommentsWhere to find BSDL files on Altera Web?
Hi, I needed to get BSDL file for device A5ED013BB32, but can't find it. At first I've tried page: https://www.altera.com/design/devices/resources/models/bsdl But all links on that page refers to Intel website with message "Oops, something went wrong!" or to Altera website with message "Sorry! No results were found." After a lot of bad trials I've found that it is possible to find the BSDL files using: https://docs.altera.com/search?content-lang=en-US&customSort=Relevance and try to search for BSDL Model A5ED013BB32 Then it will show download link: Agilex™ 5 Device IEEE 1149.6 Compliant BSDL Model for A5ED013BB32A – (1591-pin VPBGA) Until the main page with links to BSDL files will be fixed, it would be great inform users, that all links are not working, and they have to search manually at docs.altera.com for phrase similar to: BSDL Model device_name Martin4Views0likes0CommentsCyclone V E with or without internal scrubbing
Good day, we are using Cyclone V E 5CEFA5F23I7N The handbook respectively the product ID tells, that this component does NOT provide the Option Internal Scrubbing. To have Internal Scrubbing the product ID should show the SC instead of the N as the last digit like 5CEFA5F23I7SC. Is that correct?1View0likes0CommentsCYCLONE IVE ODDR delay mismatch
Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec. I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses. I'm attaching the project, hoping some experts can help me. The ddr registers are correctly instantiated, but in the timing analysis, the bit(3) coming out of the fpga is delayed compared to all the others: TIMING ON BUS_A: TIMING ON BUS_B: REGULAR DELAY: BIG DELAY: The only difference I see is that the "slow" pins are both also Vrefs (pin 105 and pin 80): Could this be the reason? regards, LUCA.45Views0likes6CommentsDisplay port TX SST not working.
Hi, I am working on an existing project where Display Port Transmitter MST (multi stream) is already present and working. In the current version I just need to convert that transmitter into a Dispaly Port TX SST (single stream). The result is that, starting from the design example i got a version which works only up to 3840x2160 30Hz and does not at 3840x2160 60Hz. In both cases the training is completed and lane allocated adt 5.4GHz. Bun in tha case of 60 Hz I do not see any image. The Quartus Prime Pro used is 17.1.2 for Windows. I do not know where to check for debug more. Kind Regards, Paolo.8Views0likes1Comment10M04SCU169I7G issue.
The Malaysian factory feedback the following material issue.Regarding the defective parts, re-balling has been performed, but the problem persists.Please help analyze, confirm, and resolve this issue. Details are attached. NSY production found 19pcs of PCBA (KNA-68010-0000-51-3MC1) with Program Altera failure which is related to the defective P/N 1060-8520 FPGA (U21). Voltage measurement on V_3V3_S5 (R60) which is associated with the affected component showed 1.5V instead of the expected 3.3V. The impedance value of the related passive component was measured & no abnormal values were found. Currently, 7pcs of the 1060-8520 FPGA (U21) have been reworked and the units passed the retest The remaining boards are currently on hold in production line and pending further disposition. Kindly advise on the next action. PN:1060-8520 MPN:10M04SCU169I7G DC:2546/2539/2549 FR:25/846 2.96%6Views0likes0CommentsQuartus Prime 17.0 and Modelsim License Transfer
I am currently working at Valeo in Chennai, India and I have licensed versions of Quartus Prime 17.0 and ModelSim.I would like to transfer these licenses to a colleague who is based at the same location. Could you please provide support or instructions on the necessary steps to complete this transfer? Best regards, Dhanasekhar REDDY Valeo Chennai20Views0likes2CommentsQuesta 2 licenses?
I got a new work PC (WIndows 11) recently, so I downloaded Quartus Prime Lite 25.1. At the time, I also included Questa Altera Edition in the download. But I didn't try to use Questa. Last week, I read the directions on going to the SSLC and got a license so I could start using Questa. I got the license file, put it in a folder, and followed the directions to set it up in the Environment Variables. I then tried to use Questa and I'm getting the error "Unable to Checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER) is set correctly and then run 'lmutil lmdiag' to diagnose the problem." So I dd that. It seems that I have two license files. One looks like it was set up automatically when I originally downloaded Quartus and Questa and the second that I got from the SSLC. Looking in the Environment Variables, under User variables for [my_user_name], there is a variable SALT_LICENSE_FILE with a value of C:/Users/[my_user_name]/questa_lic.dat. And under the System variables there is a variable called SALT_LICENSE_SERVER with a value of C:\[the_folder_I_setup]. I didn't set up the first environment variable. The second one is the one I entered according to the instructions on the SSLC. Looking at the first license file with a text editor, I see that it is using the MAC address of my laptop's wifi adapter. And looking at the second license file, I see that it is using the MAC address of my laptop's wired Ethernet adapter. I think I was on wifi when I originally downloaded everything. And I was wired when I got the license from the SSLC. What should I do? Which license file should it be using? Why are there two variables and two license files? Since the wifi and wired connections on any computer always have different MAC addresses, is it not possible to use Questa with both? In other words will I always have to be using one of these connections and not the other? That would stink. Thanks.25Views0likes5Comments
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Recent Blogs
2 MIN READ
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
1 day ago0likes
In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
10 days ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
10 days ago0likes
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
11 days ago0likes
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
13 days ago0likes