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Many FPGA designs hit a power wall before they hit a logic wall. The enclosure is sealed, the rack has a fixed power envelope, or the board controller has to run every hour the system is on. In each case, the question is the same: how much work can you fit within the available power budget? The answer is mostly set long before the first power estimate. It’s set by the fabric architecture: how signals are registered, how data moves, and how densely logic packs. That’s where Agilex® 2X does its power work, and it does it differently at each end of the portfolio. Why does power set the limit now? Power used to be a line item checked late in a design. In many systems it’s now the first constraint. Data center line cards and accelerator platforms work inside rack-level power and cooling budgets. Radios and satellite payloads live with thermal limits that don’t move. At the other end, board controllers, motor drives, and root-of-trust devices never switch off, so every milliwatt they draw, they draw all day. Those are two different power problems. A bandwidth-heavy system needs more work per watt. An always-on control system needs fewer watts. A portfolio that solves only one of them sends designers to a new architecture when the requirement changes. Agilex 2X addresses both through the HyperFlex® fabric architecture: 3rd Gen HyperFlex fabric targets performance per watt, while HyperFlex-LP targets low power. How does HyperFlex reduce fabric power at the same frequency? 3rd Gen HyperFlex fabric architecture places registers throughout the routing fabric, enabling efficient pipelining and retiming. As congestion and utilization increase, routing paths can become longer and slower; HyperFlex registers help maintain higher performance under these challenging conditions. Each generation has further refined this approach, as reflected in the performance curve. At the same frequency, Agilex 27 fabric uses approximately 40 percent less power than Agilex 7 fabric.¹ As the chart shows, Agilex 7 made a step of similar size over Stratix 10. Agilex 27 also delivers 1.8X performance per watt versus Agilex 7. Separately, it runs at more than 15 percent higher Fmax, on average, versus Agilex 7.¹ For systems where cooling and power delivery set the limit, the power reduction often matters more than the speed gain. It’s headroom you can spend on the workload. Where else does the power go? 3rd Gen HyperFlex fabric can move large amounts of data across the device. But in bandwidth-heavy designs, implementing wide data movement in soft interconnect consumes logic and routing resources and can increase compile time, leaving fewer fabric resources available for the application workload. Agilex 27 hardens that job in the HyperFlow data network. Data moves across the device at multi-terabit-per-second rates without consuming soft logic or adding routing congestion. Logic packing helps too. Recompile an existing design for Agilex 27 FPGAs in Quartus® Prime Pro Edition Software and it packs 5 to 10 percent more densely, using fewer adaptive logic modules (ALMs). Together, those changes cut the power spent on design infrastructure and leave more of the budget for the application. That shows up three ways: Reaching target performance within rack or enclosure power budgets Reducing cooling and operating costs Giving more of the thermal budget to the workload instead of to moving data What does low power mean for I/O-centric systems? At the other end of the portfolio, the problem changes. A board and rack controller, a motor drive, or an interface bridge rarely needs peak fabric performance. It needs plenty of I/O across a broad voltage range, a small footprint, and a power draw low enough to disappear into the system budget, because it never switches off. That’s the job Agilex 22 is built for, and it’s why Agilex 22 uses HyperFlex-LP, a low-power implementation of the HyperFlex fabric architecture. HyperFlex-LP optimizes programmable logic for lower area, lower power, and higher packing density. It uses the familiar Quartus Prime design flow while tuning the fabric to minimize power. Agilex 22 FPGAs are right-sized for I/O-centric systems, offering high I/O density for board and rack control, motor control, root-of-trust, and interface-bridging applications. Why does one architecture matter for power? Power savings are easy to lose in a migration. A new architecture means new IP, new timing behavior, and new tools. Each change is a chance for the power estimate to drift from what ships. Agilex 2X keeps one architecture and one software experience across every family. Every device is supported by Quartus Prime software, extended by QuartusIQ, the AI expert companion for Quartus Prime software. Design workflows, IP, interfaces, and engineering knowledge carry forward from family to family. The takeaway Power efficiency is decided by the architecture, long before the board is built. Agilex 2X tunes one fabric for two different power problems: more work per watt where bandwidth rules, and lower power where the FPGA is always on. Read the Agilex 27 architecture white paper Notes and disclaimers ¹ Based on Altera’s modelling of Agilex 27 versus Agilex 7 device fabric performance and power. Results may vary. Agilex 2X device architecture and feature descriptions are preliminary and subject to change. Interface support, device options, and performance figures are Altera targets and vary by device. Capabilities and availability vary by family and series.

Aerospace, defense, and high reliability systems must deliver demanding processing performance while operating in environments where extreme temperatures and mechanical stress can compromise electronics. Developers must also plan for long service lives, supply continuity, and mission requirements that continue to evolve. Altera’s defense-grade Agilex FPGA and SoC FPGA portfolio brings these priorities together. It combines scalable programmable performance with military-temperature and ruggedized packaging options, while U.S. wafer fabrication supports supply resilience. For system designers, that means more ways to balance performance, deployment conditions, and long-term program needs. Designed for harsh environments Defense-grade Agilex devices offer military-temperature options supporting operation from −55°C to +125°C, helping designers target extreme hot and cold environments in applications such as outdoor radar, vehicle-mounted communications, and airborne sensors. A wider specified temperature range can provide more thermal headroom and may reduce heating or cooling needed solely to keep a narrower-rated FPGA within its specified limits, easing size, weight, and power trade-offs. Ruggedized packaging options, including leaded-ball configurations, help address temperature cycling, vibration, and shock in mobile and deployed systems. For customers with tin-lead assembly requirements, leaded-ball options can also avoid a separate reballing step and its associated process-control and qualification burden. Addressing environmental durability and manufacturing compatibility early can reduce the risk of late-stage redesign. Together, these capabilities help designers bring Agilex FPGA performance into demanding mission environments with fewer thermal and manufacturing workarounds. Temperature grades and packaging options vary by device and configuration. Supply resilience for long-life platforms Aerospace and defense platforms often remain in service for many years, making continuity of supply an important consideration. Agilex FPGAs provide a domestic source of wafer fabrication that supports supply resilience and helps customers plan for long program lifecycles. Performance and choice across Hi-Rel applications Defense applications call for different combinations of performance, power efficiency, and integration. The Agilex portfolio spans low-power, cost-optimized Agilex 3 FPGAs, mid-range Agilex 5, high-performance Agilex 7, and Agilex 9 Direct RF-Series FPGAs. This range supports applications from embedded processing for industrial and automotive to high-bandwidth communications, radar, and electronic warfare. Altera’s HyperFlex® architecture supports higher clock frequencies and processing throughput through Hyper-Retiming and Hyper-Pipelining. Alongside FPGA programmability, these capabilities offer a flexible foundation as mission-critical systems integrate more sensing, processing, and AI within constrained platforms. Availability Initial shipments of defense-grade Agilex FPGAs are planned for the first quarter of 2027, with software support targeted for Quartus® Prime Design Software version 27.1. For more information about defense-grade device options, contact your local Altera sales representative.

Meet QuartusIQ Quartus® Prime (Pro Edition, 26.3) introduces the QuartusIQ AI Expert Companion, bringing FPGA expertise and project-aware AI assistance directly into your design workflow. Get guidance where you work, explore design decisions, and connect knowledge with hands-on tasks. Alongside new capabilities in system design, power analysis, and embedded development, QuartusIQ creates a more connected FPGA development experience. QuartusIQ: FPGA Expertise, Closer to Your Design QuartusIQ integrates AI assistance directly into the Quartus GUI, providing access to FPGA knowledge and project-aware guidance within your design environment. You can ask questions, explore design recommendations, and find relevant information without leaving Quartus. QuartusIQ connects to supported LLM providers using your own API key. Beyond general-purpose AI assistance, QuartusIQ combines FPGA-specific knowledge with project summaries to help make questions and recommendations more relevant to your design. Whether you're learning a new tool in Quartus, looking for documentation, or investigating approaches to design closure, this context can help you identify useful next steps. QuartusIQ also supports practical programming and configuration tasks. Analyze and convert programming files, discover connected hardware, and program devices through JTAG. Supports Secure Device Manager (SDM) commands, QSPI compatibility checks, and Remote System Update (RSU) image generation, extending these capabilities to additional device-configuration tasks. For teams exploring AI-assisted development beyond the Quartus GUI, Model Context Protocol (MCP) integration makes QuartusIQ expertise accessible to external AI workflows. And there is also an extension for Visual Studio Code that lets QuartusIQ work with GitHub Copilot. MCP integration and agent capabilities are available, providing additional ways to incorporate FPGA-specific knowledge and tools into connected development environments. Together, these capabilities make QuartusIQ a companion for finding information, understanding your project, and completing tasks, with recommendations you can review and apply to your design. Visual Designer Studio: Keep the System in View Visual Designer Studio (VDS) expands Platform Designer system import to include generic components and parameterized RTL, allowing more of your existing design to be incorporated into a visual workflow. Cross-probing between VDS and other Quartus applications makes it easier to navigate between the system-level view and related design information. Clock/reset fanout simplifies logical hierarchies. Improved separation of source and generated files makes revision control easier to manage. Expanded support for Arria 10, Cyclone 10 GX, and Stratix 10 devices provide greater design flexibility. Board awareness (beta) introduces board-package creation and use within VDS, adding board-level context to the system-design environment. Power & Thermal Analyzer: Streamline Power Analysis Workflows Power analysis is most valuable when it's integrated into the design process. With Tcl scripting and example scripts, Power & Thermal Analyzer makes it easier to automate analysis workflows, maintain consistency, and reassess power consumption as designs evolve. Several usability enhancements simplify working with device resources and analysis results. Device-aware resource filtering and controls help prevent invalid actions, while improved device selection, graphical displays, and numeric alignment make the interface easier to navigate. Common power-analysis reports are now available in the Report Database, providing access to power-analysis results within a familiar reporting environment. HPS is also modeled as a resource rather than a global setting, making its treatment more consistent with other design resources. Embedded Development: Expanded Platform Support and Design Examples Quartus Prime (Pro Edition, 26.3) expands embedded development support with the following: Initial Agilex® 27 SoC Hard Processor System (HPS) enablement, including Simics support and baseline hardware and software reference designs. For Agilex 5 E-Series devices, expanded FreeRTOS support includes Cortex-A76 symmetric multiprocessing (SMP) capabilities, along with the re-release of the bare-metal library. New Agilex 5 E-Series design examples help developers explore a wider range of embedded architectures. These include heterogeneous Linux and FreeRTOS operation using Bao static partitioning, cache-coherent accelerator examples for both operating systems, and Ubuntu and Docker-based Linux configurations. A new bare-metal "Hello World" example provides a simple starting point for development. Updated Nios V design examples include Triple-Speed Ethernet (TSE) designs with FreeRTOS TCP/IP and web-server functionality for Agilex 3 and Agilex 5 devices. Additional enhancements include initial Agilex 27 Nios enablement and soft-processor debug module improvements. Additional Productivity, DSP Builder Machine Learning, and Device Support Enhancements Node Finder improvements include a persistent top-level hierarchy, single-click navigation, and side-by-side search results, making it easier to explore a design while maintaining context. DSP Builder expands machine-learning capabilities with new CNN layers, expanded activation-function support, and AI Tensor DSP optimizations. Enhanced network import, quantization, and automatic sizing simplify implementation, while new demos and MATLAB/Simulink MCP-based agentic workflows support model creation, updates, and verification. Device enablement also expands for Agilex 5 E-Series and D-Series, including additional temperature-grade support for Agilex 5 D-Series devices. AI models with FPGA AI Suite FPGA AI Suite 26.3 expands the tools and capabilities available for developing and integrating AI workloads. Beta features include spatial compiler and developer APIs that enable customers to build CNN and transformer models with examples (ResNet-8, Qwen 3.5, Majika, GPT-neo), and configurable external memory interface (EMIF) connectivity. Additional updates include a new Altera Model Zoo, better integration with the Altera Video and Vision Processing, SoC/x86 profiling, and VDS examples. New production-quality design examples for Agilex 3 Memory-to-Memory designs. These additions provide more options for model exploration, data-path integration, and performance analysis. Explore Quartus Prime (Pro Edition, 26.3) From project-aware AI assistance to enhancements in system design, power analysis, embedded development, and AI workloads, Quartus Prime Pro 26.3 provides new capabilities for your FPGA projects. Visit the Quartus Prime Pro website to learn more. What's New in the Quartus® Prime (Pro Edition) Design Software Download the Quartus® Prime (Pro Edition) version 26.3 Software Learn more about QuartusIQ Read the QuartusIQ white paper Learn more about FPGA AI Suite software Agilex 3 FPGAs and SoCs overview Agilex 5 FPGAs and SoCs overview Agilex 7 FPGAs and SoCs overview

PACKET CLASSIFICATION | FPGA | NETWORKING + SECURITY Every packet decision starts with classification. Routers, firewalls, SmartNICs, security gateways, and service-edge platforms must determine which policy applies before traffic can be forwarded, blocked, inspected, redirected, or prioritized. TCAM earned its place in these systems because it provides predictable lookup behavior and native ternary matching for ACL and LPM workloads. But as policy databases grow, search keys widen, and rules change more frequently, the traditional approach of scaling specialized ternary memory creates tougher tradeoffs in capacity, power, resource utilization, and system integration. Altera Stellar solutions takes a different approach. Instead of scaling packet classification by building ever-larger ternary-memory structures, Stellar turns classification into an optimized search problem that runs on configurable FPGA resources. The result is an FPGA-native path for large, dynamic packet-classification tables without giving up the policy semantics that made TCAM useful in the first place. TCAM scales through memory expansion. Stellar scales through search intelligence.  Keep the TCAM semantics. Change the scaling model. Stellar preserves the intent of ACL, LPM, and multi-field classification, but changes how those rules are represented and searched. The Stellar Software Stack organizes policies into optimized graph structures, partitions the rule database, and continuously manages those search structures as the database evolves. The hardware then executes the search using configurable FPGA search engines while rule information is stored in conventional memory resources. Depending on the configuration, Stellar can use on-chip M20K memory, eSRAM, DDR, or HBM. That gives architects more freedom to balance throughput, capacity, latency, power, and FPGA resource use around the needs of the actual system. Use dense memory where it makes sense, and intelligence where it matters A traditional TCAM combines storage and comparison circuitry inside specialized ternary-memory arrays. That architecture delivers deterministic matching, but scaling the table means scaling the specialized comparison structure as well. Stellar separates rule storage from search execution. Ternary information can be represented as value-and-mask data in conventional memory, while graph organization and software-managed optimization direct each search toward the relevant parts of the database. As tables grow from thousands of entries toward hundreds of thousands or millions, this creates a different path for scaling capacity and power. The white paper goes deeper into why this matters, including the tradeoffs between TCAM and Stellar, the role of memory hierarchy, and a set of Stellar configurations spanning different key widths, capacities, memory resources, and projected five-tuple performance. Bring classification into the programmable datapath The value is bigger than the lookup engine itself. Stellar is designed to operate inside the FPGA alongside packet parsing, telemetry, encryption, traffic management, host-interface logic, and customer packet-processing RTL. For system architects, that means classification can become part of the same programmable platform already handling the datapath. A firewall can pair large, dynamic ACL processing with the rest of its traffic pipeline. A router can combine LPM and policy enforcement with programmable networking functions. A SmartNIC can integrate flow classification with offload and customer-specific acceleration. That system-level flexibility is especially relevant for 100GE to 400GE designs where classification must scale without consuming the platform that surrounds it. Read the full whitepaper! The full Altera white paper, Altera TCAM Alternative Solutions Scale Packet Classification to Millions of Rules for Networking Equipment, explains the architecture behind Stellar and the design choices that make it different. It covers TCAM fundamentals and scaling limits, Stellar graph-based search and software partitioning, memory-hierarchy options, configuration examples, quantitative architectural comparisons, dynamic updates, and deployment use cases across networking and security. Read the white paper See how Stellar uses search intelligence, configurable FPGA resources, and a flexible memory hierarchy to create a scalable alternative for large ACL and LPM workloads.

September 28, 2026 The next generation of embedded systems will not be defined by compute alone. It will depend on how quickly, reliably, and intelligently systems can move data from the physical world into AI engines and turn insights back into action. That message came through clearly at Embedded World North America 2026, held September 22–24 at the Anaheim Convention Center. For Altera, the show provided an opportunity to highlight a growing collaboration with NVIDIA and demonstrate the role of FPGAs in high-performance edge AI architectures. Connecting sensors to AI with flexibility and determinism At the center of the story was NVIDIA Holoscan Sensor Bridge technology. The solution creates a high-bandwidth, low-latency path between real-world sensors and GPU-based AI processing, an increasingly important capability for robotics, industrial automation, intelligent video, medical systems, and other physical AI applications. FPGAs are well suited to this role because they can provide deterministic processing, flexible I/O, and protocol adaptation close to the sensor. Rather than forcing every application into the same hardware configuration, FPGA-based designs can be tailored to performance, connectivity, and latency requirements of a specific system. In the show’s keynote, NVIDIA Vice President Deepu Talla described the value of this flexibility: “You can select any of the Altera FPGAs depending on the application and pair them with any of the NVIDIA frameworks.” Altera’s post noted that Altera offers Holoscan Sensor Bridge solutions spanning 10G to 100G, where 25G and 100G offer significantly more bandwidth compared to other Holoscan ecosystem partners, helping developers scale connectivity for demanding edge workloads.         The result is a practical sensor-to-compute architecture: Altera FPGAs handle the flexible, deterministic front end, while NVIDIA platforms provide the accelerated environment for AI and robotics workloads. An ecosystem approach to accelerating development The demonstrations also underscored that successful edge AI deployments require more than individual components. Developers need reference designs, production-ready boards, and partners that help bridge the gap between evaluation and deployment. Altera’s growing Holoscan ecosystem includes more than 10 reference designs and partner boards. These building blocks can help teams reduce integration effort and move faster from proof of concept to a real-time AI product. One example was on display at Altera partner Critical Link’s booth. Critical Link was recognized as a Best in Show Award winner in the AI & Machine Learning category at the show. Visitors to the booth could see a live demonstration of a 5-camera Holoscan Sensor Bridge solution, using Critical Link’s MitySOM-A5E as the featured Agilex® 5 FPGA hardware platform. The demonstration showed how an Agilex 5 FPGA-based system can help bring sensor data into an NVIDIA-powered AI pipeline while preserving the low-latency, high-bandwidth behavior required by edge applications.               From 10G to 100G: Building the data plane for edge AI Altera’s Holoscan Sensor Bridge solutions are designed to make the sensor-to-GPU path faster and more adaptable. A recent Altera technical blog describes 10G, 25G, and 100G reference designs, including a 25G design on Agilex 5 SoC FPGAs for multi-camera sensor data flow and accelerated processing at the edge. In this architecture, the FPGA serves as the data plane: connecting to diverse sensors, aggregating streams, adapting protocols, and preprocessing data before it reaches the NVIDIA GPU. That division of labor helps reduce data-movement bottlenecks while preserving deterministic timing and giving developers room to evolve the system as sensor interfaces and AI workloads change. Altera Technical Holoscan blog for Robotics: Altera Pushes the Boundaries of Edge AI with New Holoscan Sensor Bridge Solutions | Altera Community - 355665 Watch the 25G Holoscan demo video: YouTube/Altera Why the sensor-to-compute path matters As AI moves into physical environments, system designers are balancing several competing requirements: Real-time response: Applications such as robotics and industrial inspection cannot always afford the delay of sending raw sensor data to a remote system. High-bandwidth data movement: Modern sensors generate increasingly rich data streams that must be transported without creating a bottleneck. Deterministic behavior: Safety-critical and industrial systems need predictable timing and consistent performance. Design flexibility: Product teams must support different sensors, interfaces, and deployment conditions without redesigning the entire platform. Faster development: Reference designs and ecosystem partnerships can shorten the path from concept to production. The Altera and NVIDIA approach addresses these needs by combining FPGA-based connectivity and processing with GPU-accelerated AI. It gives developers a modular foundation for building systems that can adapt as sensors, models, and application requirements evolve. Building what comes next at the edge The conversation at Embedded World North America 2026 pointed toward a broader shift in embedded design. Edge systems are becoming intelligent, connected, and increasingly autonomous, but their performance still depends on the data path that feeds them. By pairing Altera FPGAs with NVIDIA platforms and collaborating with partners such as Critical Link, developers gain more options for designing that path. The combination of flexible hardware, high-speed connectivity, and accelerated AI can help transform raw sensor input into timely decisions at the point where data is created. For teams developing the next generation of robotics, industrial automation, intelligent vision, and physical AI systems, this is the opportunity: Build a sensor-to-compute architecture that is fast enough for today’s workloads, flexible enough for tomorrow’s requirements, and ready to scale from demonstration to deployment. Learn more about Altera’s Physical AI-related Solutions: Holoscan: https://www.altera.com/fpga-solutions/sensory-interfaces Robotics: https://www.altera.com/fpga-solutions/robotics-solutions-stack Video: https://www.altera.com/fpga-solutions/video-solutions-stack