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DDR4 Problem Migrating from Arria 10 016 to 048
We have a board design that supports an F29 package Arria 10. It has two DDR4 interfaces running at an 1866 data rate. In the past an 016 chip with DDR4-2400 ICs worked fine. We needed more logic so we migrated to an 048. Because of parts availability we had to migrate to DDR-3200 ICs. The board layout has not changed and we believe the various power supplies and clocks are working fine. The 048 design fails calibration and won't even allow running "EMIF toolkit - Create Memory Interface." It hangs and times out. If I turn off address / command leveling the design still fails calibration but now I can create a memory interface and see the calibration results which show a complete failure with write and read margins. The design is badly broken but we don't know if it is the 048 or DDR4, or a combination of both. The DDR4 IP was regenerated and adjusted for the DDR4-3200 ICs. We do see PLL lock with signaltap and can actually run Efficiency monitor. So the core is supplying a good clock to the fabric. Any suggestions are welcome! Thanks, Mike11Views0likes2CommentsQuesta 2 licenses?
I got a new work PC (WIndows 11) recently, so I downloaded Quartus Prime Lite 25.1. At the time, I also included Questa Altera Edition in the download. But I didn't try to use Questa. Last week, I read the directions on going to the SSLC and got a license so I could start using Questa. I got the license file, put it in a folder, and followed the directions to set it up in the Environment Variables. I then tried to use Questa and I'm getting the error "Unable to Checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER) is set correctly and then run 'lmutil lmdiag' to diagnose the problem." So I dd that. It seems that I have two license files. One looks like it was set up automatically when I originally downloaded Quartus and Questa and the second that I got from the SSLC. Looking in the Environment Variables, under User variables for [my_user_name], there is a variable SALT_LICENSE_FILE with a value of C:/Users/[my_user_name]/questa_lic.dat. And under the System variables there is a variable called SALT_LICENSE_SERVER with a value of C:\[the_folder_I_setup]. I didn't set up the first environment variable. The second one is the one I entered according to the instructions on the SSLC. Looking at the first license file with a text editor, I see that it is using the MAC address of my laptop's wifi adapter. And looking at the second license file, I see that it is using the MAC address of my laptop's wired Ethernet adapter. I think I was on wifi when I originally downloaded everything. And I was wired when I got the license from the SSLC. What should I do? Which license file should it be using? Why are there two variables and two license files? Since the wifi and wired connections on any computer always have different MAC addresses, is it not possible to use Questa with both? In other words will I always have to be using one of these connections and not the other? That would stink. Thanks.53Views0likes6CommentsTiming Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.406Views0likes32CommentsPIPE Direct Reset Release Sequence
Hello, I am debugging R-Tile Avalon Streaming FPGA IP for PCI Express in PIPE Direct mode on an Agilex 7 device. My goal is a custom PCIe/CXL soft controller. I was originally targeting x16, but I am currently reducing the setup to x1 for bring-up/debug. I have questions about the PIPE Direct Reset Release Sequence (Figure 50). Clock domain for reset release control It is not clear to me when ln0_pipe_direct_pld_tx_clk_out_o becomes valid enough to be used for control sequencing. Should lnX_pipe_direct_pld_pcs_rst_n_i be released(Step 4 in Figure 50) by logic clocked with ln0_pipe_direct_pld_tx_clk_out_o after lnX_pipe_direct_tx_transfer_en_o (Step 3 in Figure 50)is observed, or is it acceptable to control this sequence from another stable FPGA system clock domain with synchronization? SignalTap trigger for reset release debugging I tried using ln0_pipe_direct_pld_tx_clk_out_o as the SignalTap clock and triggering on the first rising edge of lnX_pipe_direct_phystatus_o(Step b in Figure 50)during DETECT, but I cannot reliably capture that pulse. What is the recommended trigger/event to verify that the reset release sequence is operating correctly in hardware? Missing phystatus_o before cdrlockstatus_o in P0 From Figure 50, I expected a phystatus_o pulse (Step g in Figure 50)in the P1 power state before cdrlockstatus_o asserts. In my test, that phystatus_o pulse does not appear, cdrlock2data_o never becomes 1(Step m in Figure 50), but reset_status_n_o still goes high (Step n in Figure 50), in conclusion the raw RX data from PIPE Direct IP appears corrupted/unstable. Is there a known reason this can happen? Also, I would like to verify this reset release sequence in RTL simulation, not only on hardware. However, for PIPE Direct mode, there are no example design available, so at the moment I do not have a way to validate this behavior with RTL simulation. If anyone has experience debugging Figure 50 on real hardware, I would appreciate guidance. Thank you.2Views0likes0CommentsAgilex 7 I Series Development Kit: External hardware access error when programming
I have a compiled design that I would like to test that implements Ethernet on F-Tile. When I try to program the FPGA with my bitstream, it stops and prompts me with the following errors: Would anyone know how to fix this or have insight on why this is happening?13Views0likes2CommentsAgilex5 - Bridge AXI F2H - read transactions
Hi, we are using in our design the bridge F2H between FPGA and HPS, which is a bus ACE5lite 256bits. Several masters AXI 64bits in our design will contact it via an interconnect. In Write, no problem, we can attaquer this interface in « narrow transfers » 64b over 256b, in conformity with ARM specification. But in READ, the SoC user manual (814346, 2026.01.09) says §11.5.1 : « The HPS F2H interface has a fixed data size of 256-bits. This interface allows for narrow burst sizes less than 256-bits However, if a fabric initiator generates a transfer narrower than the interface width (i.e., less than the 256-bits wide data and a nonzero burst size), there is no guarantee that the HPS F2H interface will respond with narrower data aligned on non-256-bit boundaries of the 256-bit data bus. For example, if ARADDR = 0x0010_0000, ARSIZE = 0x4, and ARLEN = 0x3, the HPS F2H interface returns two beats of 32 bytes per beat followed by two null cycles, instead of four beats of 16 bytes per beat. Altera recommends that you add width adaptation interconnect logic between the fabric initiator and the HPS F2H interface to ensure that the narrow-width data is packed/unpacked properly.” « the HPS F2H interface returns » : means it is sure that… , we will be able logic tranlation 256>64 considering that data returned on RDATA bus will fill all width of 256b (if enough read bytes of course). If “there is no guarantee…” is correct, it is a problem as there is no Read Strobe with bus RDATA in AXI spécification ; and we can not determine which bytes of which BEATs of transfert have to be considered. Last possible interpretation : the ‘width adaptation interconnect logic’ recommanded by Altera concerns more the transformation of ARADDR/ARSIZE/ARLEN by our interconnect at bridge input (AR* parameters are requests of read sent by our masters should be translated by interconnect before to be presented to bridge). Can you tell me the right meaning ? Thanks and regards2Views0likes0CommentsAgilex5 - Timings configuration
Hi, in document 813918, I have a question regrading method to define NOR timing, table 115, using Text_delay as conditions for input timings. this parameter is said dependant of frequency of interface (note 195), but only one value (max) is given (no min), and this one is greater than half-period and even at clock frequency 166MHz which seems to be considered by datasheet. I don't understand. Can we get simply Setup and Hold timings for Agilex inputs for AS configuration interface ? Thanks and regards2Views0likes0CommentsTimings eMMC
Hi, latest datasheet of SoC « 813918/2026.01.05 » lists in paragraph « HPS SD/eMMC Timing Characteristics » the constraints of eMMC, applicable to memory component but does not define any timing data in input/output of SoC. There is no Tco min/max of CMD/DATA at SoC output, as well as Tsetup/hold of CMD/DATA at SoC input. Can you provide Tco and Tsetup/hold for eMMC usage (Legacy, HS_SDR, HS_DDR, HS200, HS400) ? thanks2Views0likes0Comments
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Recent Blogs
2 MIN READ
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
6 days ago1like
In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
15 days ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
15 days ago0likes
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
16 days ago0likes
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
18 days ago0likes