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F-Tile xcvr placement on DK-DEV-AGF023FA
I have an Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. I have 1 F-Tile working with PCIe Gen4x16, and want to use the second for 400Gb Ethernet. I have used the F-Tile channel placement tool, which results in a valid placement. See attached. I have been plagued with placer message such as the following. Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 400g block but the location only supports stream(s) [7, 11, 13, 14]. I have swapped bit orders and other trials, and they all lead to a similar error. Given the placement of the QSFPDD on the board, I need to used FGT Quads 2 and 3 I have also tried to use the 100G-4 F-Tile configuration, which move the FGT usage to Quad 1. And I result it the following error: Error(22811): The specified block ftile_eth|u0|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 100g block but the location only supports stream(s) [1, 2, 3]. I have tried the example design, changing the device to the above board, but the build fails. Using Quartus 25.3.0 What is needed to move past these errors? Thanks, Ed.18Views0likes3CommentsOnce again about CTRL+L
Hello. Consider this message as mere feedback. I moved from Quartus 20.1 to 25.1 and discovered that now what Ctrl+L does depends on the focus: it deletes a line if in the text editor and starts the compilation in other cases. That's quite inconvenient, if you ask me. And there was already a thread dedicated to this peculiarity. From my standpoint, the keyboard shortcut must do one and only one thing. :-) Maybe developers will take that into account for that in the future. Also, if there is a possibility to fine-tune shortcuts — point me in that direction. I failed to find that.2Views0likes0CommentsUnable to download Quartus
Trying to download Quartus 25.3.1 Pro, but installed throws this every time Tried for several days now with the same result. Also tried another installed ( 25.3) and the Lite (25.1) installed with the same result. My internet connection is working fine.275Views0likes9CommentsQuartus Prime 25.1 installation issue
Hello to the community. I had some problems while installing Quartus Prime. Though in the end I finally succeeded, maybe someone will point out what I've done wrong. Here are the steps: I started installation by executing the setup.bat command file. Left the configuration all default as well as the installation directory. The software successfully unpacked the files and started installing the help component. After a while it reported that it was done by the "Installation Completed" message and full progress bar. I waited for a while and then forced this window to close. It displayed some error message and quit. No further progress was observed after some time, so I killed that process too. After that I played a little with installation directories, turning on and off the antivirus, but nothing helped. In the end I came up with the following solution: Again, execute the setup.bat. Disable help installation. Wait until come other component reports it's done and do not responding. Kill that process and see some error window. Wait until installation is done. Install the help. I'm attaching a few screenshots depicting this behavior for the Ashling RiscFree component below. Though in the end I did obtain the software, it is still quite annoying and time-consuming. Maybe there is some tweak to make it smooth? I'm using Windows 10 version 10.0.19045.6466. Thanks in advance.19Views0likes2CommentsAgilex 5 Power
Hello, I am using two A5EC043BB32AI4S devices and I am now planning their power rails. I have two questions. Is it possible to design one power supply (one regulator) per rail for both FPGASs There is a requirement in the PCB Design Guideline User Guide for ‘Recommended VR Accuracy (% of Vnom)’ of ±0.5%. What is the meaning of this requirement? As I understand it, this refers to the Voltage accuracy (excluding line regulation and load regulation). This is a very strict requirement, and most power regulators cannot meet it. What is the practical meaning or impact of not meeting this requirement? In the datasheet, however, only a maximum value is specified, and it is usually around 3%. P.S:the requirement of the ±0.5%.are in table 24 in PCB Design Guidelines (HSSI, EMIF,MIPI, True Differential, PDN) User Guide14Views0likes2CommentsNios V Logic Element not include
Hi, Currently, we are using Nios V/m in Max10 (10M08) with Quartus 24.1std. However, we observed that the logic elements for Nios V/m are not reflected in the compilation. We also tried recreating the project, but the issue persists — the logic elements are still not shown or included. Best Regards, QY30Views0likes1Comment
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In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
1 day ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
1 day ago0likes
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
2 days ago0likes
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
4 days ago0likes
Dell’s Open RAN radio platforms use Altera Agilex® 7 SoC FPGAs to deliver secure, adaptable 5G infrastructure. The FPGA architecture enables hardware-rooted security and post-deployment updates, allowing radio units to evolve with new protocols and threats while maintaining trusted edge infrastructure.
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