Recent Content
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
FPGA issue on electronic board
The FPGA is visible via the JTAG probe, and we can program firmware. It seems to run correctly. This is a good point. At this stage, we have tried to implement I2C accesses to configure a clock component on the electronic board and unfortunately, we did not succeed. We observed a strange behaviour on I2C pads. I2C pads are bi-directional pads and implemented in open drain mode : to output a ‘0’ value, pad is configured as output and driven to ‘0’ by internal logic of the FPGA. to output a ‘1’ value, pad is configured as input and signal is driven to ‘1’ by an external pull-up resistor. As the external clock component is not configured (and does not output clocks by default) we use for this firmware As any bi-directional pad, whatever is the pad direction configuration, electrical signal on external IO should always be replicated on <dout>. But it is not the case on one of the banks of our FPGA. To simplify the tests, we have implemented a smaller testcase firmware : 2x bi-directional IOs (SDA and SCL) A weak pull-up (in IO pad) on each of these two IOs (to emulate I2C external pull-up) We have chosen IO which are not routed on the electronic board (NC balls) We performed the test on two different banks (6B and 6D). Both banks are HVIO banks are powered with 1V8. The bi-directional pads behave as expected : io pad signals (driven by <scl_t> and <sda_t>) are replicated on <dout> pins of bidir primitives (<scl_i> and <sda_i>). The bi-directional pads do not work. <dout> pins of bidir primitives (<scl_i> and <sda_i>) are tied to ‘1’. The two designs are 100% identical excepted the pin locations !! We tried to output a clock signal on some IOs pads of the bank 6D configured as output (pins without pull-up neither in pad or on electronic board) and we can observe a clock waveform of 1V8 amplitude on the scope, which means the bank 6D is powered with 1V8. Unfortunately, we currently have only one functional FPGA board. Others should arrive by the end of the week. We are using Quartus Prime Pro 25.3.1 (patch 1.02) What could be the reasons explaining this difference in behaviour between two identical banks ? Could it be : a Quartus tool bug ? a silicium issue ? a bank power supply problem ?
Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?
Error(23098) when using IPM_IOPLL on Agliex 7
I am trying to use the IPM_IOPLL in my project on the Intel Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) but whenever i use it i get the following error: Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_0_2 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted. Info(20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info(20274): Successfully committed planned database. Error: ERROR: An error occurred during automatic periphery placement Error: Quartus Prime Fitter was unsuccessful. 3 errors, 0 warnings Error: Peak virtual memory: 9478 megabytes Error: Processing ended: Tue Feb 24 11:20:55 2026 Error: Elapsed time: 00:01:22 Error: System process ID: 177973 Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 109 warnings When i use an IOPLL generate from platform designer the project compiles successfully. The code for the IPM_IOPLL is below: inst_mac_iopll : IPM_IOPLL generic map( REFERENCE_CLOCK_FREQUENCY => "100.0 MHz", N_CNT => 1, M_CNT => 10, C0_CNT => 8, C1_CNT => 16, C2_CNT => 32, OPERATION_MODE => "direct", PLL_SIM_MODEL => "Agilex 7 (I-Series)" ) port map( refclk => clk, -- 100MHz input reset => g_rst_d1, outclk0 => i_mac_clk, -- 125MHz output outclk1 => mac_half_clk, -- 62.5MHz output outclk2 => i_ipb_clk, -- 31.25MHz output locked => i_locked ); I am not sure what is causing this error. I am using Quartus Prime Pro 24.3.1 with the DK-SI-AGI040FES board. ThanksQuartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"
Hi, I am working with Quartus Prime Pro 24.1. Unfortunately, I have encountered several issues when compiling my project on different machines and operating systems. While the project compiles and builds the bitstream without any problems on Windows Server 10, I receive a fatal error on Windows 11 and Ubuntu 24 for the same design, at the "support-logic Generation" phase. All machines are relatively powerful and equipped with more than 32 GB of RAM. I have also disabled parallel compilation, but the error still occurs. Additionally, I tested Quartus 24.3.1 and observed the same behavior. Error on Ubuntu24 machine: Error on Win11 machine: Does it have to do with our JESD float license or the JESD IP itself? I'm asking because it seems that we have this issue only with projects that include Altera JESD IP. I would appreciate it if you could help me resolve this issue. Best, SAHConfigurable transceiver enable
I need to enable transceiver channels in groups based on a board parameter read during board start-up. If the parameter is '0', channels 1 and 2 are enabled, channels 3 and 4 are disabled. If the parameter is '1', channels 3 and 4 are enabled and 1 and 2 are disabled. I want to explicitly disable the unused channels to save power and prevent them from driving outputs. The only way to disable channels that I've figured out is to hold the input reset of the reset controller asserted. Then I'll need 2 reset controllers, one for each group of 2 channels. I'll also need 2 PLLs since they are interconnected with the reset controller. Is this the way to do it or is there a better way? Best regards, Julia
Access to System MAX design for Agilex 5 kit
For the Agilex 7 I-Series Transceiver-SoC Development Kit (DK-SI-AGI027Fx), the design source for the on-board System MAX10 device is included in the installer package, under examples. For the Agilex 5 E-Series 065B Premium Development Kit (DK-A5E065BB32AEx) it is not. Is the System MAX design for the Agilex 5 kit available from somewhere else? If not, is that because of the preliminary status of that kit, or will that design never be made available?
MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application
Hello, I’m using Intel MAX10 Remote System Upgrade (RSU) with: CFM0 = Factory CFM1 = Application The firmware‑triggered RSU upgrade completes successfully, but after reconfiguration the device boots back into the Factory image instead of the Application image. Below is the design setup: RSU IP instantiated and connected over SPI Avalon‑MM master interface of RSU IP is exported to user logic onchip_flash data interface is also exported and visible in the top level Firmware performs erase/write/verify through the exported Avalon‑MM interface Autoboot decision is based on a bit stored in UFM, read at startup No external power cycle occurs during RSU (warm reconfiguration). Below are the observations: RSU programming via firmware completes without errors MAX10 reconfigures after RSU Cold boot works correctly Programming the App image via JTAG works Issue occurs only after warm RSU (no power cycle) Autoboot selection is controlled via a bit stored in UFM. For this I have exported the AV-MM I have the below questions: Is it expected that RSU does not automatically re‑enter autoboot logic? After warm RSU, must user RTL explicitly regenerate a boot / autoboot event? Are there recommended MAX10 reference patterns for autoboot handling after RSU? Thanks for any guidance or references.Why does the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP fail on Window* OS?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the example design generation of High Bandwidth Memory (HBM2E) Interface Agilex® 7 FPGA M-Series FPGA IP might fail. This problem only occurs on Windows* OS. This problem occurs because the location of quartus_py.exe file has changed but the IP still calls the file from the previous location. Resolution To work around this problem, copy the quartus_py.exe file from <Quartus installation path>\qcore\bin64\quartus_py.exe to <Quartus installation path>\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
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