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No access to the Self Service Licensing Center (SSLC)
I have a Quartus license and tried to access the Self Service Licensing Center (SSLC), but when I log in with my account, I get a message saying that I do not have access to this site (I attached a screenshot). What should I do? When I sent a help message through the link on this page, I received an automatic email directing me to seek help through other channels, such as the Altera community forum.
ASx4 Interface debug in MSEL=111 (JTAG mode)
Hi, could you, please, help me understand what is happening here: I am working with an Agilex3 FPGA (fuses are on factory default, no keys programmed, etc.) MSEL=111, so we are in JTAG mode I am trying to debug the NOR flash interface through Configuration Debugger / QSPI Controller and SFDP page. I have connected an oscilloscope. When I press Read button without QSPI Debug Session Activate button pressed, I see some NOR flash transactions on the oscilloscope and get back an Error 0x515 Unknown error and nothing is read in the SFDP window. So I try the QSPI debug session active way, and when I press it I get a lot of content but anything below the SFDP line in the tree structure is random at each read button press AND I do not see any NOR flash transaction at all on the ASx4 interface. (Did it several time, so yes, I did not forgot press the trigger active button.) So questions: is this an expected behavior? Copilot suggest that ASx4 interface is not initialized when MSEL=111 and I am reading some internal "garbage" If this is expected, should not the Quartus Programmer tool (which reads MSEL=111 correctly) warn me that I should not expect any meaningful output in this debug window? Is there any way to use the JTAG interface here as supposed: test the interfaces for problems? if yes, how?! (I stuck for a few more days/weeks with MSEL=111, so if that is the solution just let me know.) Thanks, Peter
Pushing FPGA Fabric Performance Toward 1 GHz with Agilex® 7
2 MIN READ Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
Preloader/U-Boot Compilation Failure
General Background: I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the necessary files for a successful boot sequence from a uSD card (FPGA and the ARM processor (HPS)). The Objective: I want to reconfigure the HPS functionality (Mux) for pins 53 and 54 from their current GPIO to CAN BUS. I need to ensure a successful boot from the uSD card with the updated hardware definition and Device Tree. Issue Description: Preloader/U-Boot Compilation Failure After successfully implementing the changes in Quartus and Platform Designer and after successfully generating the BSP files (bsp-editor), I'm attempting to run the "make" command to build the Preloader/U-Boot image. The process starts and creates the uboot-socfpga directory, but the compilation consistently fails with several errors, and the final boot image is not updated. Extension of the successfully completed steps: I've modified the Platform Designer (Qsys) mux functionality to reconfigure the HPS peripheral pins (GPIO53-GPIO54) for CAN BUS functionality. I've integrated the new HPS component into the top-level VHDL project. I've Generate a full VHDL compilation in Quartus. Using the "SoC EDS Command Shell", I launched the BSP-Editor and loaded the updated "settings.bsp" file. After generation, the "hps_isw_handoff" and "generated" directories were updated. I have manually verified the output files (pinmux_config.h) to confirms that CAN1 is now correctly configured in the pin multiplexing settings. What should I do?JTAG_UART stuck in printf
I'm trying to setup a NiosV and have printf appear over the JTAG_UART. I've used only the default settings when generating the bsp (just the generate command, no set_settings). I notice when I debug, anytime I step over a printf statement, it never returns (also, no print statements appear in the juart-terminal). However, if I just do a direct pointer access to the JTAG_UART base address, I successfully see characters printed in the juart-terminal. Looking in the bsp's summary.html, it appears that it has linked the jtag_uart. Ex: hal.stdout Value = jtag_uart_0. I also have a fair chunk of CPU block ram memory (262 KB total, only using about 16 KB right now for hello world). Any ideas what the issue here is?
Agilex5 HPS2FPGA usage
Hello, I have an Agilex 5E 065B devkit board with Part Number A5ED065BB32AE6SR0. I have created a design in quartus that uses HPS2FPGA communication. I tested the design extensively and now want to configure the FPGA. However, it is not clear to me how the workflow has to be in that case after reading the documentation: https://docs.altera.com/r/docs/814550/current/agilextm-5-fpga-e-series-065b-premium-development-kit-user-guide/overview . Below I list my worklfow (which was not working out): Phase 1: Resotre GSRD I have a compiling quartus design I download the official GSRD JIC from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/ghrd_a5ed065bb32ae6sr0.hps.jic.tar.gz In quartus I open the JTAG programmer and connect the device to my local machine. I power on the device with SW27 set to OFF-OFF-OFF-OFF. After clicking "auto-detect", I right click my FPGA device and click "change file" and select the freshly downloaded jic file. I click "start" and wait till process is completed sccessfully. I insert the HPS board's SD card into my local machine and download the GSRD SD image from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/sdimage.tar.gz I rename the .wic file to a .img file. Then I use Win32DiskImager to flash the image to the SD card. After completion I insert the SD card back into the HPS board. I connect the vertical HPS board pin to my local machine and open PUTTY to target the COM port. A window opens, which stays blank. I set SW27 to OFF-ON-ON-OFF and power on the board. In PUTTY I can see the linux boot logs. I can log in as root without password. Phase 2: I download the U-BOOT hex that matches my device from: https://releases.rocketboards.org/2024.05/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/u-boot-spl-dtb.hex I open a NIOS shell and create a .jic file based on my designs rbf, by typing the command: quartus_pfg -c <my_project>.sof <my_project>.jic -o device=MT25QU128 -o flash_loader=A5ED065BB32AR0 -o hps_path=<hex_file_path> -o mode=ASX4 -o hps=1 This created a .hps.jic file. I set SW27 back to OFF-OFF-OFF-OFF and connect to my local machine and power on the board. In quartus I again configure my newly created jic to the board via JTAG chain. After completion I power off the board and set SW27 back to OFF-ON-ON-OFF. I open a PUTTY window and power on the board. However, this time the PUTTY window stays quiet even after several minutes. So I guess the boot is not happening correctly. I would like to know if there is a substantial error in my workflow or, if there might be a problem in my quartus settings maybe (I have set configuration order to HPS first). I would be very glad if someone could help me with that. Feel free to tell me if any kind of log or additional information is required for understanding the error.
Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi all, I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question: My Target FPGA: Intel MAX 10 (10M25DAF4817G). Reference Design: I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center) . The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1. My Experience: In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1 and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues. [Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available: What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1 as the known stable version for my device family?Is 25.1 (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue? Any insights would be greatly appreciated. Thank you.
recovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top. background: clk freq is 416Mhz; all design use asynchronous reset; after fitting all design, the timing report about recovery violation has -1.8ns. for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network? figure 1: for compasion，I have taken the follwoing screenshot of the common path routing as figure 2 here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns. figure 2:
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