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Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required
Quartus 25.1 usually crashes during fitter, with a number of different crash reports. Here below are two examples: Problem Details Error: *** Fatal Error: Access Violation at 000000BC2DC1E830 Module: quartus_fit.exe Stack Trace: Other 0xbc2dc1e82f: Other 0xbc2dc1e6af: Other 0x1bf404d29ff: End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ------------------------------- Problem Details Error: *** Fatal Error: Module: quartus_fit.exe Stack Trace: Quartus 0x5fb4b: RaiseException + 0x6b (KERNELBASE) Quartus 0x26ad: __ExceptionPtrRethrow + 0x15d (MSVCP140) Quartus 0x19cfe: tbb::detail::r1::current_context + 0x277e (tbb12) Quartus 0x19d78: tbb::detail::r1::current_context + 0x27f8 (tbb12) Quartus 0x17695: tbb::detail::r1::current_context + 0x115 (tbb12) Quartus 0xa2567: FDRGN_EXPERT::run_place_flow + 0xd17 (fitter_fdrgn) Quartus 0xa0018: FDRGN_EXPERT::run_place + 0x188 (fitter_fdrgn) Quartus 0x95135: FDRGN_EXPERT::place + 0x195 (fitter_fdrgn) Quartus 0x2c120: fit2_fit_place_auto + 0xc0 (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x4e6b: fit2_fit_place + 0x33b (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x230ac: qexe_evaluate_tcl_script + 0x66c (comp_qexe) Quartus 0x21be9: qexe_do_tcl + 0x8f9 (comp_qexe) Quartus 0x2a1ad: qexe_run_tcl_option + 0x6cd (comp_qexe) Quartus 0x4119f: qcu_run_tcl_option + 0x6ef (comp_qcu) Quartus 0x29969: qexe_run + 0x629 (comp_qexe) Quartus 0x2abd6: qexe_standard_main + 0x266 (comp_qexe) Quartus 0xbd32: qfit2_main + 0x82 (quartus_fit) Quartus 0x28708: msg_main_thread + 0x18 (ccl_msg) Quartus 0x29912: msg_thread_wrapper + 0x82 (ccl_msg) Quartus 0x2b063: mem_thread_wrapper + 0x73 (ccl_mem) Quartus 0x265df: msg_exe_main + 0x17f (ccl_msg) Quartus 0xcfab: __scrt_common_main_seh + 0x10b (quartus_fit) Quartus 0x1259c: BaseThreadInitThunk + 0x1c (KERNEL32) Quartus 0x5af37: RtlUserThreadStart + 0x27 (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ----------------------------- this happens with every design and with Arria10, Stratix 10 and also Agilex 7. The only way to avoid these Quartus crashes is to run the fitter in Windows "Efficiency Mode", but that makes fitting time more or less double. Any hints?1.8KViews0likes22CommentsInquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5
Hello, According to GTS transceiver reference clock specifications of the Agilex 5 (GTS Transceiver Performance • Agilex™ 5 FPGAs and SoCs Device Data Sheet • Altera Documentation and Resources Center), the RMS jitter integrated from 10 kHz – 20 MHz, including spurs, is indicated as 522fs (maximum value). We are using in our design a 156.25MHz clock (AX3DAF1-156.2500 from abracon), and the measured jitter is ~1ps currently. We would like to know if this specification is for specific performances or if it’s a strict specification. (in our case, it’ll be for a 1G operation) Thanks, Best Regards10Views0likes0CommentsR-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hello, I am implementing a custom soft PCIe/CXL link layer and LTSSM using R-Tile Avalon Streaming IP in PIPE Direct mode, configured as x16. At the moment, link training does not reliably move forward because some lanes receive valid COM/K-code alignment, but the following ordered-set symbols are corrupted. Environment Device / board: AGIB027R29A IP: R-Tile Avalon Streaming FPGA IP for PCI Express Mode: PIPE Direct Link width: x16 Current focus: Gen1 training / Polling / Configuration Custom implementation: custom LTSSM custom symbol lock using COM (K28.5) custom TS1/TS2 decode logic Symptom In Polling.Active and Polling.Configuration , I can see that some lanes captures/decodes TS1/TS2 correctly, but some lanes do not. For example, in the attached SignalTap screenshot: Lane 9 appears to decode the TS2 sequence correctly. Lane 8 shows COM (K28.5) and PAD (K23.7) correctly, but the symbols after that are unstable / corrupted. From the screenshot: Lane 9 example: K28.5, K23.7, K23.7, D24.0, D30.0 D00.0, repeated Lane 8 example: K28.5, K23.7 are visible, but the following TS2 fields fluctuate and do not remain valid/stable. So it looks like: COM-based symbol lock is working at least partially but after COM/PAD, the ordered-set contents on some lanes(random) are corrupted before my soft IP can decode them correctly To verify whether this was caused by my own logic, I captured the affected lanes directly in SignalTap using the first raw 10-bit RX data from the PIPE Direct IP (`ln*_pipe_direct_pipe_rxdata_o`), before any symbol lock/decoding stage in my soft IP. I searched for the COM symbol directly in this raw 10-bit stream and confirmed that the corruption is already present at the PIPE Direct IP output. So this does not appear to be caused by my combinational decode logic; the raw RX data delivered by the IP is already corrupted on those lanes. What I already checked I already checked the following items carefully: Gen1 rxdata interpretation I only decode valid 10-bit portions for Gen1 I do not interpret the don't-care bits in rxdata[31:10] and rxdata[63:42] rxdatavalid qualification TS decode / symbol shift only happens when rxdatavalid0/1 are valid Sampling clock SignalTap capture is done in the corresponding lane RX clock domain not with a shared TX/fabric clock Reset sequence pld_pcs_rst_n_i release is gated after per-lane tx_transfer_en_o I also reviewed cdrlock2data, reset_status_n, phystatus, powerdown sequencing Deskew-related status active channels are detected Current question At this point, I suspect one of the following: lane-specific analog/RX quality issue inside or before PIPE Direct output lane-specific reset/power-up timing issue internal alignment / deskew behavior that I am misunderstanding some required PIPE Direct control/sideband setting that I am missing What I would like to ask In PIPE Direct x16 Gen1, if one lane shows valid K28.5 / K23.7 but the following TS2 symbols are corrupted, what should I check first on the R-Tile side? Are there any lane-specific PMA / RX / PIPE Direct controls that should be reviewed for this symptom? Is there any recommended way to determine whether this is: a true lane analog/RX problem, a deskew/alignment issue, or a reset/bring-up sequence issue? Are there any known recommendations for validating lane integrity directly at the PIPE Direct output during Polling.Configuration?Agilex 5 – Critical HSSI Error in JESD204B Example Design
Hi, I am bringing up the JESD204B interface on the dev kit. For this, I used the "Generate Example Design" option with the following parameters: When I generate the project and start synthesis, it reaches the "HSSI Support Logic Generation" stage, and Quartus reports the following critical error: It turns out that the generated file contains an inconsistency in the generated HSSI metadata. My fix was to replace the entry in: The problem is that after updating the Qsys file, it gets changed back to intel_jesd_RX, and HSSI reports the critical error again. If there is already a fix or workaround for this issue, please let me know. For now, I added a simple script that I run from PowerShell: that replaces this value with the correct one:3Views0likes0CommentsCXL IP type2 ED failed at the final assembler stage due to unlicensed IP in Ver 25.1
Hi supprot teams, I installed Quartus Prime Pro V25.1 and generate tool lic & CXL type1/2/3 lic in SSLC. And I create a project of CXL type2 ed. After click compile button, everything goes fine until the assembler state, the report tells: Error (23714): Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com Warning (115005): Unlicensed IP: "CXL IP for Device Type 2 with Device coherency (6AF7 0185)" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/root_partition/25.1.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/root_partition/25.1.0/final/1/names.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/auto_fab_0/25.1.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/xxx/demo/intel_rtile_cxl_top_0_ed/hardware_test_design/qdb/_compiler/cxltyp2_ed/auto_fab_0/25.1.0/final/1/names.model" Error: Quartus Prime Assembler was unsuccessful. 1 error, 6 warnings And I check the license status in output_files/cxltyp2_ed.asm.rpt : +----------------------------------------------------------------------------------------+ ; Assembler Encrypted IP Cores Summary ; +------------+------------------------------------------------------------+--------------+ ; Vendor ; IP Core Name ; License Type ; +------------+------------------------------------------------------------+--------------+ ; Intel FPGA ; CXL IP for Device Type 2 with Device coherency (6AF7 0185) ; Unlicensed ; ; Intel FPGA ; Signal Tap (6AF7 BCE1) ; Licensed ; ; Intel FPGA ; Signal Tap (6AF7 BCEC) ; Licensed ; ; Intel FPGA ; Unknown (6AF7 FFFF) ; Licensed ; +------------+------------------------------------------------------------+--------------+ But in Tools -> License Setup,I can see feature "6AF7 0185" is valid. So how can I solve this problem. Regards Joseph3Views0likes0Commentsrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top. background: clk freq is 416Mhz; all design use asynchronous reset; after fitting all design, the timing report about recovery violation has -1.8ns. for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network? figure 1: for compasion,I have taken the follwoing screenshot of the common path routing as figure 2 here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns. figure 2:62Views0likes12CommentsOnce again about CTRL+L
Hello. Consider this message as mere feedback. I moved from Quartus 20.1 to 25.1 and discovered that now what Ctrl+L does depends on the focus: it deletes a line if in the text editor and starts the compilation in other cases. That's quite inconvenient, if you ask me. And there was already a thread dedicated to this peculiarity. From my standpoint, the keyboard shortcut must do one and only one thing. :-) Maybe developers will take that into account for that in the future. Also, if there is a possibility to fine-tune shortcuts — point me in that direction. I failed to find that.80Views0likes10Comments
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Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
8 days ago1like
In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. 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Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
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Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
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Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
18 days ago0likes
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
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