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As the industry accelerates its transition from DDR4 to DDR5 and LPDDR5, memory choices are becoming a defining factor in system longevity, performance, and supply continuity. Altera is uniquely positioned to help customers navigate this shift with production-ready DDR5 and LPDDR5 solutions available today across a broad FPGA portfolio. DDR5 Is the New Standard Major memory vendors have announced plans for DDR4 end-of-life plans or significant production reductions, with full transitions to DDR5, LPDDR5, and next-generation memory already underway. While DDR4 will remain available for long lifecycle segments through multiple suppliers, new design starts today are increasingly looking to DDR5 and LPDDR5. Altera’s Head Start in DDR5 and LPDDR5 Unlike competitors still announcing or sampling future devices, Altera delivers DDR5 and LPDDR5 solutions in volume production today: Agilex™ 7 M-Series and Agilex™ 5 devices support DDR5 and LPDDR5 for high-performance and embedded applications Altera is also planning to add LPDDR5 support within Agilex™ 3 devices, reinforcing its long-term design scalability. Competitive Advantage Across Every Market Tier Altera’s memory leadership spans across a range of design requirements: - High-Performance designs: Agilex™ 7 AGM032 and AGM039 support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Mid-Range designs: Agilex™ 5 D-Series support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Power/Cost-optimized designs: Agilex™ 3 support: LPDDR5 up to 2133 MT/s Key Takeaway With DDR5 and LPDDR5 moving from ‘next-generation’ to ‘now,’ Altera offers customers a clear advantage: production-ready memory leadership, a broad and scalable FPGA portfolio, and a smooth transition path from DDR4 to DDR5—without waiting for future silicon.

Using FPGAs and MCUs Collaboratively FPGAs and microcontrollers can be used alternatively in some applications, but they can also be used cooperatively.  FPGAs provide ultimate flexibility, but microcontrollers often include peripherals like USB or wireless interfaces that may be more convenient for communications and updates.  Both devices require supporting circuitry such as power, reference clocks, and storage.  Fortunately, these can often be shared when using FPGAs and microcontrollers together. This blog introduces an open-source tool that enables microcontrollers to load a programming file into a programmable device, and the practical application of this with the Raspberry Pi RP2350 MCU.  An Open Standard for Loading Programmable Devices Loading programmable devices from embedded processors is a common task.  The Jam Standard Test and Programming Language (STAPL) was originally developed by Altera engineers to address challenges in programming programmable logic devices (PLDs) in-system, such as proprietary file formats, vendor-specific algorithms, large file sizes, and long programming times. It provides a software-level standard for in-system programming (ISP), enabling flexibility and platform independence. Figure 1. In-system programming using the Jam File & Jam Player via an embedded processor.  In August 1999, JAM/STAPL was adopted as JEDEC standard JESD-71, making it an industry-recognized solution for JTAG-based programming. The language introduced features like compact file formats, branching, and looping, which reduced programming time and file size—ideal for embedded systems. JAM/STAPL consists of two main components:  Jam Composer: Generates Jam Files (.jam) containing programming algorithms and user data.  Jam Player: Interprets these files and applies JTAG vectors for programming and testing devices.  Over time, JAM/STAPL gained widespread support from PLD vendors, programming equipment makers, and test equipment manufacturers, becoming a cornerstone for in-field upgrades, prototyping, and production programming. Its evolution also included a byte-code format (.jbc) for even smaller files, making it suitable for resource-constrained embedded processors. Recently, Altera updated the license terms of the JAM and JBC players source code to MIT-0, to better clarify the usage rights.  A Practical Example The CycloMod board is an example of an FPGA and microcontroller working cooperatively.  The board combines a Raspberry Pi RP2350 MCU with a Cyclone® 10 LP FPGA in the SparkFun MicroMod form factor.  In this board, the FPGA is connected to some of the edge connector I/O, while the RP2350 is used to provide a flexible USB interface. The boot ROM in the RP2350 is leveraged extensively for firmware and FPGA image updates. Figure 2. CycloMod Board At 22mm x 22mm (including the card-edge connector), the MicroMod form factor is quite compact. This necessitates sharing resources, as there is not much room for multiple oscillators or flash devices.  The 12 MHz crystal oscillator in the RP2350 is easily shared by routing it to one of the GPIO clock outputs.  Both the Cyclone 10 LP device and RP2350 rely on external storage, but this can also be shared.  On this board, the flash is connected to the RP2350 to take advantage of the UF2 loading provided in the boot ROM, and the RP2350 loads the Cyclone FPGA.  The Cyclone 10 LP device supports active configuration with an external SPI flash device, but it can also be configured/programmed passively through JTAG. Figure 3. CycloMod Block Diagram  The STAPL byte code format (sometimes referred to as JBC) is compact enough to be used with microcontrollers like the RP2350.  Altera provides source code for implementing the “players” to process these files in embedded systems.  They offer players for the ASCII (JAM) and bytecode (JBC) versions of the files.   Altera’s Quartus® software provides the option to generate JAM and JBC files.  Since STAPL is a JEDEC standard, other FPGA vendors also support generating these files. Using the open-source code provided by Altera, the RP2350 is able to read a JBC file from flash and load the Cyclone 10 LP FPGA through the JTAG interface.  A Python script is provided to convert the JBC files to the UF2 format, which the RP2350 uses for drag-n-drop programming.  The script also adds a header with the file length and other details.  Thanks to the ingenuity of the UF2 format created by Microsoft, this enables cross platform field updates with zero software to install.  Results and Link to Source Porting Altera’s JBC player to the RP2350 eliminated the need for a second flash device and enabled user-friendly drag-n-drop FPGA updates.  The port is available on GitHub if you want to use this in your system.  https://github.com/steieio/pico-jbc  

We’re gearing up for AOC 2025! From December 9–11, we’ll be at the Gaylord National Resort & Convention Center in National Harbor, Maryland for AOC2025—one of North America’s premier events dedicated to electronic warfare and radar. Visit us at booth #505 to discover the latest innovations in our Agilex™ 9 Direct RF and Agilex™ 5 product families. What to Expect at Altera’s Booth #505:  1. Wideband and Agility Demo using Agilex 9: Overview: Discover the power of frequency hopping with Altera’s Direct RF FPGA, enhancing system resilience and adaptability. Key Features: Demonstrates swift frequency changes and wideband monitoring.  2. Wideband Channelizer Demo using Agilex 9: Overview: Wideband Channelizer features polyphase filter and 65 phases FFT blocks with variable channel support. Key Features: Demonstrates sampling rate that supports 64 GSPS with 32GHz instantaneous bandwidth. 3. Direction of Arrival Demo using Agilex 5: Overview: Explore Direction of Arriaval estimation and signal detection using AI-based approach with deployment of neural networks. Key Features: Demonstrates neural networks implementation using DSP Builder Advanced Blockset (DSPBA), showcasing end-to-end operation running real time inference. 4. Altera COTS Partner Showcase:    Come see our Agilex based COTS boards from partners including Annapolis Microsystems, CAES, Hitek, iWave Global, Mercury Systems, & Spectrum Controls.   We are hosting customer meetings at the event, contact your local Altera    salesperson to schedule a slot.  

The computing world is hitting a wall. As AI models grow to trillions of parameters, as in-line databases scale to massive sizes, and as high-performance computing (HPC) workloads push bandwidth and memory to their limits, the need for more efficient data movement has never been greater. Traditional approaches to scaling bandwidth and capacity can’t keep pace without unsustainable cost expenditures on power usage and infrastructure build-out. Compression offers a practical and elegant solution to this challenge. By reducing the size of data that moves across interconnects, we can stretch bandwidth, improve memory efficiency, and lower system power—all without requiring a fundamental re-architecture. The Open Compute Project (OCP) has recently recognized this reality, highlighting compression as a key enabler for modern workloads. The combination of ZeroPoint Technologies (an Altera Partner), advanced compression IP, and Altera’s CXL Type 3 IP and FPGAs results in a 2–3x increase in bandwidth, giving the industry a proven path to meet the growing demand head-on. The Problem: Data Bottlenecks in Today’s Workloads AI and LLMs Large language models are exploding in size—parameters have grown from millions to billions, and now to trillions, in just a few short years. Training and inference of these models are fundamentally constrained by memory bandwidth and capacity. Without compression, these models would require even larger amounts of data movement, which increases latency, power consumption, and cost. In-line Databases Databases are increasingly run in-line with applications, from analytics pipelines to transaction processing. These in-line databases demand high throughput and low-latency access to massive datasets. Without compression, systems are forced to overprovision bandwidth and memory resources, dramatically increasing the total cost of ownership (TCO). High-Performance Computing (HPC) From climate modeling to genomics, HPC workloads require immense amounts of parallel data movement. Without compression, HPC centers must continue scaling raw interconnect bandwidth, which is unsustainable in terms of energy and cost at exascale levels. CXL Expansion (CXL Device Type 3) CXL (Compute Express Link) has emerged as the industry-standard protocol for memory pooling and expansion. Yet, as more systems adopt CXL for disaggregated memory, the sheer volume of data moving across CXL links risks overwhelming interconnect bandwidth. Without compression, the benefits of CXL expansion hit a hard ceiling. Demo Video: ZeroPoint demonstrates 2–3x increased bandwidth using its CXL compressed memory tier solution at the Future of Memory and Storage (FMS) 2025 CXL Acceleration (CXL Device Type 2) Beyond memory expansion, CXL enables accelerators to share memory seamlessly with CPUs. But in accelerator-heavy environments, data transfer volumes explode. Lack of compression makes accelerator scaling inefficient, power-hungry, and cost-prohibitive. Contact Altera to see the demo video: 2x–6x higher QPS running a VectorDB workload using a CXL 2.0 interface. Without compression, every one of these workloads faces a bottleneck that would be extremely difficult to solve with hardware scaling alone. OCP Introduces Compression into its Specification The Open Compute Project (OCP) organization recently underscored the importance of compression by including it in its specifications. This is a landmark shift: compression is no longer viewed as optional but included as a supported feature for next-generation compute infrastructure. James Kelly, VP Market Intelligence and Innovation at the OCP Foundation, said: “Within the OCP Community, our Composable Memory Systems Project, leveraging CXL and compression technologies, is driving the development of interoperable, scalable memory architectures that empower AI workloads with unprecedented efficiency and flexibility. By enabling disaggregated memory resources to be pooled and allocated across heterogeneous systems, we’re directly supporting OCP’s Open System for AI strategic initiative, fostering open specifications and standards that accelerate innovation and accessibility in AI infrastructure.” Klas Moreau, CEO of ZeroPoint Technologies, added: “What excites us about working with Altera’s CXL Type 3 IP is not just its performance, but its flexibility. Unlike other FPGA providers, Altera’s CXL solution gives us the low-latency, high-bandwidth fabric we need to showcase the full potential of our compression IP. Together, we’re able to deliver measurable gains—up to a 2–3x effective bandwidth increase—without changing the underlying hardware footprint. That’s a game-changer for customers scaling AI, HPC, and database workloads.” The Solution: ZeroPoint Compression IP + Altera CXL Type 3 IP and FPGA-based Boards ZeroPoint Compression Technology ZeroPoint brings a powerful, low-latency, hardware-efficient compression engine designed specifically for memory and interconnect applications. Unlike general-purpose compression algorithms, ZeroPoint’s IP is optimized for inline operation at wire speed, ensuring data is compressed and decompressed seamlessly without introducing overhead. Key benefits include: High compression ratios across AI, HPC, and database workloads Ultra-low latency to avoid bottlenecks on memory paths Energy savings by reducing data movement requirements Proven scalability across CXL and memory expansion use cases Altera CXL Type 3 IP Altera’s CXL Type 3 IP provides the foundation for memory expansion and pooling. It enables compute nodes to access disaggregated memory resources efficiently and securely. By integrating ZeroPoint’s compression IP, Altera’s solution extends even further—allowing CXL links to move more effective bandwidth, reduce congestion, and scale system capacity without increasing physical resources. There is a wide variety of CXL-capable FPGA-based boards available from Altera or partners. Together: Meeting the Market Need When combined, ZeroPoint’s compression IP and Altera’s CXL Type 3 IP address the OCP-driven specification requirements and solve the core problem facing data-intensive applications, ranging from AI to databases: moving massive amounts of data efficiently. Benefits to customers include: More bandwidth without more lanes: Compression effectively multiplies CXL throughput. Boost performance, cut costs: Unleash untapped performance in your current infrastructure with minimal new investment. Future-proof compliance: Alignment with OCP specifications ensures long-term viability. This combination delivers not just a technology improvement, but a market-ready solution that meets both current and emerging requirements. Conclusion The computing industry is shifting to adjust to new demands. AI, HPC, databases, and disaggregated systems are demanding exponential growth in bandwidth and memory efficiency—growth that hardware scaling alone cannot deliver. One answer is compression. OCP’s inclusion of compression in its specifications validates this direction and creates a mandate for solutions that integrate compression seamlessly with interconnect technologies like CXL. Through the combination of ZeroPoint’s cutting-edge compression IP and Altera’s CXL Type 3 IP, customers can now confidently deploy systems that are not only faster and more efficient but also aligned with the industry’s forward-looking standards. The future of computing depends on smarter ways to move and manage data. Compression + CXL is that smarter way—and with ZeroPoint and Altera, the future is already here. Learn More Presentations or videos are available for on-demand viewing or download: FMS 2025 session (video | slides) OCP 2025 session (video | slides) Next Steps Learn more about Altera’s CXL IP core. For technical details, partnership discussions, or general inquiries, please contact: nilesh.shah@zptcorp.com — CXL compression solutions phillip.swart@altera.com — FPGA-based CXL IP and boards