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Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC
Hi, I am working with a Cyclone-V 5CSXFC6C6U2317 FPGA and using the MegaWizard's IP FIFO SCFIFO in it. The SCFIFO is for custom logic and is outside of the HPS/ARM/Nios sub-system. My Quartus is 23.1 Prime Standard Edition. From the "FIFO IP User Guide for Quartus® Prime Design Suite: 25.1.1" it looks like I can enable (hard, memory-build in) ECC protection only for Arria 10 devices with M20K memory. My Cyclone-V has M10K memory (and Auto and MLAB memory) . It should be possible for me to add a soft-ECC module in the fabric, either inside the SCFIFO wrapper (from MegaWizard), or outside the SCFIFO wrapper. Has anyone done (or seen in Altera's Github) such a soft-ECC module ( for example using a Hamming SEC-DED (24,16) code or similar) ?Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory
Hi, I am working with a Cyclone-V 5CSXFC6C6U2317 FPGA and using the MegaWizard's IP FIFO SCFIFO in it. The SCFIFO is for custom logic and is outside of the HPS/ARM/Nios sub-system. My Quartus is 23.1 Prime Standard Edition. From the "FIFO IP User Guide for Quartus® Prime Design Suite: 25.1.1" it looks like I can enable (hard, memory-build in) ECC protection only for Arria 10 devices with M20K memory. My Cyclone-V has M10K memory (and Auto and MLAB memory) . It should be possible for me to add a soft-ECC module in the fabric, either inside the SCFIFO wrapper (from MegaWizard), or outside the SCFIFO wrapper. Has anyone done (or seen in Altera's Github) such a soft-ECC module ( for example using a Hamming SEC-DED (24,16) code or similar) ?
Is Quartus Prime Pro 22.4 Compatible with Stratix 10 NX Series Device?
Hello everyone, I'm wondering if Quartus 22.4 supports the Stratix 10 NX series devices. I've installed Quartus 22.4 along with the Stratix 10 device library, but I can't seem to find any options related to this chip. Has anyone else encountered this issue or knows if this version supports the Stratix 10 NX series? Any help or guidance would be greatly appreciated! Thank you!Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted
Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful. According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says: "Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate." But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file: set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1" which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build: +-----------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; i_reconfig_clk ; Missing I/O standard ; ; i_rx_serial_data_n[0] ; Missing I/O standard ; ; i_rx_serial_data[0] ; Missing I/O standard ; ; i_clk_ref_p ; Missing I/O standard ; ; o_tx_serial_data[0] ; Missing location assignment ; ; o_tx_serial_data_n[0] ; Missing location assignment ; ; qsfp_lowpwr ; Missing location assignment ; ; qsfp_rstn ; Missing location assignment ; ; i_reconfig_clk ; Missing location assignment ; ; i_rx_serial_data_n[0] ; Missing location assignment ; ; i_rx_serial_data[0] ; Missing location assignment ; ; i_clk_ref_p ; Missing location assignment ; ; i_refclk2pll_p ; Missing location assignment ; +-----------------------+-----------------------------------------------------------------------------------------------+ Whenever I try to assign these myself I get errors like Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq. or this or other type of layout or clocking type constraint errors: Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]". It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are. Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit? Cheers!
Agilex® 7 FPGAs Demonstrate Linear Pluggable Optics (LPO) for AI and Cloud Infrastructure
3 MIN READ Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.The FPGA Advantage for Secure 5G Infrastructure – A Dell Perspective
2 MIN READ Dell’s Open RAN radio platforms use Altera Agilex® 7 SoC FPGAs to deliver secure, adaptable 5G infrastructure. The FPGA architecture enables hardware-rooted security and post-deployment updates, allowing radio units to evolve with new protocols and threats while maintaining trusted edge infrastructure.Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?
Cyclone5 SoC: U-Boot not detecting USB-HUB
Hello there, I'm working on a design on top of a Chameleon96 Board (CycloneV based), featuring a USB OTG Chip USB3300, and connected to it an USB 2513B Hub. My issue is that neither U-Boot or Linux are able to detect the USB Hub connected to the USB3300. This used to work with older U-Boot versions and are still working on my board, but I was not able to reproduce such behavior with up-to-date versions (cloned from https://github.com/altera-fpga/u-boot-socfpga and https://github.com/altera-fpga/linux-socfpga). The Chameleon96 has two GPIO pins to control the reset of the mentioned USB chips, with a fixed configuration on the USB 2513B (the I2C interface is not exposed). With my version (U-Boot 2025.07-gd4f268660a70-dirty and Linux 6.12.33-g3234b1ed8956), the USB OTG is detected and the hub registered with logs like the following: [ 0.883275] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 0.890619] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 0.898034] dwc2 ffb40000.usb: Configuration mismatch. dr_mode forced to host [ 0.905721] dwc2 ffb40000.usb: DWC OTG Controller [ 0.910454] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 0.917571] dwc2 ffb40000.usb: irq 32, io mem 0xffb40000 [ 0.923324] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, b2 [ 0.931588] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 0.938800] usb usb1: Product: DWC OTG Controller [ 0.943509] usb usb1: Manufacturer: Linux 6.12.33-g3234b1ed8956 dwc2_hsotg [ 0.950362] usb usb1: SerialNumber: ffb40000.usb [ 0.955682] hub 1-0:1.0: USB hub found [ 0.959499] hub 1-0:1.0: 1 port detected but the connected USB hub never shows up. Similarly 'usb start' from the U-Boot prompt just shows something called U-Boot Root Hub: => usb start starting USB... USB DWC2 Bus usb@ffb40000: 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) U-Boot Root Hub Older u-boot versions (and linux) are able to detect the USB hub after 'usb start'. In this case, the root hub is named DWT OTC RootHub, and I don't know if this is just a change of naming somewhere or something wrong is also happening while detecting the USB3300 Hub: SOCFPGA_CHAMELEON96 # usb start (Re)start USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_CHAMELEON96 # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | DWC OTG RootHub | +-2 Hub (480 Mb/s, 2mA) the linux kernel (4.1.33-ltsi-altera) is also able to detect the USB Hub as can be seen in these logs: [ 0.913203] ffb40000.usb supply vusb_d not found, using dummy regulator [ 0.919864] ffb40000.usb supply vusb_a not found, using dummy regulator [ 0.957196] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRM [ 1.817295] dwc2 ffb40000.usb: DWC OTG Controller [ 1.822011] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.829076] dwc2 ffb40000.usb: irq 44, io mem 0x00000000 [ 1.834617] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 [ 1.841394] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber1 [ 1.848596] usb usb1: Product: DWC OTG Controller [ 1.853282] usb usb1: Manufacturer: Linux 4.1.33-ltsi-altera-svn260 dwc2_hsog [ 1.860481] usb usb1: SerialNumber: ffb40000.usb [ 1.865670] hub 1-0:1.0: USB hub found [ 1.869457] hub 1-0:1.0: 1 port detected ... [ 2.367190] usb 1-1: new high-speed USB device number 2 using dwc2 [ 2.577385] usb 1-1: New USB device found, idVendor=0424, idProduct=2513 [ 2.584069] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.591939] hub 1-1:1.0: USB hub found [ 2.595782] hub 1-1:1.0: 3 ports detected I think I've ported all the needed configuration to the u-boot sources (basically resetting the USB hub using the attached GPIOs, and I also tried the reset sequence manually from U-Boot with the gpio command) and I'm not able to figure out how to find where the issue might be. I've forked u-boot sources here: https://github.com/teiram/u-boot-socfpga/, using the socfpga_chameleon96_defconfig configuration. Could you please support me in order to troubleshoot what the issue might be? I tried to backport my changes to some different branches on u-boot-socpfga but got the same results or even worse (no boot at all). I also have sources for a working U-Boot but they are quite old and the configuration changed sensibly since. I think all the needed options are set. Cheers, Manuel
QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer
When I execute the Signal Tap Logic Analyzer function on QuartusPro 25.3, after finding and viewing the signal I wanted , then saving it, the crash was happend. I also saved the log by clicking "preview report". the part of log message as below. *** Fatal Error: Segment Violation: faulting address=(nil), PC=0x7f9af7f4acff : 0x7f9af7f4acff: sld_sdr!SDR_TX_SIGNAL_NODES_GEN2::get_parent_index(int, int) + 0x29 Module: quartus Stack Trace: Err Handler 0x327e1: ERR_UNWINDER_BACKTRACE::get_stack_trace(void const**, int, int, void*) + 0xed (ccl_err) Err Handler 0x8f7b0: msg_ie_get_call_stack(void*) + 0xc4 (ccl_msg) Err Handler 0x91b16: MSG_INTERNAL_ERROR::report_fatal(char const*, void*, bool) + 0x40 (ccl_msg) Err Handler 0x123c7: err_report_fatal_exception(char const*, void*, bool) + 0x63 (ccl_err) Err Handler 0x24f40: err_sigaction_handler + 0x727 (ccl_err) System 0xf630: (pthread)JTAG_UART stuck in printf
I'm trying to setup a NiosV and have printf appear over the JTAG_UART. I've used only the default settings when generating the bsp (just the generate command, no set_settings). I notice when I debug, anytime I step over a printf statement, it never returns (also, no print statements appear in the juart-terminal). However, if I just do a direct pointer access to the JTAG_UART base address, I successfully see characters printed in the juart-terminal. Looking in the bsp's summary.html, it appears that it has linked the jtag_uart. Ex: hal.stdout Value = jtag_uart_0. I also have a fair chunk of CPU block ram memory (262 KB total, only using about 16 KB right now for hello world). Any ideas what the issue here is?
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