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Do we need to manually Pin map HBM m2u Interface ports
Critical Warning (12677): No exact pin location assignment(s) for 40 pins of 72 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Getting following Critical Warning in fit.plan.rpt The un-mapped 40 pins are the following m2u interface ports exported from HBM controller instances ///// HBM m2u bridge signals ///// input wire hbm_b_m2u_bridge_cattrip, // hbm_b_m2u_bridge.cattrip input wire [2:0] hbm_b_m2u_bridge_temp, // .temp input wire [7:0] hbm_b_m2u_bridge_wso, // .wso output logic hbm_b_m2u_bridge_reset_n, // .reset_n output logic hbm_b_m2u_bridge_wrst_n, // .wrst_n output logic hbm_b_m2u_bridge_wrck, // .wrck output logic hbm_b_m2u_bridge_shiftwr, // .shiftwr output logic hbm_b_m2u_bridge_capturewr, // .capturewr output logic hbm_b_m2u_bridge_updatewr, // .updatewr output logic hbm_b_m2u_bridge_selectwir, // .selectwir output logic hbm_b_m2u_bridge_wsi, // .wsi input wire hbm_t_m2u_bridge_cattrip, // hbm_t_m2u_bridge.cattrip input wire [2:0] hbm_t_m2u_bridge_temp, // .temp input wire [7:0] hbm_t_m2u_bridge_wso, // .wso output logic hbm_t_m2u_bridge_reset_n, // .reset_n output logic hbm_t_m2u_bridge_wrst_n, // .wrst_n output logic hbm_t_m2u_bridge_wrck, // .wrck output logic hbm_t_m2u_bridge_shiftwr, // .shiftwr output logic hbm_t_m2u_bridge_capturewr, // .capturewr output logic hbm_t_m2u_bridge_updatewr, // .updatewr output logic hbm_t_m2u_bridge_selectwir, // .selectwir output logic hbm_t_m2u_bridge_wsi // .wsi Do we really need to map these ports to FPGA IO Pins ? How can I fix this Critical Warning? Regards Siva KonaSolved2.4KViews0likes5CommentsMAX10 Dual Configuration
I am using the MAX10 Dual Configuration. The device settings in the Quartus are shown in the image below. The settings for the generation of the .pof file and the .rpd files are shown below: The CONFIG_SEL file is set by a jumper via a 10K resistors either high or low. I can update the flash memory, but it appears that both CFM0 and CFM1 are programmed with the same image. Also, when I use JTAG to program CFM0 and CFM1 with two different images, it seems that the programming of CFM1 overwrites the CFM0 image. What could be wrong?11Views0likes2CommentsAgilex 5: Cascading DSPs in tensor-mode doesn't work
Hi, In my design for Agilex 5 I have two DSPs, configured in tensor fixed-point mode with side feed control, cascaded together. I expect the summation of the dot products in the second (last-in-chain) DSP to include the result from the previous (first-in-chain) DSP. This works in simulation using the simulation models generated by the IP generator (which are based on tenm_dsp_prime primitives), and the Technology Map Viewer shows that the cascade connection is present in the placed-and-routed design. The issue is that it doesn't work once programmed on the FPGA. The summation of the dot products in both DSPs works in each of them separately, but the second (last-in-chain) DSP doesn't include the cascade output from the first DSP. This has been confirmed with SignalTap, i.e., I can see that the dot-product summation outputs (FXP32) correctly reflect the result of the dot-product summation for their respective inputs, but the second DSP doesn't include the cascaded result. The cascaded path cannot be tapped. Both DSPs were generated with IP generator with the following settings: * DSP 1 (first-in-chain): cascade_in = disabled (ZERO_TENSOR_CHAIN_OUTPUT set in .ip file), cascade_out = enabled * DSP 2 (last-in-chain) : cascade_in = enabled (TENSOR_CHAIN_OUTPUT set in .ip file), cascade_out = disabled My suspicion is that the input multiplexer in the last-in-chain DSP is somehow not set correctly to include the cascaded path, despite correct settings in the .ip file. Here are the details of my setup: * dev kit: Agilex 5E065B Premium DK * tools : Quartus Prime 25.3.1 build 100 12/19/2025 SC Pro Edition + 1.02 patch * os : Ubuntu 24.04.3 LTS I'd like to confirm whether it's a known issue with the cascade multiplexer configuration or whether some additional constraints are needed to make sure the cascaded path is correctly enabled. Can you provide a resolution to this issue? Thanks, KJ30Views0likes3CommentsNiosV and juart-terminal
I had a project which works fine under niosII. I upgrade all the project with niosv and all seems fine except printing values in juart-terminal. Here is the main code : #include <stdio.h> #include "system.h" #include "altera_avalon_pio_regs.h" #include <altera_avalon_i2c.h> #include <unistd.h> #include <string.h> int main() { //* ALT_AVALON_I2C_DEV_t *i2c_dev; //pointer to instance structure alt_u8 txbuffer[20]; alt_u8 rxbuffer[20]; float co2Concentration = 0; float temperature = 0; float humidity = 0; alt_u32 co2U32 = 0; alt_u32 tempU32 = 0; alt_u32 humU32 = 0; ALT_AVALON_I2C_STATUS_CODE status; i2c_dev = alt_avalon_i2c_open("/dev/i2c"); //Ouverture du périphérique i2c et récupération d'un pointeur if (NULL==i2c_dev) { printf("Error: Cannot find /dev/i2c\n"); return 1; } //set the address of the device using alt_avalon_i2c_master_target_set(i2c_dev,0x61); //Définition de l'adresse du composant adressé 0x61 pour le SCD30 txbuffer[0]=0x00; txbuffer[1]=0x10; txbuffer[2]=0x00; txbuffer[3]=0x00; txbuffer[4]=0x81; //Remplissage du buffer pour configurer le SDC30 en Continous measurement status=alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 5,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL while(1) { txbuffer[0]=0x02; txbuffer[1]=0x02; //Remplissage du buffer pour déterminer si les données sont prêtes alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant rxbuffer[1]=0x00; usleep(3000); // Il faut attendre au moins 3ms avant de demander la réponse alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 3,ALT_AVALON_I2C_NO_INTERRUPTS); //Récupération de la réponse du composant si rxbuffer[1]==0x01 alors les données sont prêtes if(rxbuffer[1]==0x01) { txbuffer[0]=0x03; txbuffer[1]=0x00; //Remplissage du buffer pour la lecture des données alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2, ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer de lecture et récupération des données usleep(3000); //Wait 3ms before data available alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 18,ALT_AVALON_I2C_NO_INTERRUPTS); //Read datas co2U32 = (alt_u32)((((alt_u32)rxbuffer[0]) << 24) | (((alt_u32)rxbuffer[1]) << 16) | (((alt_u32)rxbuffer[3]) << 8) | ((alt_u32)rxbuffer[4])); tempU32 = (alt_u32)((((alt_u32)rxbuffer[6]) << 24) | (((alt_u32)rxbuffer[7]) << 16) | (((alt_u32)rxbuffer[9]) << 8) | ((alt_u32)rxbuffer[10])); humU32 = (alt_u32)((((alt_u32)rxbuffer[12]) << 24) | (((alt_u32)rxbuffer[13]) << 16) | (((alt_u32)rxbuffer[15]) << 8) | ((alt_u32)rxbuffer[16])); memcpy(&co2Concentration, &co2U32, sizeof(co2Concentration)); memcpy(&temperature, &tempU32, sizeof(temperature)); memcpy(&humidity, &humU32, sizeof(humidity)); } printf("---------------------------------------------------------\n"); printf("SCD30\n"); printf("Concentration de CO2 : %f ppm\n",co2Concentration); printf("Température : %.1f °C\n",temperature); printf("Humidité relative : %.1f %% \n",humidity); usleep(500000); } } I put a breakpoint just before the printf and the values are good : but when i print the values in the juart-terminal : I can't figure out why the printf does not work as i expect. Someone could help me to understand this problem ? Thanks Eric35Views0likes5CommentsNiosV µC/OS-II
Hello, I try to design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I understand that uC-TCP-IP library needs µC/OS-II but this option is not available in bsp editor GUI (only hal and freertos are available). When I try to execute the command from the project README, I have the following error : $ niosv-bsp -c sw/bsp/settings.bsp -qpf=hw/top.qpf -qsys=hw/sys.qsys --type=ucosii --cmd="enable_sw_package uc_tcp_ip" ... 2026.03.11.18:36:31 Warning: Environment variable SOPC_KIT_NIOS2 not set 2026.03.11.18:36:38 Info: Searching for BSP components with category: os_software_element 2026.03.11.18:36:41 Error: BSP type "ucosii" is not valid. Valid types are: * freertos * hal I'm using Quartus Version 23.4.0 Build 79 11/22/2023 Patches 0.70 SC Pro Edition Thank you for your help.89Views0likes6CommentsAgilex 5 RSU, application image addition fails
Dear all, We are trying, unsuccessfully, to add new application images in a Agilex5 based project . We re using am AXE5000 board with an Agilex5 A5EC008BM16AE6S (M16A) model and a 256 Mbit QSPI config Flash memory. We are working with Quartus Prime Pro 25.1.0 version. Following the example here our programming file generator looks like this Below is shown the content of our .map file: BLOCK START ADDRESS END ADDRESS BOOT_INFO 0x00000000 0x0020FFFF FACTORY_IMAGE 0x00210000 0x00357FFF (0x00316FFF) SPT0 0x00358000 0x0035FFFF SPT1 0x00360000 0x00367FFF CPB0 0x00368000 0x0036FFFF CPB1 0x00370000 0x00377FFF P1 0x00378000 0x0048BFFF Configuration device: A5EC008BM16A Configuration mode: Active Serial x4 Notes: - Data checksum for this conversion is 0xE6BCBC7E - All the addresses in this file are byte addresses In this scenario, using system console and the script rsu1.tcl provided , we have been able to switch between Aplication and Factory images flawlessly using "rsu_image_update" function. Then following the mentioned excample, we tryied to add a new application image qspi_open qspi_set_cs program_flash ./output_files/RemoteImage_jic.rpd 0x0048C000 1024 Once finished, we can check how the memory possitions have been written changing from all 0xFFFFFFFF to different values, using : qspi_read 0x0048C000 512 Then, we check the configuration pointer blocks: qspi_read [expr { 0x00368000 + 0x20}] 1 qspi_read [expr { 0x00368000 + 0x28 }] 1 qspi_read [expr { 0x00370000 + 0x20}] 1 qspi_read [expr { 0x00370000 + 0x28}] 1 Here we can see in both pointers how the current application image pointer entry has the value 0x00378000, while the next image pointer entry has all ones 0xFFFFFFFF. Then we update the aplication pointers with: qspi_write_one_word [expr { 0x00368000 + 0x28}] 0x0048C000 qspi_write_one_word [expr { 0x00370000 + 0x28}] 0x0048C000 Using "qspi_read" again we see how the pointer entries which before were all ones 0xFFFFFFFF, now contains the new address 0x0048C000. Then we close the qspi access with "qspi_close". Now, if we restart the system we see how the application image loaded is the one which was originally set on address 0x00378000. Running "rsu_status", we see how the added image failed The failing code returned is not listed in Error Code Responses Could you please help us with this topic? Thanks in advance13Views0likes0CommentsWhy does the maximum observed channel-to-channel skew exceed 2 UI + 125 ps in an E-Tile transceiver under NRZ mode, even when TX PMA bonding is enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may observe channel-to-channel skew exceeds 2 UI + 125 ps in E-Tile transceivers under NRZ mode even when TX PMA bonding is enabled. Resolution There is no workaround currently, and there is no plan to fix this problem.Country of Origin Request
Dear Team, Greetings!!! Can you please help to provide country of Origin info for below listed ALTERA parts. Part no Country of Origin PL-USB-BLASTER-RCN EPCQ128ASI16N EP4CGX30CF19C7N EP2C35F484C7N EP4CE22E22A7N EP4CE22E22C6N EP4CE22E22C7N EP4CE22E22I7N EP4CGX75CF23C8N 5M1270ZT144C5N 5M160ZM100C5N 5M240ZM100C5N 10M16SAU169C8G 10M25DCF484C7G 10M50DAF256C7G 10M50DCF484C7G EP3C40F484I7N 5CEBA5F23C7N 5CEBA5F23C8N 5CGXFC7C7F23C8N 5CSEMA5F31C8N DK-DEV-10M50-A EPCQ128SI16N EP1C20F400C6 EN5322QI EP2S30F672C5N DK-DEV-5CGTD9N4Views0likes0CommentsRequest for PLP / Lifecycle Information – Cyclone III FPGA
Dear Team, Greetings!!! According to Intel’s PLP, the legacy FPGA family Cyclone III was supported through 2040. Can you please confirm if we can expect PLP commitment information from Altera similar to what was previously provided by Intel? What is the expected End-of-Life (EOL) timeline for the Cyclone III FPGA product family? Example Part: EP3C80U484I7N Please advise.1View0likes0CommentsCYCLONE IVE ODDR delay mismatch
Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec. I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses. I'm attaching the project, hoping some experts can help me. The ddr registers are correctly instantiated, but in the timing analysis, the bit(3) coming out of the fpga is delayed compared to all the others: TIMING ON BUS_A: TIMING ON BUS_B: REGULAR DELAY: BIG DELAY: The only difference I see is that the "slow" pins are both also Vrefs (pin 105 and pin 80): Could this be the reason? regards, LUCA.Solved96Views0likes14Comments
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Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
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In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
16 days ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
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Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
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Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
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