Recent Content
Agilex 5 Premium Dev Kit Ethernet Performance
Hello! We built the golden sample image following the HPS GSRD User Guide with additional packages to profile/evaluate the board and experience performance problems when sending data over ethernet. The test setup is a host connected to the dev kit and sending data to test the throughput. First, we used iperf3 with zero copy flag, which caps at about 940 Mbit/s with almost no variation. Without zero copy, iperf3 caps at about ~880 Mbit/s with some variation down to 629 Mbit/s, see attachment 1.png. With our custom application that also does some additional work, we’d expect about 430-440 Mbit/s, but cap at about 300 Mbit/s, with lots of time spent in kernel again, see attachment 2.png. From the first investigation, we suspect the driver can’t keep up with the generated data and can’t send it fast enough to the host. We are wondering whether we can adjust something in the kernel (driver) or in the image so that we can improve the throughput with heavy workloads. Kind regards!18Views2likes0CommentsIssues with downloading
Im currently trying to download intel Quartus version 24.1 (recommended via the university), however im getting an error which ive added in the attachment below. I am on my home WiFi which is a private network and my laptop has no firewall or antivirus apart from windows defender active. Ive had this issue on multiple different internet connections and im wondering if anyone has any advice on how i can fix it.3Views0likes0CommentsError Modelsim-Altera for integer type ports in adder
I searched the forums and found that others were experiencing the same problem, but it seems they hadn't found a solution. I tried writing a similar program a long time ago; it worked fine in Quartus 13, but everything started having problems in Quartus 24. I don't know how to fix it. Please help me. https://community.altera.com/discussions/quartus-prime/error-modelsim-altera-for-integer-type-ports/333570?utm_source=chatgpt.com LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY ex1 IS PORT ( A, B : IN integer range 0 to 15; Y : OUT integer range 0 to 31); END ex1; ARCHITECTURE Behavior OF ex1 IS SIGNAL Z: integer range 0 to 31; BEGIN Z <= A+B; Y <= Z WHEN (z<10) ELSE Z+6; END Behavior; this is my code , this is my error information: Determining the location of the ModelSim executable... Using: C:/intelFPGA/20.1/modelsim_ase/win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source="C:/sample/adder/Waveform.vwf" --testbench_file="C:/sample/adder/simulation/qsim/Waveform.vwf.vht" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition Info: Copyright (C) 2025 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Apr 6 01:08:46 2026 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source=C:/sample/adder/Waveform.vwf --testbench_file=C:/sample/adder/simulation/qsim/Waveform.vwf.vht Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/sample/adder/simulation/qsim/" adder -c adder Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition Info: Copyright (C) 2025 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Apr 6 01:08:47 2026 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/sample/adder/simulation/qsim/ adder -c adder Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file adder.vho in folder "C:/sample/adder/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4737 megabytes Info: Processing ended: Mon Apr 6 01:08:48 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 Completed successfully. **** Generating the ModelSim .do script **** C:/sample/adder/simulation/qsim/adder.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do adder.do Reading pref.tcl # 2020.1 # do adder.do # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 01:08:48 on Apr 06,2026 # vcom -work work adder.vho # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package altera_lnsim_components # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package cyclonev_atom_pack # -- Loading package cyclonev_components # -- Loading package std_logic_arith # -- Compiling entity adder # -- Compiling architecture structure of adder # End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 01:08:48 on Apr 06,2026 # vcom -work work Waveform.vwf.vht # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity adder_vhd_vec_tst # -- Compiling architecture adder_arch of adder_vhd_vec_tst # End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.adder_vhd_vec_tst # Start time: 01:08:48 on Apr 06,2026 # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading work.adder_vhd_vec_tst(adder_arch) # Loading altera_lnsim.altera_lnsim_components # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading cyclonev.cyclonev_atom_pack(body) # Loading cyclonev.cyclonev_components # Loading ieee.std_logic_arith(body) # Loading work.adder(structure) # ** Fatal: (vsim-3807) Types do not match between component and entity for port "A". # Time: 0 ps Iteration: 0 Instance: /adder_vhd_vec_tst/i1 File: adder.vho Line: 40 # FATAL ERROR while loading design # Error loading design Error loading design # End time: 01:08:49 on Apr 06,2026, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.4Views0likes1CommentHow can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?
I am an engineer in Terasic, I am writting a tutorial for Agilex 5. I use Quartus Pro 25.1, there is a sopc-create-header-files in \quartus\sopc_builder\bin path, I want to generate a header file in Windows system.however, I couldn't use it in Win10 system. I tried it in Nios V command Shell: even I used Windows WSL: or in Windows PowerShell: Thanks for your advice. DoreenNiosV µC/OS-II TCP-IP debug
Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devkit, so I compiled it for two different Arria10 targets. For both targets, I get the error: [network_init] Failed to NetIF_Start(): (2010). TSE link seems to be OK. Since I'm not experienced with Nios, I'm looking for help to debug it. Thanks190Views0likes12CommentsMIPI CSI IP using M20K ram for 128 bits
I'm looking at the design assistant warnings for my project. And I see some weird usage by the mipi csi 2 core (Agilex 5 device, intel_mipi_csi2 v3.0.0). I'm greedy about my ram blocks, and I do not think it is reasonable for an IP core to use this for deskew. It's a problem because we use multiple mipi streams.. so it seems like a huge waste of M20Ks. Why arent they using MLABs? Example location: <my_system>|intel_mipi_csi2_0|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[2].gen_per_byte[1].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM <my_system>|intel_mipi_csi2_1|intel_mipi_csi2_0|mipi_rx_protocol_inst|mipi_rx_ppi_inst|gen_per_lane[0].gen_per_byte[0].deskew_dcfifo_inst|auto_generated|fifo_altera_syncram|altera_syncram_impl5|ALTERA_SYNCRAM Any way to fix this? or a variant IP that fixes it? Thank you. Regards.2Views0likes0CommentsF-tile 10GBASE-R firecode FEC IP (Agilex 7)
Hi! We require to support 10GBASE-R clause 74 (firecode) FEC + PCS. This option isn't available in the Agile 7 F-Tile hard FEC IP. It is available for 25G rates, but we need it specifically for 10G. Our application doesn't require a MAC, in other rates we are to use PCS/MII mode It seems the only way forward is a soft firecode FEC + PCS, which would could connect to our FGT in PMA direct mode. Is this correct, and does altera provide an equivalent soft IP in order to support this configuration?6Views0likes0CommentsI want to use a lot of 10GBase-R PHY on an Agilex 5 E
I want to implement a lot of 10GBase-R PHY with XGMII Interface in an Agilex 5 E-Series. I need NOT to use 10G Ethernet MAC. I found some IP Parameters in GTS PMA and FEC Direct PHY IP. Is it correct to my use-case ? Thanks.7Views0likes0Comments
Featured Places
Community Resources
Check out the support articles on personalizing your community account, contributing to the community, and providing community feedback directly to the admin team!Tags
- troubleshooting10,338 Topics
- fpga dev tools quartus® prime software pro4,227 Topics
- FPGA Dev Tools Quartus II Software3,160 Topics
- stratix® 10 fpgas and socs1,533 Topics
- agilex™ 7 fpgas and socs1,425 Topics
- arria® 10 fpgas and socs1,351 Topics
- stratix® v fpgas1,314 Topics
- arria® v fpgas and socs1,226 Topics
- cyclone® v fpgas and socs1,053 Topics
- Configuration972 Topics
Recent Blogs
Quartus Prime Pro 26.1 improves FPGA development with faster performance, a new drag-and-drop design tool (Visual Designer Studio), better power/thermal analysis, and expanded IP support and debugging—making design workflows simpler and more efficient.
19 hours ago0likes
2 MIN READ
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
12 days ago1like
In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
21 days ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
21 days ago0likes
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
22 days ago0likes