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Meet QuartusIQ Quartus® Prime (Pro Edition, 26.3) introduces the QuartusIQ AI Expert Companion, bringing FPGA expertise and project-aware AI assistance directly into your design workflow. Get guidance where you work, explore design decisions, and connect knowledge with hands-on tasks. Alongside new capabilities in system design, power analysis, and embedded development, QuartusIQ creates a more connected FPGA development experience. QuartusIQ: FPGA Expertise, Closer to Your Design QuartusIQ integrates AI assistance directly into the Quartus GUI, providing access to FPGA knowledge and project-aware guidance within your design environment. You can ask questions, explore design recommendations, and find relevant information without leaving Quartus. QuartusIQ connects to supported LLM providers using your own API key. Beyond general-purpose AI assistance, QuartusIQ combines FPGA-specific knowledge with project summaries to help make questions and recommendations more relevant to your design. Whether you're learning a new tool in Quartus, looking for documentation, or investigating approaches to design closure, this context can help you identify useful next steps. QuartusIQ also supports practical programming and configuration tasks. Analyze and convert programming files, discover connected hardware, and program devices through JTAG. Supports Secure Device Manager (SDM) commands, QSPI compatibility checks, and Remote System Update (RSU) image generation, extending these capabilities to additional device-configuration tasks. For teams exploring AI-assisted development beyond the Quartus GUI, Model Context Protocol (MCP) integration makes QuartusIQ expertise accessible to external AI workflows. And there is also an extension for Visual Studio Code that lets QuartusIQ work with GitHub Copilot. MCP integration and agent capabilities are available, providing additional ways to incorporate FPGA-specific knowledge and tools into connected development environments. Together, these capabilities make QuartusIQ a companion for finding information, understanding your project, and completing tasks, with recommendations you can review and apply to your design. Visual Designer Studio: Keep the System in View Visual Designer Studio (VDS) expands Platform Designer system import to include generic components and parameterized RTL, allowing more of your existing design to be incorporated into a visual workflow. Cross-probing between VDS and other Quartus applications makes it easier to navigate between the system-level view and related design information. Clock/reset fanout simplifies logical hierarchies. Improved separation of source and generated files makes revision control easier to manage. Expanded support for Arria 10, Cyclone 10 GX, and Stratix 10 devices provide greater design flexibility. Board awareness (beta) introduces board-package creation and use within VDS, adding board-level context to the system-design environment. Power & Thermal Analyzer: Streamline Power Analysis Workflows Power analysis is most valuable when it's integrated into the design process. With Tcl scripting and example scripts, Power & Thermal Analyzer makes it easier to automate analysis workflows, maintain consistency, and reassess power consumption as designs evolve. Several usability enhancements simplify working with device resources and analysis results. Device-aware resource filtering and controls help prevent invalid actions, while improved device selection, graphical displays, and numeric alignment make the interface easier to navigate. Common power-analysis reports are now available in the Report Database, providing access to power-analysis results within a familiar reporting environment. HPS is also modeled as a resource rather than a global setting, making its treatment more consistent with other design resources. Embedded Development: Expanded Platform Support and Design Examples Quartus Prime (Pro Edition, 26.3) expands embedded development support with the following: Initial Agilex® 27 SoC Hard Processor System (HPS) enablement, including Simics support and baseline hardware and software reference designs. For Agilex 5 E-Series devices, expanded FreeRTOS support includes Cortex-A76 symmetric multiprocessing (SMP) capabilities, along with the re-release of the bare-metal library. New Agilex 5 E-Series design examples help developers explore a wider range of embedded architectures. These include heterogeneous Linux and FreeRTOS operation using Bao static partitioning, cache-coherent accelerator examples for both operating systems, and Ubuntu and Docker-based Linux configurations. A new bare-metal "Hello World" example provides a simple starting point for development. Updated Nios V design examples include Triple-Speed Ethernet (TSE) designs with FreeRTOS TCP/IP and web-server functionality for Agilex 3 and Agilex 5 devices. Additional enhancements include initial Agilex 27 Nios enablement and soft-processor debug module improvements. Additional Productivity, DSP Builder Machine Learning, and Device Support Enhancements Node Finder improvements include a persistent top-level hierarchy, single-click navigation, and side-by-side search results, making it easier to explore a design while maintaining context. DSP Builder expands machine-learning capabilities with new CNN layers, expanded activation-function support, and AI Tensor DSP optimizations. Enhanced network import, quantization, and automatic sizing simplify implementation, while new demos and MATLAB/Simulink MCP-based agentic workflows support model creation, updates, and verification. Device enablement also expands for Agilex 5 E-Series and D-Series, including additional temperature-grade support for Agilex 5 D-Series devices. AI models with FPGA AI Suite FPGA AI Suite 26.3 expands the tools and capabilities available for developing and integrating AI workloads. Beta features include spatial compiler and developer APIs that enable customers to build CNN and transformer models with examples (ResNet-8, Qwen 3.5, Majika, GPT-neo), and configurable external memory interface (EMIF) connectivity. Additional updates include a new Altera Model Zoo, better integration with the Altera Video and Vision Processing, SoC/x86 profiling, and VDS examples. New production-quality design examples for Agilex 3 Memory-to-Memory designs. These additions provide more options for model exploration, data-path integration, and performance analysis. Explore Quartus Prime (Pro Edition, 26.3) From project-aware AI assistance to enhancements in system design, power analysis, embedded development, and AI workloads, Quartus Prime Pro 26.3 provides new capabilities for your FPGA projects. Visit the Quartus Prime Pro website to learn more. What's New in the Quartus® Prime (Pro Edition) Design Software Download the Quartus® Prime (Pro Edition) version 26.3 Software Learn more about QuartusIQ Read the QuartusIQ white paper Learn more about FPGA AI Suite software Agilex 3 FPGAs and SoCs overview Agilex 5 FPGAs and SoCs overview Agilex 7 FPGAs and SoCs overview

PACKET CLASSIFICATION | FPGA | NETWORKING + SECURITY Every packet decision starts with classification. Routers, firewalls, SmartNICs, security gateways, and service-edge platforms must determine which policy applies before traffic can be forwarded, blocked, inspected, redirected, or prioritized. TCAM earned its place in these systems because it provides predictable lookup behavior and native ternary matching for ACL and LPM workloads. But as policy databases grow, search keys widen, and rules change more frequently, the traditional approach of scaling specialized ternary memory creates tougher tradeoffs in capacity, power, resource utilization, and system integration. Altera Stellar solutions takes a different approach. Instead of scaling packet classification by building ever-larger ternary-memory structures, Stellar turns classification into an optimized search problem that runs on configurable FPGA resources. The result is an FPGA-native path for large, dynamic packet-classification tables without giving up the policy semantics that made TCAM useful in the first place. TCAM scales through memory expansion. Stellar scales through search intelligence.  Keep the TCAM semantics. Change the scaling model. Stellar preserves the intent of ACL, LPM, and multi-field classification, but changes how those rules are represented and searched. The Stellar Software Stack organizes policies into optimized graph structures, partitions the rule database, and continuously manages those search structures as the database evolves. The hardware then executes the search using configurable FPGA search engines while rule information is stored in conventional memory resources. Depending on the configuration, Stellar can use on-chip M20K memory, eSRAM, DDR, or HBM. That gives architects more freedom to balance throughput, capacity, latency, power, and FPGA resource use around the needs of the actual system. Use dense memory where it makes sense, and intelligence where it matters A traditional TCAM combines storage and comparison circuitry inside specialized ternary-memory arrays. That architecture delivers deterministic matching, but scaling the table means scaling the specialized comparison structure as well. Stellar separates rule storage from search execution. Ternary information can be represented as value-and-mask data in conventional memory, while graph organization and software-managed optimization direct each search toward the relevant parts of the database. As tables grow from thousands of entries toward hundreds of thousands or millions, this creates a different path for scaling capacity and power. The white paper goes deeper into why this matters, including the tradeoffs between TCAM and Stellar, the role of memory hierarchy, and a set of Stellar configurations spanning different key widths, capacities, memory resources, and projected five-tuple performance. Bring classification into the programmable datapath The value is bigger than the lookup engine itself. Stellar is designed to operate inside the FPGA alongside packet parsing, telemetry, encryption, traffic management, host-interface logic, and customer packet-processing RTL. For system architects, that means classification can become part of the same programmable platform already handling the datapath. A firewall can pair large, dynamic ACL processing with the rest of its traffic pipeline. A router can combine LPM and policy enforcement with programmable networking functions. A SmartNIC can integrate flow classification with offload and customer-specific acceleration. That system-level flexibility is especially relevant for 100GE to 400GE designs where classification must scale without consuming the platform that surrounds it. Read the full whitepaper! The full Altera white paper, Altera TCAM Alternative Solutions Scale Packet Classification to Millions of Rules for Networking Equipment, explains the architecture behind Stellar and the design choices that make it different. It covers TCAM fundamentals and scaling limits, Stellar graph-based search and software partitioning, memory-hierarchy options, configuration examples, quantitative architectural comparisons, dynamic updates, and deployment use cases across networking and security. Read the white paper See how Stellar uses search intelligence, configurable FPGA resources, and a flexible memory hierarchy to create a scalable alternative for large ACL and LPM workloads.

September 28, 2026 The next generation of embedded systems will not be defined by compute alone. It will depend on how quickly, reliably, and intelligently systems can move data from the physical world into AI engines and turn insights back into action. That message came through clearly at Embedded World North America 2026, held September 22–24 at the Anaheim Convention Center. For Altera, the show provided an opportunity to highlight a growing collaboration with NVIDIA and demonstrate the role of FPGAs in high-performance edge AI architectures. Connecting sensors to AI with flexibility and determinism At the center of the story was NVIDIA Holoscan Sensor Bridge technology. The solution creates a high-bandwidth, low-latency path between real-world sensors and GPU-based AI processing, an increasingly important capability for robotics, industrial automation, intelligent video, medical systems, and other physical AI applications. FPGAs are well suited to this role because they can provide deterministic processing, flexible I/O, and protocol adaptation close to the sensor. Rather than forcing every application into the same hardware configuration, FPGA-based designs can be tailored to performance, connectivity, and latency requirements of a specific system. In the show’s keynote, NVIDIA Vice President Deepu Talla described the value of this flexibility: “You can select any of the Altera FPGAs depending on the application and pair them with any of the NVIDIA frameworks.” Altera’s post noted that Altera offers Holoscan Sensor Bridge solutions spanning 10G to 100G, where 25G and 100G offer significantly more bandwidth compared to other Holoscan ecosystem partners, helping developers scale connectivity for demanding edge workloads.         The result is a practical sensor-to-compute architecture: Altera FPGAs handle the flexible, deterministic front end, while NVIDIA platforms provide the accelerated environment for AI and robotics workloads. An ecosystem approach to accelerating development The demonstrations also underscored that successful edge AI deployments require more than individual components. Developers need reference designs, production-ready boards, and partners that help bridge the gap between evaluation and deployment. Altera’s growing Holoscan ecosystem includes more than 10 reference designs and partner boards. These building blocks can help teams reduce integration effort and move faster from proof of concept to a real-time AI product. One example was on display at Altera partner Critical Link’s booth. Critical Link was recognized as a Best in Show Award winner in the AI & Machine Learning category at the show. Visitors to the booth could see a live demonstration of a 5-camera Holoscan Sensor Bridge solution, using Critical Link’s MitySOM-A5E as the featured Agilex® 5 FPGA hardware platform. The demonstration showed how an Agilex 5 FPGA-based system can help bring sensor data into an NVIDIA-powered AI pipeline while preserving the low-latency, high-bandwidth behavior required by edge applications.               From 10G to 100G: Building the data plane for edge AI Altera’s Holoscan Sensor Bridge solutions are designed to make the sensor-to-GPU path faster and more adaptable. A recent Altera technical blog describes 10G, 25G, and 100G reference designs, including a 25G design on Agilex 5 SoC FPGAs for multi-camera sensor data flow and accelerated processing at the edge. In this architecture, the FPGA serves as the data plane: connecting to diverse sensors, aggregating streams, adapting protocols, and preprocessing data before it reaches the NVIDIA GPU. That division of labor helps reduce data-movement bottlenecks while preserving deterministic timing and giving developers room to evolve the system as sensor interfaces and AI workloads change. Altera Technical Holoscan blog for Robotics: Altera Pushes the Boundaries of Edge AI with New Holoscan Sensor Bridge Solutions | Altera Community - 355665 Watch the 25G Holoscan demo video: YouTube/Altera Why the sensor-to-compute path matters As AI moves into physical environments, system designers are balancing several competing requirements: Real-time response: Applications such as robotics and industrial inspection cannot always afford the delay of sending raw sensor data to a remote system. High-bandwidth data movement: Modern sensors generate increasingly rich data streams that must be transported without creating a bottleneck. Deterministic behavior: Safety-critical and industrial systems need predictable timing and consistent performance. Design flexibility: Product teams must support different sensors, interfaces, and deployment conditions without redesigning the entire platform. Faster development: Reference designs and ecosystem partnerships can shorten the path from concept to production. The Altera and NVIDIA approach addresses these needs by combining FPGA-based connectivity and processing with GPU-accelerated AI. It gives developers a modular foundation for building systems that can adapt as sensors, models, and application requirements evolve. Building what comes next at the edge The conversation at Embedded World North America 2026 pointed toward a broader shift in embedded design. Edge systems are becoming intelligent, connected, and increasingly autonomous, but their performance still depends on the data path that feeds them. By pairing Altera FPGAs with NVIDIA platforms and collaborating with partners such as Critical Link, developers gain more options for designing that path. The combination of flexible hardware, high-speed connectivity, and accelerated AI can help transform raw sensor input into timely decisions at the point where data is created. For teams developing the next generation of robotics, industrial automation, intelligent vision, and physical AI systems, this is the opportunity: Build a sensor-to-compute architecture that is fast enough for today’s workloads, flexible enough for tomorrow’s requirements, and ready to scale from demonstration to deployment. Learn more about Altera’s Physical AI-related Solutions: Holoscan: https://www.altera.com/fpga-solutions/sensory-interfaces Robotics: https://www.altera.com/fpga-solutions/robotics-solutions-stack Video: https://www.altera.com/fpga-solutions/video-solutions-stack

Altera has begun shipping the new Agilex® 7 M-Series R31G multi-host acceleration package, giving customers a new way to build high-bandwidth systems that connect more hosts while moving more data through the network and memory subsystem. R31G is designed for architectures where data must move quickly between the network, memory, and multiple CPUs, GPUs, or other hosts. By bringing 800G or 2x400G Ethernet together with expanded PCIe 5.0/CXL host connectivity, the package opens new possibilities for AI NICs, storage acceleration, cloud acceleration, and other high-throughput platforms. What R31G enables More network bandwidth: 800G or 2x400G Ethernet capability for high-throughput data paths. More host connectivity: Two PCIe 5.0 x16 host interfaces, or up to four independent PCIe 5.0 x8 connections, with CXL support for flexible multi-host architectures. More memory bandwidth and I/O: DDR5-6400 and LPDDR5-6400 support, up to 204.8 GBps of memory bandwidth, and 768 GPIO in a compact 56 x 45 mm package. The result is a programmable platform that can connect, accelerate, and adapt as infrastructure requirements evolve, while keeping high-speed networking, host connectivity, and memory bandwidth tightly integrated. More network bandwidth. More hosts. More memory bandwidth. One programmable platform. Learn more in the Agilex® 7 M-Series product site.  

As AI, cloud, and high-performance computing systems continue to scale, data center operators need more bandwidth within increasingly constrained power and thermal envelopes. Linear Pluggable Optics (LPO) offers an important path forward by simplifying optical modules, reducing power consumption, and lowering latency. LPO places signal-conditioning responsibilities in the host device, allowing the optical module to operate without the DSP used in traditional retimed optics. This architecture can reduce optical module power by 30% to 40%, helping data center designers increase connectivity density while simplifying cooling and thermal management. Altera Brings LPO to the FPGA Market Altera is the first FPGA provider to publicly demonstrate Linear Pluggable Optics interoperability using production FPGA devices. Continued validation with LPO modules from Amphenol and FS further demonstrates the breadth of the emerging ecosystem supported by Altera. Agilex® 7 FPGAs and SoCs bring the power and latency advantages of LPO to programmable platforms used in SmartNICs, data processing units, AI accelerators, and custom infrastructure. The initial public demonstration established that Agilex 7 devices could successfully interoperate with 400G LPO modules. The latest validation advances that milestone by confirming that the implementation meets the performance requirements expected for deployment in demanding data center environments. Validated for Real Deployment Conditions Comprehensive testing confirms that Agilex 7 F-Tile transceivers meet the electrical and link-performance requirements defined by the 100G-DR-LPO specification. The validation demonstrated: Compliance with the required transmit, receive, and link-performance criteria Successful interoperability with LPO modules from Amphenol and FS Successful LPO connectivity across distances from 1 meter to 500 meters Consistent performance across temperature and voltage conditions Measurable performance margin beyond required thresholds Testing covered demanding signal conditions, voltage variation, and temperatures ranging from minus 40 degrees Celsius to 105 degrees Celsius for electrical characterization. Functional link testing included a 1-meter LPO connection, a 100-meter active optical cable, and 500-meter LPO modules from Amphenol and FS. The results demonstrate robust, repeatable operation across multiple module suppliers and link distances, with measurable margin relative to the required performance limits. For customers, this validation provides confidence that Agilex® 7 support for LPO is ready for real-world deployment. Following the industry’s first public FPGA interoperability demonstration, the solution has now been evaluated against LPO performance requirements using modules from multiple suppliers and over link distances up to 500 meters. Together, these results demonstrate a practical foundation for deploying LPO connectivity in next-generation data center systems. More Efficient Connectivity for AI and Cloud Infrastructure The value of LPO grows as data centers deploy more high-speed optical connections. Eliminating the DSP from each optical module can reduce power across thousands of links, simplify optical module design, ease thermal pressure at the front panel, and support lower-latency data movement. Agilex 7 FPGAs add programmability to this more efficient optical architecture. Customers can combine LPO connectivity with packet processing, acceleration, security, telemetry, and evolving protocol support on a single adaptable platform. This flexibility is especially valuable for AI clusters and cloud infrastructure, where workloads, network architectures, and connectivity standards continue to evolve. Validation with multiple module vendors also gives system designers greater flexibility as the LPO supplier ecosystem continues to develop. Ready for the Next Generation of Data Centers The combination of public interoperability and comprehensive validation marks a major step for LPO in the FPGA market. Altera has demonstrated that LPO works with production Agilex 7 devices and validated that the solution meets key LPO requirements with measurable operating margin. This gives customers a proven foundation for evaluating and deploying lower-power, lower-latency optical connectivity in real data center environments. With Agilex® 7 FPGAs, LPO is ready for real-world data center deployment.