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Quartus Prime Lite 25.1 - Issue with the Verilog generate loops
Hi! I believe, this is the same issue mentioned here, or at least its sibling. Long story short, here is a snippet from the IEEE Std 1364™-2005 standard, page 185: module addergen1 (co, sum, a, b, ci); parameter SIZE = 4; output [SIZE-1:0] sum; output co; input [SIZE-1:0] a, b; input ci; wire [SIZE :0] c; wire [SIZE-1:0] t [1:3]; genvar i; assign c[0] = ci; // Hierarchical gate instance names are: // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1 // bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2 // and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3 // bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4 // or gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5 // Generated instances are connected with // multidimensional nets t[1][3:0] t[2][3:0] t[3][3:0] // (12 nets total) for(i=0; i<SIZE; i=i+1) begin:bit xor g1 ( t[1][i], a[i], b[i]); xor g2 ( sum[i], t[1][i], c[i]); and g3 ( t[2][i], a[i], b[i]); and g4 ( t[3][i], t[1][i], c[i]); or g5 ( c[i+1], t[2][i], t[3][i]); end assign co = c[SIZE]; endmodule Quartus Prime 25.1std.0 Build 1129 10/21/2025 SC Lite Edition reports the error 10170 when attempting to compile this module: Error (10170): Verilog HDL syntax error at main.v(22) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at main.v(23) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at main.v(28) near text: "end"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "addergen1" at main.v(1) due to previous errors It accepts it, though, if to embrace the generating loop into "generate/endgenerate" framing. The Verilog version in the project settings is "Verilog-2001". Changing it to "System Verilog" has no impact on the behavior. ========== For comparison, I fed this exact snippet to the Questa Altera Starter FPGA Edition-64 2025.2 and it had no problems with it. ========== So my question is: "What is the root cause of this misbehaving?". Am I understanding the standard wrong? Ot is it some peculiarity of the Quartus itself? Thanks in advance!
Timing models don't match measured delays
I am working with an Agilex 7 I-series device in Quartus Prime Pro 25.3. The device is fully supported by that QPP version and has final timing models. Since I am working with precise timing, I need to find out the propagation delay from internal clock to output on a pin with as good precision as possible. I am trying to use the Timing Analyzer (TA) to do this. The results do not match my expectations though. The TA reports paths for five operating conditions for this device: fast/vid1/100C, fast/vid1a/100C, fast/vid1a/0C, slow/vid1b/100C and slow/vid1/100C. My expectation is that one of them corresponds to the shortest propagation delay (used for hold analysis) and one the longest (used for setup analysis) and that my measured delay should therefore fall somewhere between these extremes. It does not. To test this, I have added two registers to my design, both clocked by the same clock, both toggling at every clock edge. I have instructed Quartus to preserve these and don't merge them. These two registers drive two outputs that I can measure on the board. Then I control the placement of the two registers to get different propagation delay to their pins. I start out by calibrating the setup. Placing the two registers in the same LAB close to the relevant I/O bank results in very nearly the same path delay to both pins according to the TA. As expected, I also measure a very small difference between the edges (around 100 ps). This shows that there is no significant difference between the board traces or measurement cables. Then I move one of the registers a bit, 271 LABs in the X direction to be exact. According to the TA, this design should have the following propagation delay differences between the pins for the five operating conditions: Fast vid1 100C 3.134 ns Fast vid1a 100C 3.138 ns Fast vid1a 0C 2.795 ns Slow vid1b 100C 3.028 ns Slow vid1 100C 3.011 ns However, I measure just 2.32 ns. This is lower than even the 0C model, which must be the fastest timing that is used to guarantee hold timing. How can this be?Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B
Hello, I'm working with an Agilex 5 E-Series A5ED043BB32AI4S device. On my board, I have two 32-bit LPDDR4 interfaces connected to the HSIO banks 3A and 3B. The DDR reference clock is available only on the dedicated differential CLK pins in bank 3A (K105/M105). There is no refclk in bank 3B. HPS EMIF case Using the External Memory Interfaces for HPS IP configured as 2x32 LPDDR4, Quartus instantiates two EMIFs (one in bank 3A and one in bank 3B). From the generated netlist (see attached images), it appears that the PLL associated with the EMIF in bank 3A receives the external CLK (K105/M105), the PLL reference clock is then internally forwarded/shared to the PLL associated with the EMIF in bank 3B. The design routes and fits successfully. This is the intended DDR architecture on my board and works correctly. FPGA EMIF case For debug purposes, I would like to use the LPDDR4 External Memory Interfaces (EMIF) IP together with the EMIF Debug Toolkit. Since this IP only supports up to 1x32 LPDDR4, I instantiated one LPDDR4 EMIF in bank 3A and one LPDDR4 EMIF in bank 3B. The EMIF in bank 3A works correctly when using the REFCLK in bank 3A (on K105/M105). However, I cannot get the EMIF in bank 3B to fit when its PLL reference clock is assigned to the same REFCLK source located in bank 3A. The fitter reports routing/connectivity issues. Questions 1) For the FPGA LPDDR4 External Memory Interfaces (EMIF) IP, is it mandatory that the PLL reference clock be located in the same bank as the EMIF instance? 2) Is there any supported mechanism to share or bypass the PLL reference clock from the EMIF PLL in bank 3A to the EMIF PLL in bank 3B, similar to what appears to be done automatically by the HPS EMIF 2x32 implementation? Any guidance would be appreciated. Thanks,
System Console master_read_memory fails above 7688 bytes on Agilex 5 (AXE5-Eagle)
A single master_read_memory of 7689 bytes or more never completes on an Agilex 5. It returns nothing, times out after 60 seconds, and leaves the JTAG channel closed so the next command fails too. 7688 bytes on the same master and the same address returns all 7688 values in under 0.1 second. The boundary is byte exact and repeats every time. I can reproduce this entirely with an unmodified example bitstream published by Arrow, so no design of mine is involved and there is nothing for me to send you. SETUP Board: Arrow AXE5-Eagle, device A5ED065BB32AE4SR0, IDCODE 0364F0DD Bitstream: axe5_eagle_voltage_temp.sof from https://github.com/ArrowElectronics/Agilex-5, path images/promo3/, md5 b391b9cd5226fe92fd2068ddc66f8442 That bitstream was built with Quartus Prime Pro 24.3 and reports "HPS present: FALSE", so it configures straight over JTAG with no bootloader merge and no HPS involvement. It exposes a Nios V node and a JTAG PHY master. Tools: Quartus Prime Pro 26.1.1 build 130, System Console from the same installation, Windows 10 Enterprise LTSC 21H2 Cable: Arrow USB Blaster ARA39943-TEI0004, JTAG clock pinned to 6 MHz, Altera JTAG Server running as a Windows service STEPS 1. Program the board over JTAG: quartus_pgm -c "Arrow-USB-Blaster [ARA39943-TEI0004]" -m jtag -o "p;axe5_eagle_voltage_temp.sof@1" 2. In System Console, open the JTAG PHY master and read: set m [lindex [get_service_paths master] 0] open_service master $m master_read_memory $m 0x0 7688 master_read_memory $m 0x0 7689 RESULT master_read_memory 7688 bytes -> 7688 values in 0 master_read_memory 7689 bytes -> nothing, 60.0 s, then: master_read_memory: This transaction did not complete e is giving up. After the failure the channel is closed and the next command reports "Channel closed" until the service is reopened. Recovering costs 20 to 60 seconds. WHAT I HAVE ALREADY RULED OUT Not the address. Identical behaviour reading from 0x0, 0x1000, 0x10000000 and 0x20000000, and shifting the base by 1, 2, 4 or 4092 bytes at a fixed size changes nothing. Only the requested byte count Not a timeout. Reads return in 0.0 s right up to 7688, then the very next byte fails. A timeout would show times rising as the limit approached, not an instant success becoming an outright fa Not the size of the reply. master_read_32 hands back a 45055 character answer without trouble, while master_read_memory fails while producing a 39044 character one. Not the design. The same byte boundary appears on two other unrelated bitstreams on this board, one with an HPS and one without, built with different Quartus versions. The Arrow example above is simy. master_read_32 IS NOT AFFECTED, AND HAS NO COMP On the same master and the same bitstream, master_read_32 was run at increasing sizes. Every one returned the full count, correctly, with no timeout and no channel closure: master_read_32 $m 0x0 4096 -> 4096 words, 16 kB spanned, 0.5 s master_read_32 $m 0x0 8192 -> 8192 words, 32 kB master_read_32 $m 0x0 16384 -> 16384 words, 64 kB spanned, 2.2 s master_read_32 $m 0x0 32768 -> 32768 words, 128 kB master_read_32 $m 0x0 65536 -> 65536 words, 256 kB spanned, 9.8 s That last one spans 262144 bytes, which is 34 times theead_memory cannot deliver, and it scales linearly at about0.15 ms per word with no sign of a ceiling. If the JTAG link, the Avalon bridge or the reply channel were the constraint, master_read_32 would degrade somewhere across that range. It does not. master_read_32 is therefore a usable workaround, but a slow one: master_read_memory returns 7688 bytes in under 0.05 s, roughly 150 kB/s, where master_read_32 sustains about 26 kB/s. Around 6 times slowp> QUESTIONS Is 7688 bytes an intended limit for master_read_memory on Agilex 5? If so, where is it documented, and does it vary by device family? The same tool version against Arria V hardware is rock solid and sh Whatever the limit is, could an oversized request return an error immediately instead of hanging for 60 seconds and closing the channel? The silent 60 second stall is far more expensive than a reject Happy to run any additional test on this board if neede
getting a license for Quartus standard for DE10 standard board
Hello everyone, I just bought my DE10 standard board for my graduation project. Unfortunately, my university doesn't provide a license for the Quartus standard, and I need more than 90 days to finish the project. Is there any way to get a license as a student for free? My project is about an AI accelerator, so I need the standard version; the lite one isn't enough. Thank you,getting a licnese
Hello everyone, I just bought my DE10 standard board for my graduation project. Unfortunately, my university doesn't provide a license for the Quartus standard, and I need more than 90 days to finish the project. Is there any way to get a license as a student for free? My project is about an AI accelerator, so I need the standard version; the lite one isn't enough. Thank you,
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