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EP4CE30F23C8N scratches
Hello Guys, I would like to ask a question. There is an issue with this BGA product, model number EP4CE30F23C8N: there are scratches on the bottom substrate that have penetrated the solder balls. Could this be a quality issue? I would be grateful if you could provide a reply. Many thanks!
The DC_FIFO issue of Cyclone 10 GX devices
Hello Guys, We are using 10CX220F780 and 10CX105F780 devices now. They are communicating thru XCVR. So one DC_FIFO is realized between RX received data and user logic fabric. This DC FIFO operation always has problem during the first operating. But it will be normal during the second operating. As the above image indicates, RX get data from XCVR and put them to FIFO. The write is ok, however, the reading has problem. Because the first read data is ZERO, this causes the following reads all halt. I apply one more same operation, now it's ok, as following image: As above image indicates, one data is put into FIFO, and it will be read out from this FIFO in time. But why always the first time operating is not correct after power-up or re-configuring FPGA? I did one test: FIFO's Rdreq is fix to high level. Then I got the following result: As above image indicates, the first data x"40000000" can't be written into FIFO. So I always got ZERO for the first data. Buy how this can happen? I kept detecting more deeply, as following image As above image indicates, after Wreq valid, 2 clock cycles later, Usedw will change, and 2 more clock cycles later, empty signal will be changed to low level. This is the problem. Usedw and empty signals are changed too fast. I checked normal timing, UsedW should be changed 3 clock cycles later after Wreq valid, and empty should be changed 5 clock cycles later after Wreq valid. Why can this happen? And always happen one time after power-up. Best Regard
MT25Q512 Programming Issue When Connected to Cyclone 10CX150Y
Hello friends, I am trying to program an MT25Q512 QSPI Flash memory that is connected to an Altera Cyclone 10CX150Y FPGA through QSPI CS, CLK, DQ0, DQ1, DQ2, and DQ3. The Flash memory can be programmed successfully when it is standalone. However, programming fails when it is connected to the FPGA. During programming, I hold: nCE High nCONFIG Low Could you please confirm whether this should force the FPGA QSPI pins into a high-impedance state? Please advise whether any additional FPGA pin control, board-level isolation, or specific programming sequence is required in order to program the MT25Q512 externally while it remains connected to the FPGA. Best regards
DisplayPort Sink (Quartus 18.1) – horizontal pixel offset.
We are experiencing an issue with the DisplayPort Sink IP core (Quartus Prime 18.1), where the captured video stream becomes horizontally shifted after some runtime. The system works correctly after reset, but after a variable period (typically several minutes), the image suddenly shifts horizontally by a constant number of pixels (hundreds of pixels). The image remains stable but shifted. After longer time (tens of minutes), the image may spontaneously recover, and the cycle repeats. This behavior only appears when the input signal is routed through a DisplayPort optical extender (G&D). Without the extender, the system operates correctly and indefinitely stable. This system design is constrained to Quartus 18.1 (cannot migrate easily) - We are primarily looking for a workaround or confirmation of known limitation - Not asking for redesign or migration unless necessaryWhy does the Quartus® Prime Pro Edition software version 26.1.1 report Error (25640) when an Agilex® 5 FPGA GTS regional reference clock drives 16 transceiver channels?
Description In the Quartus® Prime Pro Edition software version 26.1, an Agilex® 5 FPGA D-Series transceiver design may compile when a single GTS regional reference-clock pin drives 16 transceiver channels across four GTS quads. Starting with the Quartus Prime Pro Edition software version 26.1.1, the Fitter reports Error (25640) for the reference-clock input. The error indicates that the reference clock drives 16 transceiver channels, exceeding the allowed limit of 12 channels. The same user RTL, SDC, and pin assignments can therefore compile in version 26.1 and fail in version 26.1.1. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Quartus Prime Lite 25.1 - Issue with the Verilog generate loops
Hi! I believe, this is the same issue mentioned here, or at least its sibling. Long story short, here is a snippet from the IEEE Std 1364™-2005 standard, page 185: module addergen1 (co, sum, a, b, ci); parameter SIZE = 4; output [SIZE-1:0] sum; output co; input [SIZE-1:0] a, b; input ci; wire [SIZE :0] c; wire [SIZE-1:0] t [1:3]; genvar i; assign c[0] = ci; // Hierarchical gate instance names are: // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1 // bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2 // and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3 // bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4 // or gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5 // Generated instances are connected with // multidimensional nets t[1][3:0] t[2][3:0] t[3][3:0] // (12 nets total) for(i=0; i<SIZE; i=i+1) begin:bit xor g1 ( t[1][i], a[i], b[i]); xor g2 ( sum[i], t[1][i], c[i]); and g3 ( t[2][i], a[i], b[i]); and g4 ( t[3][i], t[1][i], c[i]); or g5 ( c[i+1], t[2][i], t[3][i]); end assign co = c[SIZE]; endmodule Quartus Prime 25.1std.0 Build 1129 10/21/2025 SC Lite Edition reports the error 10170 when attempting to compile this module: Error (10170): Verilog HDL syntax error at main.v(22) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at main.v(23) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at main.v(28) near text: "end"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "addergen1" at main.v(1) due to previous errors It accepts it, though, if to embrace the generating loop into "generate/endgenerate" framing. The Verilog version in the project settings is "Verilog-2001". Changing it to "System Verilog" has no impact on the behavior. ========== For comparison, I fed this exact snippet to the Questa Altera Starter FPGA Edition-64 2025.2 and it had no problems with it. ========== So my question is: "What is the root cause of this misbehaving?". Am I understanding the standard wrong? Ot is it some peculiarity of the Quartus itself? Thanks in advance!
Timing models don't match measured delays
I am working with an Agilex 7 I-series device in Quartus Prime Pro 25.3. The device is fully supported by that QPP version and has final timing models. Since I am working with precise timing, I need to find out the propagation delay from internal clock to output on a pin with as good precision as possible. I am trying to use the Timing Analyzer (TA) to do this. The results do not match my expectations though. The TA reports paths for five operating conditions for this device: fast/vid1/100C, fast/vid1a/100C, fast/vid1a/0C, slow/vid1b/100C and slow/vid1/100C. My expectation is that one of them corresponds to the shortest propagation delay (used for hold analysis) and one the longest (used for setup analysis) and that my measured delay should therefore fall somewhere between these extremes. It does not. To test this, I have added two registers to my design, both clocked by the same clock, both toggling at every clock edge. I have instructed Quartus to preserve these and don't merge them. These two registers drive two outputs that I can measure on the board. Then I control the placement of the two registers to get different propagation delay to their pins. I start out by calibrating the setup. Placing the two registers in the same LAB close to the relevant I/O bank results in very nearly the same path delay to both pins according to the TA. As expected, I also measure a very small difference between the edges (around 100 ps). This shows that there is no significant difference between the board traces or measurement cables. Then I move one of the registers a bit, 271 LABs in the X direction to be exact. According to the TA, this design should have the following propagation delay differences between the pins for the five operating conditions: Fast vid1 100C 3.134 ns Fast vid1a 100C 3.138 ns Fast vid1a 0C 2.795 ns Slow vid1b 100C 3.028 ns Slow vid1 100C 3.011 ns However, I measure just 2.32 ns. This is lower than even the 0C model, which must be the fastest timing that is used to guarantee hold timing. How can this be?Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B
Hello, I'm working with an Agilex 5 E-Series A5ED043BB32AI4S device. On my board, I have two 32-bit LPDDR4 interfaces connected to the HSIO banks 3A and 3B. The DDR reference clock is available only on the dedicated differential CLK pins in bank 3A (K105/M105). There is no refclk in bank 3B. HPS EMIF case Using the External Memory Interfaces for HPS IP configured as 2x32 LPDDR4, Quartus instantiates two EMIFs (one in bank 3A and one in bank 3B). From the generated netlist (see attached images), it appears that the PLL associated with the EMIF in bank 3A receives the external CLK (K105/M105), the PLL reference clock is then internally forwarded/shared to the PLL associated with the EMIF in bank 3B. The design routes and fits successfully. This is the intended DDR architecture on my board and works correctly. FPGA EMIF case For debug purposes, I would like to use the LPDDR4 External Memory Interfaces (EMIF) IP together with the EMIF Debug Toolkit. Since this IP only supports up to 1x32 LPDDR4, I instantiated one LPDDR4 EMIF in bank 3A and one LPDDR4 EMIF in bank 3B. The EMIF in bank 3A works correctly when using the REFCLK in bank 3A (on K105/M105). However, I cannot get the EMIF in bank 3B to fit when its PLL reference clock is assigned to the same REFCLK source located in bank 3A. The fitter reports routing/connectivity issues. Questions 1) For the FPGA LPDDR4 External Memory Interfaces (EMIF) IP, is it mandatory that the PLL reference clock be located in the same bank as the EMIF instance? 2) Is there any supported mechanism to share or bypass the PLL reference clock from the EMIF PLL in bank 3A to the EMIF PLL in bank 3B, similar to what appears to be done automatically by the HPS EMIF 2x32 implementation? Any guidance would be appreciated. Thanks,
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As AI, cloud, and high-performance computing systems continue to scale, data center operators need more bandwidth within increasingly constrained power and thermal envelopes. Linear Pluggable Optics (LPO) offers an important path forward by simplifying optical modules, reducing power consumption, and lowering latency. LPO places signal-conditioning responsibilities in the host device, allowing the optical module to operate without the DSP used in traditional retimed optics. This architecture can reduce optical module power by 30% to 40%, helping data center designers increase connectivity density while simplifying cooling and thermal management. Altera Brings LPO to the FPGA Market Altera is the first FPGA provider to publicly demonstrate Linear Pluggable Optics interoperability using production FPGA devices. Continued validation with LPO modules from Amphenol and FS further demonstrates the breadth of the emerging ecosystem supported by Altera. Agilex® 7 FPGAs and SoCs bring the power and latency advantages of LPO to programmable platforms used in SmartNICs, data processing units, AI accelerators, and custom infrastructure. The initial public demonstration established that Agilex 7 devices could successfully interoperate with 400G LPO modules. The latest validation advances that milestone by confirming that the implementation meets the performance requirements expected for deployment in demanding data center environments. Validated for Real Deployment Conditions Comprehensive testing confirms that Agilex 7 F-Tile transceivers meet the electrical and link-performance requirements defined by the 100G-DR-LPO specification. The validation demonstrated: Compliance with the required transmit, receive, and link-performance criteria Successful interoperability with LPO modules from Amphenol and FS Successful LPO connectivity across distances from 1 meter to 500 meters Consistent performance across temperature and voltage conditions Measurable performance margin beyond required thresholds Testing covered demanding signal conditions, voltage variation, and temperatures ranging from minus 40 degrees Celsius to 105 degrees Celsius for electrical characterization. Functional link testing included a 1-meter LPO connection, a 100-meter active optical cable, and 500-meter LPO modules from Amphenol and FS. The results demonstrate robust, repeatable operation across multiple module suppliers and link distances, with measurable margin relative to the required performance limits. For customers, this validation provides confidence that Agilex® 7 support for LPO is ready for real-world deployment. Following the industry’s first public FPGA interoperability demonstration, the solution has now been evaluated against LPO performance requirements using modules from multiple suppliers and over link distances up to 500 meters. Together, these results demonstrate a practical foundation for deploying LPO connectivity in next-generation data center systems. More Efficient Connectivity for AI and Cloud Infrastructure The value of LPO grows as data centers deploy more high-speed optical connections. Eliminating the DSP from each optical module can reduce power across thousands of links, simplify optical module design, ease thermal pressure at the front panel, and support lower-latency data movement. Agilex 7 FPGAs add programmability to this more efficient optical architecture. Customers can combine LPO connectivity with packet processing, acceleration, security, telemetry, and evolving protocol support on a single adaptable platform. This flexibility is especially valuable for AI clusters and cloud infrastructure, where workloads, network architectures, and connectivity standards continue to evolve. Validation with multiple module vendors also gives system designers greater flexibility as the LPO supplier ecosystem continues to develop. Ready for the Next Generation of Data Centers The combination of public interoperability and comprehensive validation marks a major step for LPO in the FPGA market. Altera has demonstrated that LPO works with production Agilex 7 devices and validated that the solution meets key LPO requirements with measurable operating margin. This gives customers a proven foundation for evaluating and deploying lower-power, lower-latency optical connectivity in real data center environments. With Agilex® 7 FPGAs, LPO is ready for real-world data center deployment.
1 month ago
Security requirements are entering a new phase. Systems being designed today may remain deployed for many years, while regulatory expectations, cryptographic standards, and threat models continue to evolve. For designs in industrial, communications, infrastructure, aerospace, defense, and embedded applications, long-term security is becoming a core platform requirement. FPGA-based designs allow designs to meet today’s security needs and evolve with tomorrow’s requirements. Altera is now offering Agilex® 3 and Agilex® 5 devices with PQC-enabled secure boot and configuration support, helping customers prepare for the next generation of security requirements. With the Quartus® Prime Pro Edition 26.1.1 release, customers can begin using a PQC flow that works with Agilex 3 and Agilex 5 based hardware. This milestone extends the security architecture already built into the Agilex platform. Agilex devices use the Secure Device Manager as a hardware root of trust for secure configuration and device management. By combining PQC-capable devices with Quartus software enablement, Altera is helping customers strengthen the FPGA chain of trust as post-quantum requirements move from planning to implementation. The value is immediate and practical. Customers can start designing with supported devices today, while using Quartus 26.1.1 to take advantage of the current software flow. This gives teams a path to address emerging compliance and security expectations without needing a future platform redesign. The same hardware foundation also allows for additional security enhancements over time. Customers designing with PQC-capable Agilex 3 and Agilex 5 devices can benefit from planned software and firmware improvements enabled by the underlying hardware, with no further FPGA hardware upgrade required for those enhancements. Agilex 3 devices bring this capability to power- and cost-optimized FPGA and SoC designs used in embedded, edge, industrial, control, and platform-management applications. Agilex 5 devices extend the same security direction into mid-range FPGA and SoC designs that require higher performance, greater integration, and broader system capability. Post-quantum readiness will continue to advance, and Altera is building that evolution into the Agilex platform roadmap. With PQC-capable Agilex 3 and Agilex 5 devices and Quartus 26.1.1 software enablement, customers have a practical starting point today and a scalable foundation for future security enhancements.
1 month ago
Altera has started to sample Agilex® 5 D-Series FPGA devices to customers, expanding the Agilex 5 family for customers building higher-performance midrange systems. This adds a second Agilex 5 path alongside Agilex 5 E-Series FPGAs, which are already in full production. Agilex 5 E-Series remains the production-ready choice for power- optimized midrange designs. It is a strong fit when customers need production availability, efficient power, and right-sized capability for applications such as industrial control, edge compute, physical AI, and embedded systems. Agilex 5 D-Series extends the family for designs that need more system performance headroom. It is intended for applications that place heavier demands on signal processing, embedded memory, memory bandwidth, and fabric performance, including broadcast, wireless, video, AI-enabled embedded systems, and higher-performance applications that benefit from memory interfaces such as DDR5 and LPDDR5 capability. One Agilex 5 family, two design paths Agilex 5 E-Series Agilex 5 D-Series In full production Engineering samples available Power-optimized midrange designs Higher-performance midrange designs Right-sized logic and efficient power More DSP, embedded memory, EMIF bandwidth, and higher DDR and LPDDR bandwidth Industrial control, edge compute, physical AI and embedded systems Data Center, Communications, Broadcast, video, and AI-enabled embedded systems Together, Agilex 5 E-Series and D-Series enable customers a clearer way to choose the right midrange FPGA path: production deployment today with E-Series, or higher-performance design evaluation with D-Series. Customers evaluating Agilex 5 D-Series can begin real-silicon design work with Quartus® Prime Pro Edition 26.1.1 support. To order Agilex 5 D-Series engineering samples, please contact your Altera representative. Visit the Agilex 5 D-Series page Visit the Quartus Pro 26.1 Page
1 month ago
Quartus® Prime Pro Edition 2026.1.1 expands memory options across the Agilex® FPGA portfolio. Memory is increasingly setting the performance, power, and lifecycle limits of modern systems. AI acceleration, packet processing, storage, video, industrial automation, and edge computing all depend on moving large amounts of data efficiently. At the same time, memory availability and vendor transitions can force design teams to revisit component choices long after a platform architecture has been selected. With Quartus® Prime Pro Edition 2026.1.1, Altera expands memory options across the Agilex portfolio. The release brings higher-speed DDR5 and LPDDR5 options to Agilex 7 M-Series FPGAs and SoCs, broadens component choice through documented LPDDR5X device support, and extends LPDDR5 support to Agilex 3 FPGAs and SoCs. Together, these enhancements give designers greater flexibility to balance performance, power, footprint, memory cost, and supply continuity. What is new with Quartus Prime Pro Edition 2026.1.1 Enhancement Customer value DDR5-6400 and LPDDR5-6400 on Agilex 7 M-Series devices Higher Memory Bandwidth Raises the maximum supported memory data rate from 5600 to 6400 MT/s, an increase of more than 14%. DDR5 delivers up to 204.8 GB/s of aggregate bandwidth, while LPDDR5 provides a lower-power, compact-footprint option for bandwidth-intensive designs. LPDDR5X device use in LPDDR5-compatible mode New Sourcing Option Adds sourcing flexibility when LPDDR5 availability, or component strategy favors an LPDDR5X device. LPDDR5 now available for Agilex 3 devices New Memory Support Added Brings a modern low-power memory option to power- and cost-optimized Agilex 3 device configurations. Two 6400 MT/s paths for high-performance systems Agilex 7 M-Series FPGAs and SoCs already combine high logic density, high-speed connectivity, and advanced external memory functionality in a device family available today in full-volume production. Quartus Prime Pro Edition 2026.1.1 strengthens that family’s offering with DDR5-6400 and LPDDR5-6400 in approved configurations. For DDR5, the move from 5600 MT/s to 6400 MT/s increases the maximum data rate by more than 14%. That additional throughput can help AI, networking, storage, and infrastructure designs sustain higher data movement without expanding the FPGA footprint. It can also give architects more flexibility in how they meet a target bandwidth, including the potential to optimize channel count, DIMM selection, board space, and subsystem complexity when the application and supported configuration allow it. LPDDR5-6400 brings a second option to the same top-line interface rate. LPDDR5 is increasingly relevant beyond mobile products because it combines strong bandwidth with lower I/O power and a compact board footprint. Those characteristics are valuable in embedded systems, smart network interface cards, industrial platforms, edge compute, and other designs, where thermal limits and board area matter alongside performance. The result is a high-end FPGA platform that lets designers choose between DDR5 for capacity and server-class memory options, or LPDDR5 for power and footprint efficiency, while reaching up to 6400 MT/s and 204.8 GB/s of aggregate memory bandwidth in selected Agilex 7 M-Series device configurations. LPDDR5X device compatibility adds practical supply-chain flexibility The LPDDR5X enhancement addresses a different customer need. LPDDR5X devices are backward compatible with the LPDDR5 interface, so components can be used with an Agilex LPDDR5 memory interface while operating at the same speeds, voltages, and specifications as the LPDDR5 configuration. Customers can now design with LPDDR5X components in LPDDR5-compatible mode with greater confidence, backed by documented Altera support process. A complete memory offering across the Agilex portfolio Because the Agilex portfolio spans high-performance, mid-range, and power- and cost-optimized devices, customers can carry a consistent FPGA architecture and Quartus development flow across products with very different memory requirements. That continuity helps reduce redesign effort and gives engineering teams more freedom to scale compute, connectivity, and memory together. Teams can preserve DDR4 or LPDDR4 where product requirements, temperature range, or supply conditions still favor those technologies. New designs can move to DDR5 or LPDDR5 for higher bandwidth and better system efficiency. LPDDR5X device compatibility provides an additional sourcing path without requiring customers to redesign a separate memory interface. Explore Agilex FPGA external memory solutions and review the Quartus Prime Pro Edition 2026.1.1 documentation for supported devices, speed grades, memory components, and configurations.
1 month ago
A customer recently shared with me an interesting way they viewed the updated Altera brand: It’s like a long-time friend who had moved away for a few years but is now back and it’s time to get caught up. One of the things customers might want to 'catch up' on is Altera's efforts with regards to AI. It started when early FPGA products included the first basic digital signal processing (DSP) circuits within the FPGA fabric to improve performance for math-based logic, such as Fast Fourier transforms (FFTs) and finite impulse response (FIR) filters. These early enhancements improved general purpose FPGA-based computing but since 2015, our focus has shifted to improving AI capabilities in both silicon and software tools. DSP capabilities have gotten more sophisticated (fixed point, floating point, small and large bit precisions, etc.) and the quantity of available DSPs within a single device, have increased dramatically. Modern FPGAs are now capable of handling complex equations, especially those needed with the introduction of AI. This historical reminisce catches us up all the way until today’s news, where the latest Altera FPGA family is now broadly available to any customer who wants it; Agilex™ 5 SoC FPGAs, the first FPGAs infused with AI tensor blocks throughout the FPGA fabric. A short list of features that would be attractive to embedded or intelligent edge applications include: For those haven’t heard about Agilex™ 5 devices before today, here is how you can get started: Learn about the family. Review technical details. Download FPGA software. Free for anyone wanting access to Agilex™ 5 E-Series devices: Download Quartus® Prime Pro Test drive hardware (generally available now, lead-times may apply, via franchised distributors): Buy Altera development kits or 3rd party boards and SoMs The initial wave of board/SoM options include 9+ variants, with more coming. Evaluate AI or embedded options: Test out the FPGA AI Suite. Contact Altera sales for limited time introductory pricing. Utilize 3rd party tools (Arm DS, MathWorks) to design for the new, best-in-class Arm dual-A76 + dual-A55 based SoC subsystem or RISC-V based Nios® V soft IP processors. Altera is announcing the Agilex™ 5 family broad availability coincident with Embedded World 2024 because it is one of the key markets this mid-range FPGA family was architected for. Embedded customers clearly told us they perceive a lack of adequate compute in embedded processors, see a big need to fill security gaps, and want to add AI into their next generation systems. Agilex™ 5 devices can address all these concerns. Coming back to our initial topic, AI: GPUs are certainly a popular choice for AI training, but power consumption of GPUs for AI inferencing may be too high for intelligent edge or embedded applications. Instead of adding a separate GPU/AI semiconductor device to an embedded system (resulting in higher cost, more power, more thermal, etc.), why not add the AI function into an FPGA already planned to be used in embedded/edge equipment? For decades, FPGAs have been used in embedded/edge and communication systems for real-time control, IO connectivity, or image/data processing. The estimates on Agilex™ 5 device AI performance look good compared to equivalent class competitors. Because the FPGAs new DSP/tensor is implemented in a fine-grained architecture, it provides the FPGA designer the ability to tune for higher performance or lower power consumption, using the minimum amount of FPGA resources for the desired algorithm. Agilex™ 5 devices – AI key figures of merit: Tensor neural acceleration performance: Up to 26 / 56 TOPS ² Better performance per power efficiency versus embedded market inference GPUs. 1.7x higher frames per second per watt ³ Better raw performance versus other AI targeted FPGAs. 69% higher frames per second ⁴ There are many great reasons to look at this new family of FPGAs. If you are an architect, AI developer, or FPGA designer for embedded systems, don’t wait. As Mark Twain famously said, “The secret of getting ahead is getting started.” Don’t believe the marketing hype, try out your ideas in actual hardware, to see what is ‘possible’. Agilex™ 5 SoC FPGAs are just the latest phase in our DSP/AI journey. Altera, accelerating innovators. Come visit us at Embedded World 2024: Altera booth Hall 5, 5-135 and 5-136. Footnotes: Performance per watt: https://edc.intel.com/content/www/us/en/products/performance/benchmarks/agilex-fpga/ Theoretical peak INT8 calculations for the largest density Agilex 5 E-Series or D-Series devices. 1.7x higher frames per second per watt vs. Nvidia Jetson-class GPUs (AGX Orin) 69% higher frames per second vs. AMD/Xilinx Versal AI devices (VE2302)
1 month ago