Recent Content
Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy
Hi, 1. The Agliex 7 F Series EMIF User Guide page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F series evaluation board DDR4 memory vendor datasheet (thisis publicly available one for the MT40A2G8VA used on above linked eval board) states RESET must be low while power rails ramp up as pictured below which implies it should be instead pulled down to ground. Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies? From above public Micron datasheet 2. Figure 143 in section 6.5.6.1 of Agilex 7 EMIF User Guide shows ADDR/CMD clock terminated to VDD through R and C network. Altera F Tile eval board has ADDR/CMD clock terminated to GND through R and C network. Can Altera explain why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation? From Eval board Thanks!Ashling IDE scripted project creation
On Windows, is there a way to script the Ashling IDE project creation (or import an existing project)? I'm trying to clean my project down to the bare minimum for CM/repo purposes (deleting .metadata), and then have an automated way to recreate the project up to the point I can open Ashling RiscFree IDE, point to my (newly recreated) workspace, and then the project is already imported and ready to build, with all my previous settings (include paths, optimizations). Right now, the only way I can get this to work is if I manually click File -> Import and go through that dialog to import my sources from the repo. I need a hands-off way to do this. I looked at the Ashling RiscFree IDE manual, but couldn't find anything.
AGILEX 5 cvp mode
Hello, I'm using the Arrow Eagle board and trying to use CVP mode. I've flashed the JIC file and am now trying to upload the core.rbf file using this command echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name but the directory /sys/kernel/debug/fpga_manager/ does not exist. I noticed that the directory /sys/class/fpga_manager/fpga0/ exists, but there is no firmware_name file ls /sys/class/fpga_manager/fpga0/ => device/ name power/ state status subsystem/ uevent How can I resolve this issue?
Interface LVDS to Gigabit transceivers
Hi, I need to interface LVDS transmitter channels from a Cyclone 10 GX to Gigabit receivers in Arria 10, in other words from LVDS to 1.5V PCML. The reason is backwards compatibility in our hardware. Is it possible with only AC-coupling or am I missing something? The link will be asynchronous, clock recovery at the receiver, double data rate, clock frequency of 1GHz.
Agilex 7 R-Tile CXL IP: D2H write bandwidth does not scale with dual CAFU AXI-MM ports
Device: Agilex 7 I-Series AGI027 Software: Quartus Prime Pro 24.3 IP Core: CXL Type 2 IP Issue Description: We are attempting to increase CXL Device-to-Host (D2H) write bandwidth by utilizing both CAFU AXI-MM ports (port 0 and port 1) provided in the CXL Type 2 IP design example. However, our measurements show that enabling both AXI ports does not improve bandwidth as expected. For Non-cacheable writes, bandwidth remains unchanged when moving from one port to two ports. For Cacheable Owned writes, bandwidth decreases when using two ports. Please refer to the figures blow for detailed results. We are using the design example configured with two DCOH slices. To avoid potential DCOH contention, we've implemented address interleaving such that: - AXI port 0 only accesses addresses corresponding to "even number × 64B" - AXI port 1 only accesses addresses corresponding to "odd number × 64B" Despite this, no bandwidth improvement is observed for either Non-cacheable or Cacheable Owned traffic. Additionally, the non-cacheable bandwidth curve remains almost identical regardless of whether one or both AXI ports are used. This suggests that the exercised hardware path may contain a bottleneck or contention point within (either soft or hard part of) the CXL Type-2 IP. We would like to understand how to resolve this bandwidth limitation. If it cannot be improved, we would appreciate clarification on the underlying cause of this behavior. Thank you for your time and support.
Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0
Hi, We are working with the following differential clock input pins: - CLK_[T,B]_2[A,B]_[0:1] (P/N) - CLK_[T,B]_3[A,B]_[0:1] (P/N) Could you please confirm the allowed common-mode voltage range for these differential clock inputs?
Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger
Hello, I have to reopen another topic from last year: Arria 10: Remote Update may brick FPGA and Factory Fallback won't work | Altera Community - 315011 Opposed to my comments in the original thread, enabling the watchdog does not trigger a factory fallback if the application Image is wrongly aligned. This brings me back to this scenario of the original post: Invalid application load image location, i.e. start of application load is shifted by1-10 Byte (Manually induced error scenario) --> The reprogramming sequence starts but never completes and no fallback to the factory load is performed. => The FPGA is completely unresponsive unless programmed via JTAG It is obvious, that the this scenario might be an exotic error scenario, however we require a robust setup and have to make sure, that the FPGA remains accessible under any circumstances, so we need the Factory Fallback mechanism to work reliable! We have this boot procedure: Boot into factory image (0x20 as boot address in flash boot sector 0x00 to 0x1F). We have certain HW which is sensible to boot up timing so we need this to guarantee an identical and reliable boot up procedure. Boot from factory load into application image Check for power up boot: Read RU_RECONFIG_TRIGGER_CONDITIONS register for power up state (0) do not reconfigure if Bit 4,2,1,0 is set Set AnF bit: write "1" to RU_CONFIGURATION_MODE Set application image address RU_PAGE_SELECT Enable Watchdog Set RU_WATCHDOG_TIMEOUT & RU_WATCHDOG_ENABLE Reconfigure: write "1" to RU_RECONFIG In Application mode we only read the RU_RECONFIG_TRIGGER_CONDITIONS as status info We do not write the RU_WATCHDOG_ENABLE nor RU_RESET_TIMER registers I have run tests, with a Application Image being stored with an offset of -2 Bytes, i.e. the first 2 Bytes of the Application image are not stored in Flash Memory and the full image is shifted in its Flash storage. In this case, the FPGA gets stuck in an unresponsive state, when trying to load the application image. There is no fallback to the factory load happening, no CRC error, no watchdog triggering. As a best guess I could assume it might be related to this Note in 1.3.1. Remote System Configuration Mode that the factory fallback mechanism won't work for Arria 10 FPGAs if the last 576 Bytes of the bitstream are corrupted. Note: The fallback to the factory image does not work under the following conditions: If the last 576 bytes of an unencrypted application image bitstream are corrupted. Intel recommends that you examine the last 576 bytes of the unencrypted application image before triggering the application image configuration. But I have noticed that the binary images of the FPGA bitstream vary in size. So there is no way to check explicit memory locations for these 576 Bytes. Is there any way to identify this section? My Questions: Why is the factory configuration fallback mechanism not working in the above described scenario? The Factory load image is valid! How can I examine/validate a FPGA bitstream in flash memory before executing it? best regards Fabian
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