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Generating RBF raw binary file on Max 10
I am trying to design an in-system firmware update for the Max 10 FPGA. I have a microcontroller between the FPGA and the outside world. The microcontroller has a large data storage area where I want to store the data for the new FPGA firmware. I want to load the data into there, then at some later time, have the microcontroller take care of sending the update to the FPGA. In the interest of modular design, I want to store the data in a generic or raw format. This will give the microcontroller the option of bit-banging the JTAG of the FPGA, or sending over any other communication channel. However, I am not able to find a way to get the raw data that goes into the CFM0 section of the FPGA's configuration flash. When I compile the FPGA's firmware, I get the SOF and POF files. I am able to use the POF file directly with USB Blaster as usual. However, these file formats are apparently not public information, so I can't reliably build my own tool for extracting the raw data. So I started looking into the available utilities in the Quartus software. In the Quartus Programmer, I looked at File -> Create JAM, JBC, SVF, ISC. All of these formats basically generate a file containing a list of JTAG instructions. Because I want the design to be modular, I do not want to use this directly and be locked into JTAG. Since these formats are documented, I think it would be possible to build my own post-build tool that emulates the receiving end of JTAG and extracts raw data from one of these formats. However, I would like to get the raw data directly somehow in order to minimize risk of error building my own tool like that. So I confinued looking elsewhere to get the raw data. Next, in the Quartus IDE, I found File -> Convert Programming Files. This utility can generate an RBF file (Raw Binary File), which is EXACTLY what I need. I selected output file type "Raw Binary File (.rbf)", selected the compiled SOF file as the input, and clicked Generate. This gives me the vague error message "Device 10M02SCE144 does not support selected configuration mode". Playing around with lots of settings, I never could get it to generate an RBF file for me. I was searching the internet how to do this. Ideally, I wanted a command line way of generating the file so I can do this with a post-build script and have the ability for a build server to do this, etc. I found some instructions using the Quartus Nios II Command Shell. It seemed I needed to install a full distribution of Linux on my PC in order to use the shell... Not willing to do that (I am running Windows 11), I did some more digging, and I found the actual EXE file on my hard drive that the command shell stuff was going to run for me, "quartus_cpf.exe". I ran it like this: quartus_cpf.exe -c firmware.sof firmware.rbf It still failed, but now I get a slightly better error message: Device 10M02SCE144 does not support 1-bit Passive Serial scheme Error (213050): Convert Programming Files was NOT successful -- refer to messages that appear above this message for more information Error: Quartus Prime Convert_programming_file was unsuccessful. 1 error, 0 warnings After all of that, I am still stuck. How can I properly get to the raw binary format for the CFM0 memory?3Views0likes0CommentsQuesta 2 licenses?
I got a new work PC (WIndows 11) recently, so I downloaded Quartus Prime Lite 25.1. At the time, I also included Questa Altera Edition in the download. But I didn't try to use Questa. Last week, I read the directions on going to the SSLC and got a license so I could start using Questa. I got the license file, put it in a folder, and followed the directions to set it up in the Environment Variables. I then tried to use Questa and I'm getting the error "Unable to Checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER) is set correctly and then run 'lmutil lmdiag' to diagnose the problem." So I dd that. It seems that I have two license files. One looks like it was set up automatically when I originally downloaded Quartus and Questa and the second that I got from the SSLC. Looking in the Environment Variables, under User variables for [my_user_name], there is a variable SALT_LICENSE_FILE with a value of C:/Users/[my_user_name]/questa_lic.dat. And under the System variables there is a variable called SALT_LICENSE_SERVER with a value of C:\[the_folder_I_setup]. I didn't set up the first environment variable. The second one is the one I entered according to the instructions on the SSLC. Looking at the first license file with a text editor, I see that it is using the MAC address of my laptop's wifi adapter. And looking at the second license file, I see that it is using the MAC address of my laptop's wired Ethernet adapter. I think I was on wifi when I originally downloaded everything. And I was wired when I got the license from the SSLC. What should I do? Which license file should it be using? Why are there two variables and two license files? Since the wifi and wired connections on any computer always have different MAC addresses, is it not possible to use Questa with both? In other words will I always have to be using one of these connections and not the other? That would stink. Thanks.13Views0likes2CommentsAltera Extends Agilex®, MAX® 10, and Cyclone® V Lifecycles Through 2045 for Long-Life Systems
2 MIN READ Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.94Views0likes0CommentsNiosV µC/OS-II TCP-IP debug
Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devkit, so I compiled it for two different Arria10 targets. For both targets, I get the error: [network_init] Failed to NetIF_Start(): (2010). TSE link seems to be OK. Since I'm not experienced with Nios, I'm looking for help to debug it. Thanks52Views0likes7CommentsQuesta – Altera FPGA Edition simulator licensing
Hello all, I am trying to get this simulator to work with a fixed license file but when trying to open it I get the licensing error shown below Currently my environment is configured so that environment variable LM_LICENSE_FILE points to the .dat fixed license file. SALT_LICENSE_SERVER environment variable doesn't exist in my environment. Am i missing anything regarding the configuration of my environment? Could somebody please help me solve this licensing problem? Thank you very much in advance for your help. Best Regards, Eduardo.45Views0likes4CommentsS10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!20Views0likes2CommentsWhy the Agilex® 5 FPGA MPU hang when accessing higher memory regions?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 GSRD and earlier, when the Agilex® 5 FPGA HPS MPU access memory regions greater than 2GB this will cause the system to hang. This is because the higher memory bank region was not mapped in the MPU Table. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v25.1 GSRD release. u-boot-socfpga tag is QPDS25.1_REL_GSRD_PR.ASx4 Interface debug in MSEL=111 (JTAG mode)
Hi, could you, please, help me understand what is happening here: I am working with an Agilex3 FPGA (fuses are on factory default, no keys programmed, etc.) MSEL=111, so we are in JTAG mode I am trying to debug the NOR flash interface through Configuration Debugger / QSPI Controller and SFDP page. I have connected an oscilloscope. When I press Read button without QSPI Debug Session Activate button pressed, I see some NOR flash transactions on the oscilloscope and get back an Error 0x515 Unknown error and nothing is read in the SFDP window. So I try the QSPI debug session active way, and when I press it I get a lot of content but anything below the SFDP line in the tree structure is random at each read button press AND I do not see any NOR flash transaction at all on the ASx4 interface. (Did it several time, so yes, I did not forgot press the trigger active button.) So questions: is this an expected behavior? Copilot suggest that ASx4 interface is not initialized when MSEL=111 and I am reading some internal "garbage" If this is expected, should not the Quartus Programmer tool (which reads MSEL=111 correctly) warn me that I should not expect any meaningful output in this debug window? Is there any way to use the JTAG interface here as supposed: test the interfaces for problems? if yes, how?! (I stuck for a few more days/weeks with MSEL=111, so if that is the solution just let me know.) Thanks, Peter33Views0likes3CommentsConnecting Intel Agilex FPGA to DE1-SoC via Hub
Hello, I have an Intel Agilex FPGA with QSFP-DD 10 GbE PHY, a DE1-SoC board with 1 GbE PHY, and an Ethernet Hub 1 GbE. I want to connect the Agilex to the DE1-SoC through this hub. I understand the DE1-SoC only supports 1 GbE while the Agilex PHY is capable of 10 GbE. I would like to know the best way to communicate between these boards. Is it possible to configure the Agilex Ethernet IP and PHY to 1 GbE so it can communicate directly through the hub without a physical adapter? If not, would a media converter or adapter be needed to downspeed from 10 GbE to 1 GbE? Are there any recommended best practices for connecting an Agilex to a slower device like the DE1-SoC via Ethernet? Any guidance or experience would be greatly appreciated. Thank you!14Views0likes2Comments
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Recent Blogs
2 MIN READ
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
2 hours ago0likes
In a world where technological complexity is rising, standards are evolving, and differentiation is critical, customers need partners who can move fast, stay focused, and innovate without compromise. At Altera™, operating as an independent pure play FPGA solutions provider is more than a corporate structure. It’s a strategic advantage. For more than four decades, Altera has been at the forefront of FPGA innovation, helping customers push the boundaries of what’s possible across the most demanding applications. With our recent operational independence and singular focus on pioneering FPGA innovations, we are uniquely positioned to deliver FPGA solutions that enable customers to differentiate, innovate, and grow in rapidly changing markets. Why Demand for FPGAs is Accelerating The FPGA industry is entering a period of strong, sustained growth, driven by powerful forces across cloud, networking, and edge applications. As enterprises race to process and monetize exploding volumes of data, FPGAs have become a critical enabling technology, uniquely suited for workloads where flexibility, re-programmability, and real-time performance matter most. Over the next five years, the market is expected to grow at roughly 10% CAGR, expanding from an estimated ~$7B in 2025 to more than $13B by 2030¹. Demand is accelerating across data center and networking, telecom, aerospace and government, industrial automation, robotics, medical, and beyond. Growth is being driven by AI infrastructure modernization, 5G-Advanced and early 6G deployments, and the rise of physical AI and real-time, low-latency edge computing. At the same time, escalating development costs for ASIC and ASSPs, longer development cycles, and the need for post-deployment flexibility are pushing more customers toward programmable solutions that reduce risk while maintaining performance and differentiation. Altera is uniquely positioned to help drive this next phase of growth. As the largest independent, pure-play FPGA solutions provider, our agility and focus allow us to move faster, invest deeply in a thriving ecosystem, and deliver differentiated, end-to-end solutions backed by strong customer support. By partnering closely with customers, we enable them to seize opportunities across AI, cloud, networking, and edge applications. While at the same time allowing customers to stay ahead as new technology inflection points emerge. Let’s take a closer look at how Altera’s independence strengthens the five strategic pillars that matter most to our customers: Innovation, Quality, Ecosystem Partnerships, Solutions, and Community Support. Faster Decisions Enable Faster FPGA Innovation Altera’s independence means customers benefit from faster decisions, quicker execution, and a partner that can adapt as requirements evolve. Free from competing priorities or broader corporate agendas, we respond rapidly to market shifts, delivering new capabilities sooner, resolving challenges faster, and helping customers stay on track with demanding development timelines. This momentum is reflected in Altera’s renewed commitment to the broad-based FPGA market and the launch of our power- and cost-optimized Agilex® 3 FPGAs, supported by an expanding ecosystem of partner boards. Altera’s first power- and cost-optimized FPGA since the launch of Cyclone 10, Agilex 3 enables industrial, automotive, and edge AI customers to accelerate differentiation and reduce time-to-market. Our investments are not stopping here. We are advancing a next-generation FPGA roadmap that delivers new levels of performance while introducing the next wave of power- and cost-optimized devices, providing a clear and scalable path forward across the Agilex portfolio. A Relentless Focus on FPGA Quality Because Altera is singularly focused on FPGAs, our priority is to ensure our programmable solutions meet the industry’s most demanding quality and lifecycle requirements. Every investment, engineering decision, and roadmap commitment is dedicated to delivering rigorously validated silicon, dependable software tools, long-term product availability, and sustained support that customers designing mission-critical systems require, including long-term supply commitments extending to 2035 and 2040 for select product families. This unwavering focus allows us to provide the stability, reliability, and multi-decade lifecycle assurance FPGA customers depend on, with no competing agendas and no compromise. Additional information about Altera’s quality and reliability can be found at: https://www.altera.com/quality/overview Accelerating FPGA Innovations Through a Robust Ecosystem FPGA value is unlocked faster through a strong, connected ecosystem. Altera supports a global network of more than 300 validated FPGA partners delivering over 1,400 proven solutions spanning IP, development tools, system integration, and turnkey platforms. By leveraging these pre-validated solutions, customers can reduce development time by up to 50%, lower risk, and accelerate time-to-market. Through deep ecosystem investments, we extend the power and usability of Altera FPGAs, enabling faster system-level innovation and helping customers move from concept to deployment with greater speed and confidence. Learn more about the Altera Solution Acceleration Program at: https://www.altera.com/asap Purpose-built Investments Across the FPGA Stack Every dollar we invest is directed toward advancing FPGA innovation. A recent example includes expanding our MAX® 10 FPGA family with new high-I/O density Variable Pitch BGA (VPBGA) packages, which deliver up to 485 I/Os in a compact 19 x 19 mm footprint, reducing board size by 50% compared to traditional 27 x 27 mm packages and enabling more space-efficient Type III PCB designs. We are also accelerating productivity through tools like Visual Designer Studio, which dramatically reduces development cycles by reducing system creation time from five days to as little as two hours. In parallel, we continue to invest in a broad portfolio of FPGA IP, spanning interfaces, memory, DSP, embedded processing, and connectivity. An extensive portfolio of Altera and parter IP provide pre-validated building blocks that reduce design complexity and speed integration. Together, these investments across silicon, packaging, software, and IP ensure continuous gains in performance, power efficiency, programmability, and ease of use. Customer Support Focused Exclusively on Solving FPGA Challenges Support is another area where independence makes a meaningful difference. Altera’s teams are entirely dedicated to solving the real-world challenges customers face. Our commitment to our customers is reinforced by the recently launched Altera Premier Support (APS) and Altera Community portals. These platforms provide streamlined access to engineering assistance, service request tracking, technical resources, and peer collaboration, ensuring customers have both direct expert support and 24/7 self-service capabilities. This deep specialization enables faster issue resolution, more relevant guidance, and a true partnership mindset. Whether optimizing designs, debugging complex systems, or scaling into production, customers can rely on experts who live and breathe FPGA solutions. Learn more about Altera communities, visit https://community.altera.com/ Enabling Innovators to Shape What’s Next As the largest independent, pure-play FPGA solutions provider, Altera is entering a new era defined by agility, focus, and the freedom to innovate at the pace of change. Our independence allows us to invest with intention, strengthen our ecosystem, and deliver complete solutions backed by deep customer engagement. By working side-by-side with our customers, we’re not just responding to technology inflection points across AI, cloud, networking, security and the edge… We’re helping customers shape what’s next. Visit Altera at www.altera.com (1) Source: Based on Altera and 3rd-party data
8 days ago1like
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.
8 days ago0likes
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.
9 days ago0likes
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.
11 days ago0likes