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Dear Team, Hope you are doing well. Can you please help us in providing below details for Altera product categories. in addition to this does Altera has this info avaialble for other product catergories as well. if yes, where can we find this info. Please advise. Product Catagories Manufacturing/Assembly/Wafer Plant City Country Field Programmable Gate Arrays Programmable Logic Devices Flash Memories
Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins [TEST]
In the Pin Connection Guidelines below, the connection method for the RCOMP_GTS pins has been changed. https://docs.altera.com/r/docs/813266/current/pin-connection-guidelines/example-1-agilextm-5-devices-with-speed-and-power-grade-1v-2v-2e-and-3v Related KDB: Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? | Altera Community - 353565 We have two questions. Is this change due to a change in the device itself (silicon or specification)? Or was only the document updated, with no change to the device? Why do the HVIO input pins stop working when RCOMP_GTS is floating? We thought the HVIO bank and the GTS transceiver bank were not related.
Investigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
We are investigating the cause of fluctuations in the HIGH-level voltage of a 3.3 V LVTTL output signal from the MAX 10 FPGA. Device Part Number: 10M08DCF256I7G HIGH-Level Voltage: 2.8 V to 3.3 V 1.Verification of BANK Power Supply Stability We compared the BANK power supply voltage with the signal voltage and confirmed that the power supply voltage remains stable even when fluctuations occur in the signal voltage. 2.Relationship with the Connected Device (Under Investigation) Connection: MAX 10 → [3.3 V LVTTL, 8 mA] → DS90CR287 ・Changing the damping resistor from 22 Ω to 0 Ω did not affect the issue. Could you please advise us on the possible causes of this issue and any additional aspects we should investigate?
Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins
Hi There, In the Pin Connection Guidelines below, the connection method for the RCOMP_GTS pins has been changed. https://docs.altera.com/r/docs/813266/current/pin-connection-guidelines/example-1-agilextm-5-devices-with-speed-and-power-grade-1v-2v-2e-and-3v Related KDB: Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? | Altera Community - 353565 We have two questions. Is this change due to a change in the device itself (silicon or specification)? Or was only the document updated, with no change to the device? Why do the HVIO input pins stop working when RCOMP_GTS is floating? We thought the HVIO bank and the GTS transceiver bank were not related. Kindly advise. Thank you.Leakage Current in MAX 10 Bank 1A (ADC Bank)
Device：10M08DCF256I7G We have connected the following voltage divider circuit to each of Bank 1A and Bank 8 of the MAX 10 device. 12 V → 10 kΩ / 3.6 kΩ voltage divider → MAX 10 input (typical voltage: 3.18 V) The measured voltages at each bank are as follows: Bank 8: 3.17 V Bank 1A: 3.06 V The voltage at Bank 1A is lower than that at Bank 8. We checked the 12 V input voltage and resistor tolerances, but found no deviations large enough to account for this difference. We also found the following statements in the datasheet: ////////// The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V). 10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on. Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A. ////////// Could you please confirm whether it is reasonable to conclude that this phenomenon is caused by leakage current specific to Bank 1A (the ADC bank)?Can Agilex 3 A3CY100BM16AE7S (AXC3000) use SDM cryptographic services?
Hello, I would like to confirm whether the SDM cryptographic services (user-mode access through the Mailbox Client IP) are supported on this device: Device: A3CY100BM16AE7S (Agilex 3 C-Series 100, M16A), Arrow AXC3000 board Tools: Quartus Prime Pro 26.1 build 110 Mailbox Client IP: Enable C-r-y-p-t-o Service = 1, C-r-y-p-t-o Memory Timeout = 10000, AXI manager connected to an on-chip RAM (confirmed in the compile log: intel_memory_initiator_endpoint with has_offload=1) Access: from fabric over Avalon-MM, no HPS What I observe (3 runs each, identical results, response FIFO empty after each command): - NOOP -> response header 0x00000000 (OK) - GET_IDCODE (0x10) -> header 0x00001000, data 0x4361B0DD (OK) - GET_CHIPID (0x12), GET_USERCODE (0x13), GET_TEMPERATURE (0x19), CONFIG_STATUS (0x04) -> all return the documented response lengths - open_crypto_service_session (0xA0) -> header 0x00001085 (error code 0x085, LENGTH=1), data word 0x000000FF - close_crypto_service_session, random_number_request, aes_crypt_request, get_digest_request, ecdsa sign/verify, ecdh_request -> header error code 0x085 (LENGTH=0) What the documentation says: - Agilex 3 C-Series Product Table (2026.02.11): specification code Y has C-r-y-p-t-o = No ("user mode access to the SDM hardened cryptographic IP"); codes U and W have C-r-y-p-t-o = Yes. - Security TRM: the error table of open_crypto_service_session lists both 0x0F (function not supported on the device) and 0x85 (command not allowed under the current security settings). - Security Overview for SDM-based devices, section 2.6, says the SDM C-r-y-p-t-o engines are made available to the FPGA design through the mailbox in user mode, without mentioning per-device restrictions. Questions: 1. Does A3CY100BM16AE7S (spec code Y) support SDM cryptographic services through the Mailbox Client IP? 2. If not, is 0x085 the expected response, or should it be 0x0F? 3. If the device is supposed to support them, what could make the SDM reject the command with 0x085 (security settings, provisioning, initialization)? 4. Is there any supported way to enable these services on this device? Thank you.DK-DEV-AGI027RBES CXL Type-3 example remains in reset and is not detected by host
Hi, I have several Agilex 7 FPGA I-Series Development Kits with serial numbers 8100035 and 8020138. My goal is to run the boards as CXL Type-3 devices and verify that they can be enumerated by the host. I am currently debugging board 8020138 with the following setup: Board: DK-DEV-AGI027RBES FPGA: AGIB027R29A1E2VR3 Power configuration: Power Solution 2 Quartus Prime Pro: 24.3 Connection: PCIe edge connector Design: CXL Type 3 with DDR4 Link width: CXL x16 Number of slices: 2 PLD clock: 400 MHz Reference clock mode: Common Refclk source is global clock: Enabled The board can successfully enumerate as a normal PCIe endpoint when using the pcie_ed example design included in: agilex_agib027r29a1e1vb_fpga_revc_v24.3b194_v1.1 However, when I generate and compile the RBES CXL Type-3 DDR4 example design, the host cannot detect the device and it does not appear in lspci. I added JTAG debug registers and Signal Tap probes. The observed status is: config_done = 1 pll_lock = 1 sip_rst_n = 0 cxl_warm_rst_n = 0 cxl_cold_rst_n = 0 ip2hdm_reset_n = 0 ip2cafu_avmm_rstn = 0 ip2csr_avmm_rstn = 0 pf0_bus_master_en = 0 pf0_memory_access_en = 0 pf0_msix_enable = 0 The fabric heartbeat counter(refclk4) is running, so FPGA configuration and the debug fabric clock are working. However, the CXL cold, warm, and SIP resets never deassert, and host enumeration never starts. Could you please confirm: Are these CXL IP settings correct for board 8020138, Power Solution 2, and the PCIe edge connector? For CXL x16 with two slices, must both refclk0 and refclk1 be active? What conditions control cxl_cold_rst_n, cxl_warm_rst_n, and sip_warm_rstn_o? How can I observe the physical PERST# status, R-Tile reset status, PHY initialization status, LTSSM state, and link-up status? Should Enable PIPE Mode Simulation be disabled for hardware operation? Is 400 MHz the correct PLD clock frequency? Is there a known-good CXL Type-3 DDR4 example project or SOF for DK-DEV-AGI027RBES with FPGA AGIB027R29A1E2VR3? Are there any required Quartus 24.3 patches for this board and CXL IP? The normal PCIe example works, but the CXL example remains in reset. This suggests the issue may be related to the CXL IP configuration, reference-clock/reset requirements, or the generated example-design constraints. I can provide the IP configuration, QSF/SDC files, Signal Tap captures, compilation logs, and host logs if needed. Thank you. Best regards, Jeffrey
Agilex 5 GTS Reference Clock Buffer Protection
While reviewing the Agilex 5 GTS documentation, I found that the Input Reference Clock Buffer Protection mechanism automatically disables the reference clock buffer when the input clock is not toggling, and that the documented recovery methods are either reconfiguration or a buffer turn-on request. For an Agilex 5 design, I would like to clarify: Is there any supported method to keep the GTS reference clock buffer permanently enabled? Can the Input Reference Clock Buffer Protection mechanism be disabled? Is there any alternative to repeatedly issuing a Buffer Turn-on Request when the reference clock may stop and restart during normal operation? If not supported, is the documented re-enable procedure the only recommended approach?
