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Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
MegaWizard Plug-In Manager : ALTPLL [Corrupted in Quartus Prime Lite 25.1]
This is a newly discovered bug in: "Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition". As stated in the subject, I am encountering corruption of ALTPLL both at the graphical level and in the IP upgrade process. To confirm this, here is a screenshot. Kind regards.nSTATUS is sometimes asserted low during Agilex-F configuration when operating in PMBus slave mode
I am using Passive Avalon-ST 16 mode to configure the Agilex-F device. There is external PMBus master to run the ARA process of the SmartVID protocol immediately after sensing ALERT low signal. Sometimes when trying configuration after power up (starting the process by asserting nConfig low), nStatus goes low before reaching the point of ALERT signal going low. Retry of the configuration after such failure always succeeds. Any idea? Thanks, Itzik
LVDS SERDES rx_inclock idle
Hi, We are using LVDS SERDES IP as a multichannel LVDS receiver in Cyclone 10 GX device. The reciver is configured to run at DDR mode using 200MHz rx_inclock. The transmitter device output clock is not a free-running clock and is subjected to changes with correlation to the output data (for example clock is only running when the transmitter outputs data). I see in the Altera LVDS SERDES IP Core User Guide that the SERDES use IO PLL for that clock, meaning it should meet IO PLL cycle-to cycle clock jitter for the PLL input. Does that means that only a free running clock at a constant frequency and duty cycle can be used as part of the LVDS bus? How should i treat devices that has an LVDS bus clock that is correlated with data?
Asynchronous FIFO and discontinuous write clock
Hello, The FPGA is a Cyclone 10LP (10CL016YU256I7G). The FIFO is configured as separate write and read clocks, it is 32 words deep. I have a design where the write clock is discontinuous. I have a difference between simulation and hardware behavior. In fact, all works great in simulation. However, it does not work as expected in hardware. I suppose that simulation model is not accurate with the real hardware. What I observe, when I write the four words (full and empty signals are useless as I have another way of knowing how many words have been written), the first read is always 0 and the fourth read give me the penultimate word. So, question is : can we use this asynchronous FIFO with a discontinuous write clock ? Many thanks in advance for the help. Steve
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
