Recent Discussions
Has the 5AGXFB7K4F40I3G updated the process to replace the steel lid with the glass lid after 2021
Dear Sir or Madam We received a batch of product of part number 5AGXFB7K4F40I3G, the parts with steel lid, and the date code is 2133. But we found package drawing in the official website is different with the part. Link: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04R00410-09.pdf However, we received a batch of product with same part number before, these parts are glass lid, and the date code is 2225. This part is consistent with the package drawing in official website. So I would like to know whether the 5AGXFB7K4F40I3G updated the process to replace the steel lid with the glass lid after 2021. Can provide the steel lid package drawing? Thanks
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, BrianQuartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?
Mac internal loopback F-Tile, Quartus 25.2
Hi all, I have Quartus 25.2 and I'm looking to run some tests in loopback mode without having any physical hardware connected. I have Reflexv2 FPGA Card. Can you guide me which IP from quartus should i choose to run loopback for testing purposes? I want only to run internal loopback, without card connection. Best Regards, Przemyslaw Pajak
Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chips
Hello Guys, I read one post here, which requested the way to design carry chain style TDC based on Agilex 9 chips. Here is that post linkcarry chain tdc | Altera Community - 351924 Kenney answer that post and give some recommendations about it. Now I have similar questions about carry chain TDC by using ALTERA's Cyclone 10 GX. Is that wire LUT delay lines in Cyclone 10 Gx devices?
