Recent Discussions
A3C* BSDL updates available?
Hello, There are several of the A3CZ, A3CU and A3CV* families which are fail compilation with syntax errors on pins duplicated (usually K24 and K25). and then a most have errors in their use of port_grouping. Are there updates available? Regars, Tom iBSDL - Intellitech BSDL Compiler Version 14.25 Copyright (C) 1993-2026 Intellitech Corp. All rights reserved. ERROR: Device package pin mappings: Duplicate pin id K24 ( IEEE Std 1149.1 Rule B.8.7.3 a). ERROR: Device package pin mappings: Duplicate pin id K25 ( IEEE Std 1149.1 Rule B.8.7.3 a). INFO: Associated Port REFCLK_GTSL1A_RX_n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH3n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH2n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH0n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH1n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden ERROR: Associated port GTSL1A_TX_CH3n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH3n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH2n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH2n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH1n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH1n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH0n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH0n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) The compile failed.
Cold Temperature Issue
Hallo, We used the Agilex5 device in AS configuration connect to external QSPI Flash. We apply Smart VID interface at the device demands. When we perform Cold power up at -40C the device is not configured, It seemed the device is not output from the POR, No traffic on the PMBus. Power sequence and voltage ramp time and levels are OK. Please advise Thanks AsafALTPLL - BANDWIDTH OPTION ?
Here is a professional and technically accurate English translation: Hi, I would like to ask about the meaning of the following setting in ALTPLL: Bandwidth - Preset Options: Auto, Preset (Low, L, H), Custom What is the purpose of this setting? I am using the FPGA device 10M02SCM153C8G and implementing an SCFIFO. Due to the signal logic requirements, I need to generate a stable 180-degree phase-shifted version of the signal and feed it into the SCFIFO, as well as to the FX2 IFCLK connected after the SCFIFO. Currently, I am encountering a very rare issue: image tearing (or frame splitting). My system architecture is: sensor → FPGA (FIFO) → FX2 → PC. Although this issue occurs very infrequently, I would still like to explore possible improvements. Previously, the FPGA setting was configured as Auto, and under this condition, the image tearing issue occurred more frequently. After changing the setting to Low, the system became significantly more stable. I am now considering whether to try the Medium setting, but before making further changes, I would like to understand what this bandwidth setting actually controls. Would you like me to refine this into a more formal email style (for vendor support like Intel/Altera), or keep it as a technical discussion tone?
Stratix III FPGA Development Kit
"Hello! I am currently facing an unusual issue when trying to use the Stratix III FPGA Development Kit. After installing Quartus II 13.1 Subscription Edition (the last version supporting the Stratix III family) along with the respective device files (.qdz) for Cyclone, Arria, and Stratix III, and properly configuring the license on Windows 11, the Stratix III family does not appear in the device selection wizard. Interestingly, the Quartus Device Installer states that the family is already installed, but it remains hidden inside the software. To isolate the issue, I have tested multiple operating systems and Quartus versions, but the problem persists: 1) Windows 11 & Windows 7 (Quartus II 13.1, 13.0, and 12.1 Subscription): Arria and Cyclone families work perfectly. Stratix III shows as installed in the device manager but is unavailable inside Quartus. 2) Windows 7 (Quartus II 9.0 Web Edition): The Stratix III family appears in the family selection menu in Quartus, but our specific device (EP3SL150F1152) is listed as unsupported. 3) Ubuntu 12.04 (Quartus II 13.1 Subscription): Same behavior as Windows; the installer claims it is there, but Quartus does not show it. Given these cross-platform results, I suspect the root cause might be: 1) A corrupted or flawed Stratix III device installer file (.qdz). 2) A licensing restriction, where our current license might need a specific feature enabled for the Stratix III family, even though the software allows the installation. Could you please guide me on how to get this Stratix III Development Kit operational (which features the EP3SL150F1152 device)?" Thank you for your time and assistance. I look forward to your guidance. Best regards!
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
Cyclone V nRST assertion upon nPOR
Hello, I am looking for a confirmation on whether the nRST pin is driven low upon a nPOR input assertion. I have found no definite answer in the HPS TRM (cv_5v4 dated 2024.12.03). But HPS TRM version 1.3 (Nov 2012), Table 3-3 page 3-7 says with I ran an experiment today on our prototype, asserting nPOR once the system has boot-up (linux) and see no assertion of nRST pin. Also, in the Reset Manager register description, I see no configuration bit that would enable/disable nRST assertion upon nPOR. Can someone confirm the unconditional assertion of nRST upon a nPOR as I understand from HPS TRM from Nov 2012. Thanks, Best regard PascalModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。
Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)
Hello everyone, While reviewing the schematics for a Terasic DE10 board, I noticed a specific circuit block on the power rails. See attached image From my understanding of the schematic, when a specific Enable (EN) signal drops or is disabled, this circuit actively shorts the power rails to ground. My question is regarding the fundamental design here: If the power to the board drops, or the EN signal to the voltage regulators is pulled low, the voltage to the FPGA will naturally stop being supplied anyway. Why is there a need to spend BOM cost and board space on actively shorting the rails to ground? I would love a more in-depth explanation from a board-level design perspective. What exact failure modes or risks does this active discharge circuit prevent in FPGAs? Is this considered a mandatory best practice for all Agilex/Stratix/Cyclone designs, or is it only necessary under specific power supply topologies? Thank you for the insights!
Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.