FPGA Device

CPLDs, FPGAs, Configuration, and Power

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Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
Roshan
18 minutes ago
Configuration
Core Logic
Generic Io
Power
Programmable Logic Device
10Views
0likes
1Comment
Dedicated Clock Pins for MAX 10
Hello Intel Community, I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resources and the presence of only a single hardware PLL (PLL1) on this device, I need to ensure that my clock network architecture conforms strictly to the hardware requirements to achieve optimal jitter performance and complete phase compensation. My Application Topology: Clock Input: An external reference clock enters the FPGA and drives the inclk0 port of the instantiated ALTPLL IP core. Phase Shift: Inside the ALTPLL, the clock waveform is inverted by 180 degrees. Clock Distribution: This 180-degree phase-shifted clock is split into two destinations: Internal: It drives an internal single-clock FIFO (scfifo) within the FPGA fabric. External: It is routed out through a physical I/O pin to drive an external MCU. My Questions for Intel Support: Dedicated Input Pins: For the M153 package of the 10M02 device, which physical pin numbers are the true Dedicated Clock Input Pins that are directly hardwired to the internal PLL1's inclk0 port, enabling full hardware-level phase compensation (Normal Mode) without introducing routing delays or Quartus compilation warnings? Dedicated Output Pins: To output the 180-degree inverted clock to the external MCU, does this device feature any Dedicated Clock Output Pins (such as PLL external clock outputs) that are physically bonded out in the M153 package? Or are we required to route this clock out via regular user I/O pins through the global clock network? ALTPLL Operation Mode Advice: Considering that this clock simultaneously drives an internal FIFO and an external MCU, which compensation mode (Normal Mode vs. Zero-Delay Buffer Mode) does Intel recommend for the ALTPLL IP core to minimize clock skew and ensure optimal timing closure? Are there any specific parameters (e.g., compensate_clock) that must be explicitly configured to align with the chosen dedicated pins? Any official documentation snippets, device handbook references, or design guidelines regarding the clock routing constraints for this specific micro-package would be highly appreciated. Thank you in advance for your technical assistance! Best regards, Martin.
Solved
MartinMaa
36 minutes ago
Core Logic
Programmable Logic Device
214Views
0likes
12Comments
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"
Ouseph7
49 minutes ago
Configuration
Programmable Logic Device
Security
250Views
0likes
7Comments
A3C* BSDL updates available?
Hello, There are several of the A3CZ, A3CU and A3CV* families which are fail compilation with syntax errors on pins duplicated (usually K24 and K25). and then a most have errors in their use of port_grouping. Are there updates available? Regars, Tom iBSDL - Intellitech BSDL Compiler Version 14.25 Copyright (C) 1993-2026 Intellitech Corp. All rights reserved. ERROR: Device package pin mappings: Duplicate pin id K24 ( IEEE Std 1149.1 Rule B.8.7.3 a). ERROR: Device package pin mappings: Duplicate pin id K25 ( IEEE Std 1149.1 Rule B.8.7.3 a). INFO: Associated Port REFCLK_GTSL1A_RX_n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH3n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH2n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH0n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden INFO: Associated Port GTSL1A_RX_CH1n with function OBSERVE_ONLY in a boundary register is legal - 1149.1 Rule B.8.8.3 d overridden ERROR: Associated port GTSL1A_TX_CH3n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH3n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH2n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH2n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH1n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH1n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) ERROR: Associated port GTSL1A_TX_CH0n was found in a PORT_GROUPING attribute. Associated ports, the second port in a PORT_GROUPING statement can only be in the boundary register when the function in the BOUNDARY_REGISTER attribute is OBSERVE_ONLY. One solution would be to remove GTSL1A_TX_CH0n from the PORT_GROUPING attribute. ( IEEE Std 1149.1 Rule B.8.8.3 d) The compile failed.
tomachie
1 hour ago
Programmable Logic Device
quality|reliability
57Views
0likes
4Comments
Cold Temperature Issue
Hallo, We used the Agilex5 device in AS configuration connect to external QSPI Flash. We apply Smart VID interface at the device demands. When we perform Cold power up at -40C the device is not configured, It seemed the device is not output from the POR, No traffic on the PMBus. Power sequence and voltage ramp time and levels are OK. Please advise Thanks Asaf
Asaf_Bloch
4 hours ago
Configuration
Programmable Logic Device
159Views
0likes
14Comments
ALTPLL - BANDWIDTH OPTION ?
Here is a professional and technically accurate English translation: Hi, I would like to ask about the meaning of the following setting in ALTPLL: Bandwidth - Preset Options: Auto, Preset (Low, L, H), Custom What is the purpose of this setting? I am using the FPGA device 10M02SCM153C8G and implementing an SCFIFO. Due to the signal logic requirements, I need to generate a stable 180-degree phase-shifted version of the signal and feed it into the SCFIFO, as well as to the FX2 IFCLK connected after the SCFIFO. Currently, I am encountering a very rare issue: image tearing (or frame splitting). My system architecture is: sensor → FPGA (FIFO) → FX2 → PC. Although this issue occurs very infrequently, I would still like to explore possible improvements. Previously, the FPGA setting was configured as Auto, and under this condition, the image tearing issue occurred more frequently. After changing the setting to Low, the system became significantly more stable. I am now considering whether to try the Medium setting, but before making further changes, I would like to understand what this bandwidth setting actually controls. Would you like me to refine this into a more formal email style (for vendor support like Intel/Altera), or keep it as a technical discussion tone?
MartinMaa
5 hours ago
Configuration
5Views
0likes
0Comments
Stratix III FPGA Development Kit
"Hello! I am currently facing an unusual issue when trying to use the Stratix III FPGA Development Kit. After installing Quartus II 13.1 Subscription Edition (the last version supporting the Stratix III family) along with the respective device files (.qdz) for Cyclone, Arria, and Stratix III, and properly configuring the license on Windows 11, the Stratix III family does not appear in the device selection wizard. Interestingly, the Quartus Device Installer states that the family is already installed, but it remains hidden inside the software. To isolate the issue, I have tested multiple operating systems and Quartus versions, but the problem persists: 1) Windows 11 & Windows 7 (Quartus II 13.1, 13.0, and 12.1 Subscription): Arria and Cyclone families work perfectly. Stratix III shows as installed in the device manager but is unavailable inside Quartus. 2) Windows 7 (Quartus II 9.0 Web Edition): The Stratix III family appears in the family selection menu in Quartus, but our specific device (EP3SL150F1152) is listed as unsupported. 3) Ubuntu 12.04 (Quartus II 13.1 Subscription): Same behavior as Windows; the installer claims it is there, but Quartus does not show it. Given these cross-platform results, I suspect the root cause might be: 1) A corrupted or flawed Stratix III device installer file (.qdz). 2) A licensing restriction, where our current license might need a specific feature enabled for the Stratix III family, even though the software allows the installation. Could you please guide me on how to get this Stratix III Development Kit operational (which features the EP3SL150F1152 device)?" Thank you for your time and assistance. I look forward to your guidance. Best regards!
bsneves
5 hours ago
Configuration
Programmable Logic Device
470Views
0likes
10Comments
Global Clock & Regional clock inputs in Agilex M FPGA
Hi, Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ? Why multiple clock inputs of Global clocks and Regional clocks are provided in F-Tile of Agilex M FPGA? Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? When do we need to drive regional clock inputs ? When do I need to drive global clock inputs ? In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ? Regards, Thulasi
Solved
Thulasi
1 day ago
Core Logic
Generic Io
55Views
0likes
6Comments
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
SiddeshChavan
1 day ago
Configuration
Core Logic
Generic Io
Power
Programmable Logic Device
11Views
0likes
0Comments
Cyclone V nRST assertion upon nPOR
Hello, I am looking for a confirmation on whether the nRST pin is driven low upon a nPOR input assertion. I have found no definite answer in the HPS TRM (cv_5v4 dated 2024.12.03). But HPS TRM version 1.3 (Nov 2012), Table 3-3 page 3-7 says with I ran an experiment today on our prototype, asserting nPOR once the system has boot-up (linux) and see no assertion of nRST pin. Also, in the Reset Manager register description, I see no configuration bit that would enable/disable nRST assertion upon nPOR. Can someone confirm the unconditional assertion of nRST upon a nPOR as I understand from HPS TRM from Nov 2012. Thanks, Best regard Pascal
PRega1
3 days ago
Core Logic
25Views
0likes
1Comment