Recent Discussions
System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven from PCIE card edge. After power up, IO PLL locked but System PLL cannot be locked, PCIE hard IP remains in reset status, regardless the configuration method of FPGA (that is, via JTAG or QSPI flash). Here are my questions: 1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source. 2、If the answer of above question is positve, how should I debug to make the System PLL work? Best regards.
Bidirectional differential port on MAX10
I want to implement a bidirectional differential port on a MAX10 10M02SCU324C8G I first tried to do it on my own and then tried to do it with the GPIO Lite IP too. At the end of the day I get the same error: Error (176202): The differential I/O standard Differential 2.5-V SSTL Class I cannot be used on the pin RC_A[0], because the specified pin uses a tri-stated output buffer. Is it only possible to have either a dedicated input or output differential port? Why is it even letting me configure the IP as a bidirectional differential IO? Or am I missing something when it comes to pin configuration?
Backplane Ethernet 10GBASE-KR PHY FPGA IP
I would like to know more information about the Intel\Altera Backplane Ethernet 10GBASE-KR PHY FPGA IP . Can it be implemented in the Agilex 5 FPGA ? If not are there any plans to incorporate it there and what would be the time frame ? Also what type of license is offered. I tried the site contact :- https://www.altera.com/products/ip/po-3078/backplane-ethernet-10gbase-kr-phy-fpga-ip twice but I got no response ???
MAX10 DDR3 Timing
Hi, I need a definitive statement regarding the timing. The two attached screenshots were created with Quartus 23.1 but can also be found in 25.1. Although adjusting the temperature range reduced the number of failing paths (see screenshot 800MHz_300MHz_DDR3_1, which ran at -40°C to 100°C), there remain parts that do not meet the timing. According to the datasheet, this should work. The MAX10 being used is a 10M16DAF484I6G, which is the fastest speed grade. The memory is Micron MT41K256M16TW-107AAT. Br, Korbinian
Avalon-ST configuration with Agilex 3 fails
Hi, I have implemented a kind of passive serial programming from a CPU using SPI and a shift register. The signals nSTATUS, nCONFIG, CONF_DONE, READY, and VALID are directly controlled by GPIOs. This works well except after a power cycle. After the system has powered up, the programming fails — CONF_DONE does not go high. All retries afterward succeed. I already went through the debugging guidelines but couldn’t find an issue. However, I have observed two things: The nSTATUS pin follows exactly the timing of the nCONFIG pin during the first attempt. Normally, nSTATUS is delayed and goes high later. The CPU must finish the complete programming cycle before retrying; otherwise, the FPGA remains stuck in this erroneous state. I recorded some curves with a logic analyzer: full_timing.png: Power cycle First configuration cycle fails Retry works Another cycle also works 2_start.png: Beginning of cycle 2. Here, the nSTATUS pin follows exactly the timing of the nCONFIG pin. 2_3_restart.png: End of cycle 2 and beginning of cycle 3. 4_start.png: Another configuration cycle that works. Any idea what could cause this problem? Regards Samuel
Agilex 7I-Series Device Errata and User Guide: Why my answers are deleted all the time:
Am asking to help with obtaining [ Agilex™ 7 F-Series and I-Series ES Device Errata and User Guidelines] datasheets. But all my answers with sreenshots of other Altera/Intel documents regarding this datasheet link and document number are always deleted. Why deleted ? Terrible support ! Wasted $15K on DK-SI-AGI040FES Kit, cannot get access to errata document, got help request questions deleted from Alterra board This what was in Intel/Altera original datasheet: For Information about the Agilex & Device Errata Sheet and User Guidelines [ES-1069] and Agilex 7 Known Issues List, contact Intel Premier Support and quote ID #15011992053. Now in Altera datasheet (Agilex 7 Known Issues List) its mentioned as Agilex 7 F-Series and I-Series Device Errata and User Guide [Agilex 7 Known Issues List] PDF is public open while [Agilex 7 F-Series and I-Series Device Errata and User Guide] is NOT Need help obtaining Agilex 7 I errata !
