Recent Discussions
Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hello, Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone. The relevant link is below. Cyclone® IV Device Handbook - Chapter 5: Clock Networks and PLLs in Cyclone IV Devices - Figure 5–26. PLL Dynamic Phase Shift The reason for this is that the wait time for the phase shift to complete is required in the higher-level design. Regards
Agilex5 - Timings configuration
Hi, in document 813918, I have a question regrading method to define NOR timing, table 115, using Text_delay as conditions for input timings. this parameter is said dependant of frequency of interface (note 195), but only one value (max) is given (no min), and this one is greater than half-period and even at clock frequency 166MHz which seems to be considered by datasheet. I don't understand. Can we get simply Setup and Hold timings for Agilex inputs for AS configuration interface ? Thanks and regards
10M04SCU169I7G issue.
The Malaysian factory feedback the following material issue.Regarding the defective parts, re-balling has been performed, but the problem persists.Please help analyze, confirm, and resolve this issue. Details are attached. NSY production found 19pcs of PCBA (KNA-68010-0000-51-3MC1) with Program Altera failure which is related to the defective P/N 1060-8520 FPGA (U21). Voltage measurement on V_3V3_S5 (R60) which is associated with the affected component showed 1.5V instead of the expected 3.3V. The impedance value of the related passive component was measured & no abnormal values were found. Currently, 7pcs of the 1060-8520 FPGA (U21) have been reworked and the units passed the retest The remaining boards are currently on hold in production line and pending further disposition. Kindly advise on the next action. PN:1060-8520 MPN:10M04SCU169I7G DC：2546/2539/2549 FR:25/846 2.96%HDMI example design errors with Agilex 7
Hello, I generated the HDMI example design for the Agilex 7 devkit and it compiled and worked fine. But when I ported it to my platform and remapped it to the nwe pins, I get these errors (for evenry RX lane and every TX lane): Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Error(21843): cdr_f_out_hz == 1745000000 Error(21843): cdr_f_ref_hz == 87250000 Error(21843): is_used == TRUE Error(21843): location == UX12 Error(21843): rx_tuning_hint == RX_TUNING_HINT_DISABLED Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings Error(21843): Conflict 0 ---------------------------------------------------------------- Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_f_min_ref_limit_rule @ gdr.z1577b.u_ux_quad_3.flux_top Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_f_out_hz_rule @ gdr.z1577b.u_ux_quad_3.flux_top Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): Rule: gdrb_wrapper::topology_mapping_mux_rule @ Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): Rule: z1577b::topo_down_to_ux_and_barak_powerdown_rules @ gdr.z1577b Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): Input variables: Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Error(21843): cdr_f_out_hz == 1745000000 Error(21843): cdr_f_ref_hz == 87250000 Error(21843): is_used == TRUE Error(21843): location == UX12 Error(21843): rx_tuning_hint == RX_TUNING_HINT_DISABLED Can you please clarify what the issue is? On my new platform, I am using Bank 12A Quad 3 (TX and RX) and for reference clocks fgt_12a_refclk_ch3 and fgt_12a_refclk_ch4. Thanks
Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy
Hi, 1. The Agliex 7 F Series EMIF User Guide page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F series evaluation board DDR4 memory vendor datasheet (thisis publicly available one for the MT40A2G8VA used on above linked eval board) states RESET must be low while power rails ramp up as pictured below which implies it should be instead pulled down to ground. Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies? From above public Micron datasheet 2. Figure 143 in section 6.5.6.1 of Agilex 7 EMIF User Guide shows ADDR/CMD clock terminated to VDD through R and C network. Altera F Tile eval board has ADDR/CMD clock terminated to GND through R and C network. Can Altera explain why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation? From Eval board Thanks!
Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
Agilex 7 Decoupling capacitor scaling factor
Hi! I have got my power estimate from quartus prime based on our requirement, which is " board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , where would i get this value? is it related to FPGA part(AGFB027R24C2I2V) or the max current rating of my convertors? Thanks, Vigneswaran
Rocketboards Secure Boot Example with 5CSXFC6D6F31 instead of 5CSEBA6
I have been following the tutorial to implement the Cyclone V SoC secure boot example at https://rocketboards.org/foswiki/Projects/CycloneVSoCSecureBootExample and as attachment. I can successfully generate both the hardware and the software projects, resulting in the .jic image. However, when inserting the image I get an error due to compability issues. My question is: how can I adapt / rebuild the projects in order for them to be compatible with my board? Has anyone had the same issue? Any guideline on pointers that might be related or help me? Thanks a lot in advance.Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.