Recent Discussions
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, BrianQuartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices
Hi, Is there any power down sequence for Agilex 7 F-Series (2x F-Tile) Devices? I went through Agilex™ 7 Power Management User Guide, which lists power down sequence for Agilex 7 Devices with E-Tile & Agilex 7 M-Series Devices bit i could not find for F-Series (2x F-Tile) Devices. Thanks in-advance, Deva
Manual checksum verification of CFM0
I am working on some post-build scripting for generating firmware update programming files for the Max 10 series FPGA. My goal is to generate 2 separate files: POF file, for use with USB Blaster. Proprietary file, for use through a different communication channel. The POF file is easy; the file is basically auto-generated when you compile in Quartus. When loading the POF into the Quartus programmer software, it shows "Checksum" and "Usercode Checksum". The usercode checksum can also be found in the RPT file. So I have used my post-build scripting to make a copy of the POF file, with the usercode checksum appended to the POF filename. That is all working great and goal #1 is satisfied. I have been working on the proprietary file. In this case, I would be storing something that amounts to the raw data that will end up written to the CFM0 section of the FPGA. To get the raw data, I used quartus_cpf to generate RPD files from the compiled SOF file. The raw data can then make its way into the FPGA's CFM0 section through undisclosed means other than USB-Blaster. All of that is OK, but the problem I have is that I wish to use the SAME usercode checksum as the POF file for consistency, and I have not been able to figure out how to correctly calculate that. One thing that I did where I got close was, I added this argument to the quartus_cpf command when generating the MAP file: -o memory_map_file=on The MAP file generated shows a totally different checksum. However, when I do a simple 32-bit checksum on the RPD data (just adding all 32-bit words of the file and coming to a 32-bit result), it DOES exactly match the checksum in the MAP file. In summary: I want the consistency between one of the POF's checksums shown in Quartus Programmer, vs. what I can calculate from the raw RPD data. Since both methods of programming the FPGA should produce identical results, I want to be able to have the same checksum in both methods. How may I correctly use the RPD data to calculate the same checksum shown in Quartus programmer when loading the POF file?
Why does PTA show zero W for F-tiles in Hierarchical Design Editor
Why is there no power shown in the Hierarchical Design Editor(25.3: Current Level Dynamic Power, 26.1: Self Dynamic Power) when adding a fully utilized F-tile? The Total Power does however show the expected power. Is it a bug or a feature?
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.Agilex 5 configuration via Avalon-ST x8 issues
I have a MAX10 device controlling the configuration of an Agilex 5 device (A5EC065BB23AI4S) set for Avalon-ST x8. We use the MAX10 to translate serial programming from our processor to AvalonST x8 for the Agilex 5. I am able to program both the MAX10 and Agilex 5 device via JTAG and verify we can talk to these devices via SPI busses in the hardware. For the configuration via the MAX10 we bring nCONFIG low and nSTATUS returns from the Agilex 5 low. We next bring nCONFIG back high and nSTATUS returns to high. We start the Avalon-St transfer but never see INIT_DONE go high. The odd thing is we also never see CONF_DONE go low even with nCONFIG low? Any idea what else to check? Below is a pic of the SDM_IO connections from the Agilex5 to the MAX10.
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
writing a word to cfm1 using on chip flash ip on max10
hii i have the neek board development kit , and i am writing my own logic to perform a writing of an image to cfm1 flash sector for remote update i am transferring the image through uart from rpd file just like in nios rsu example lab . i configured the on chip flash ip in this parameters data interface :parallel read burst mode :incrementing read burst count:8 configuration mode :dual compressed images i set the burstcount to 1 I managed to erase the CFM1 sector, and I read the status register to confirm that the erase of sectors 3 and 4 was successful. Sector 3 + 4 corresponds to CFM1. Before performing the write operation, I verify that the on-chip flash is in the idle state by reading the CSR status register. I place the word on the data_writedata signal of the Avalon bus with the correct address, assert the data_write signal, and then wait until waitrequest goes low before proceeding to the next word. I confirm that the write was successful by reading the ‘write successful’ bit in the CSR status register. but sometimes in the middle of the file transfer , i get a write failure and i am not sure why , my clock on board is 50 mhz and i am using pll to generate 75mhz. so i i am feeding the 75mhz clock to the on chip flash ip and my own writing fsm logic Using SignalTap, I can see that the word before the one where the write failed was written successfully. I send each word over the UART interface with a delay of 2.5 ms, which I believe is sufficient for the write to complete. I also check the waitrequest signal before proceeding to the next word and verify that the on-chip flash is in the idle state.” I would be thankful to know why I am getting a write failure and what I should check to resolve this issue? thanks