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Error when using University Program VwF
I'm using Quartus 16.1 I want to simulate, but when I press Run functional simulation this error occur " Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (199014): Vector source file C:/Users/myusername/Desktop/veri/Waveform1.vwf specified with --testbench_vector_input_file option does not exist Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 471 megabytes Error: Processing ended: Fri Dec 30 22:56:30 2016 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error. "HPS+PCIe project(Quartus II 13.1 64 bit),compile design--Assembler error
Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Processing started: Thu Jan 09 10:46:06 2014 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off kz -c kz Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. Info (115030): Assembler is generating device programming files Error (210006): Can't save or open file D:/work/altera_pcie_hip_ast_ed/kz_cv/db/ip/pcie_de_gen1_x4_ast64_hps/submodules/sequencer/alt_types.pre.h Error: Quartus II 64-Bit Assembler was unsuccessful. 1 error, 4 warnings Error: Peak virtual memory: 706 megabytes Error: Processing ended: Thu Jan 09 10:46:25 2014 Error: Elapsed time: 00:00:19 Error: Total CPU time (on all processors): 00:00:18 Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 791 warnings screenshots： http://www.alteraforum.com.cn/attachment.aspx?attachmentid=1377 http://www.alteraforum.com.cn/attachment.aspx?attachmentid=1378 The alt_types.pre.h file is exist. Anyone any suggestions on how to solve the problem ? Thanks PS: alt_types.pre.h file; #ifndef __alt_types_h__ #define __alt_types_h__ /* * don't declare these typedefs if this file is included by assembly source. */ #ifndef alt_asm_src typedef signed char alt_8; typedef unsigned char alt_u8; typedef signed short alt_16; typedef unsigned short alt_u16; typedef signed long alt_32; typedef unsigned long alt_u32; typedef long long alt_64; typedef unsigned long long alt_u64; #endif #define alt_inline __inline__ #define alt_always_inline __attribute__ ((always_inline)) #define alt_weak __attribute__((weak)) #endif /* __alt_types_h__ */Cyclone 3 E144 package getting hot and Cannot program the Cyclone using EPSC4 Chip
Thanks in advance, for any help you guys can provide . I'm trying to configure a Cyclone 3 (EP3C5E144) device using AS configuration mode. I'm currently using the EPCS4 chip for the AS mode configuration. For some reason, after powering up the Cyclone and EPCS4 chip for bit, the Cyclone starts to heat up. I've checked my voltages for 3.3, 2.5 and 1.2 V for VCCIO, VCCA, and VCCINT, respectively. Those voltages goes to the right pin on the chip itself. I've used the AS mode circuit that was proposed by the Cyclone 3 handbook and connected MSEL[2..0] to '010', 0 being ground and 1 being VCCA (2.5V). I'm a bit puzzled on whether I should use JTAG mode in the Quartus II Programmer or should I use AS mode. By the way, this is for my own prototype board. I've bought a Cyclone 3 Development board from Terasic and I have to select JTAG mode in Quartus programmer and convert my .SOF files into .JIC files to program the Cyclone on the development board. When I try to do the same technique with my prototype board, it stated that " Can't access JTAG chain". Then I had to convert my .SOF file into a .POF file and select Active Serial Programming (AS) mode to configure my EPSC4 chip. The programmer had shown to be able to program my EPCS4 chip completely. But I'm not getting any response from my Cyclone 3 device. I've checked all the pins on the EPCS4 chip and it doesn't seem to be active. I've checked my prototype many times to make sure the connections between the Cyclone 3 and EPCS4 chip is good and it is. I've actually have a second person check it multiple times too, before powering it. After having my prototype on for less than a minute it starts to become warm and eventually hot, I've added a solid ground plane for the ground slot on the bottom of the Cyclone 3 chip (package EP3C5E144). I used a different chip and added the ground to it, that helped with the heat issue for a while. Then when I try to program it the same way I did before, it just started to heat up again. Have anyone ever encountered this same issue? If you do please help me as I'm currently new to FPGA development. I've used the exact circuit in the Altera Cyclone 3 Handbook, Figure 9-7. In-System Programming of Serial Configuration Devices. I've added the protection Schottky Diodes and Capacitors as well. Please let me know if you have any further information or question. Thank YouMax 10 RSU (Remote System Update) - Dual Images - Write to CFM
I am looking to test the remote update feature of the Max 10 using the Max 10 Development Board. I want to be able to perform a Remote System Update (RSU) using the Discrete Update method. I have worked through the RSU example using the Nios II processor (AN741: Remote System Upgrade for Max 10 FPGA Devices over UART with the Nios II Processor), however for the situation I need to perform remote updates in the Nios II method is not an option. I have been able to succesfully program the device with dual images. For this I have used a simple Platform Designer system (clk, flash, dual_boot IP) to generate HDL files which I have included in a top level HDL file for the project. Next, I intend to test the "fail safe" capability of the Max 10 by corrupting one of the images (image 1), attempting to boot into that image, and checking that the device falls back in to image 0. To do this I need to be able to write directly to the CFM on the device. I have been unable to find a method of easily writing in to the CFM. Is this even possible or can the CFM only be written to/read from using the Remote Update circuitry on the device? Are there any examples online of a Discrete RSU system on the Max 10? Any help would be much appreciated. Cheers
Licensing error in simulation. How can I fix it?
I'm trying to run a functional simulation on Quartus Prime Lite, but I get this error: Unable to checkout a license. Vsim is closing. ** Fatal: Invalid license environment. Application closing. Unable to checkout a license. Make sure your license file environment variables are set correctly and then run 'lmutil lmdiag' to diagnose the problem. Modelsim - Intel FPGA Edition uses the following environment variables to check the licenses (listed in the order of preference) 1. MGLS_LICENSE_FILE 2. LM_LICENSE_FILE. I just want to use Quartus to run some simulations.