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Arria 10 GX Remote Update Circuitry
Hello, We are using an 10AX066 FPGA connected to an MT25QU01 flash. It's connected through Active Serial. We are looking to use a system setup that will allow us to boot into a user image, before falling back to a factory image if it fails to configure 3 times, we do not need a watchdog, or the AnF bits. Is the default behaviour of the Arria 10 device to provide the features provided in this flow chat (https://www.intel.com/content/www/us/en/docs/programmable/683461/current/configuration-sequence-in-the-remote.html)? Is the Remote Update IP core necessary for any functions that we want?
Recon Engage - Download GPX files
Good morning everybody, I've seen that Recon Engage was acquired by and cancelled by Intel sometime these past years. I've also seen that the back-end servers are still running. I have recorded many activities using the Recon Snow2 goggles, and I'm hoping I could still download or receive the GPX files from those activities. Is there anybody who can help me out with that? Thanks in advance for your help! Kindest regards, Sander
Why do the A/D's on MAX10 need blank pins around them? Unable to use.
I have a 10M08SA design that is about 80% full. Board level power supplies are being measured by the FPGA's ADC's. However, when I compile the design, synthesis fails and the indication is that almost all the pins that are in use need be ununsed. This is quite bad. I understand the analog design considerations, but it appears that the ADC's are rather weak in terms of their applicable use.
not able to detect any instance for core < hps_sdram_p0 >
Hi, I'm trying to get into a Cyclone V based evaluation board (EBV SoCrates). While already getting LEDs to blink, on pure FPGA side, now I wanted to do a setup with QSYS. I took the "default clock", a "hard processor system" and created a "custom" component to combine it with one of my vhdl files. Another VHDL file is not in the QSYS setup. I compiled the QSYS and I integrated the resulting .qip into the project, together with the other .vhdl file. Finally, I adjusted the toplevel VHDL file, but there seems to be something missing. After setting the LED pins and one clock pin (the same I used before). At compilation then, I get the following: --- Quote Start --- Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/altera_reset_controller.sdc' Info (332104): Reading SDC File: 'soc_system/synthesis/submodules/hps_sdram_p0.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 > Error: Verify the following: Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper) Error: The core is not the top-level of the project Error: The memory interface pins are exported to the top-level of the project --- Quote End --- What is wrong here? What is meant by "hps_sdram_p0", I did not write a component by this name - where can I look this up? I tried to verify the items, but I'm completely unsure. How can I check if hps_sdram_p0 is instantiated within another component? The .qip (supposed it is meant by "core"), is definitely not the toplevel. I assume the "memory interface pins" as main cause, since I did not set anything here. But - which memory inteface pins, do I need? Where to look up what is required, in order to check its address in the processor's datasheet??!Modelsim compiling error:(vcom-11) Could not find work.stratixiv_hssi_components
hey,everyone! I am doing simulation with modelsim.When compiling the libraries before runing the do file, i am confused of the error below:# ** Error: (vcom-11) Could not find work.stratixiv_hssi_components.# ** Error: ./altera/stratixiv_hssi_atoms.vhd(112): (vcom-1195) Cannot find expanded name "work.stratixiv_hssi_components".# ** Error: ./altera/stratixiv_hssi_atoms.vhd(112): Unknown expanded name.# ** Error: ./altera/stratixiv_hssi_atoms.vhd(114): VHDL Compiler exiting# ** Error: D:/EDA_Tools/modeltech_6.5e/win32/vcom failed. But in fact i have do the tcl script of compiling stratixiv_hssi_components.vhd.Could anybody knows why?Thank you very much! Here is my tcl script: if ![file isdirectory verilog_libs] { file mkdir vhdl_libs set vhdl_dir "./altera" vlib vhdl_libs/altera_V vmap altera ./vhdl_libs/altera_V vcom -93 -work altera $vhdl_dir/altera_primitives_components.vhd vcom -93 -work altera $vhdl_dir/altera_primitives.vhd vlib vhdl_libs/lpm_V vmap lpm ./vhdl_libs/lpm_V vcom -93 -work lpm $vhdl_dir/220pack.vhd vcom -93 -work lpm $vhdl_dir/220model.vhd vlib vhdl_libs/sgate_V vmap sgate ./vhdl_libs/sgate_V vcom -93 -work sgate $vhdl_dir/sgate_pack.vhd vcom -93 -work sgate $vhdl_dir/sgate.vhd vlib vhdl_libs/altera_mf_V vmap altera_mf ./vhdl_libs/altera_mf_V vcom -93 -work altera_mf $vhdl_dir/altera_mf_components.vhd vcom -93 -work altera_mf $vhdl_dir/altera_mf.vhd vlib vhdl_libs/stratixiv_V vmap stratixiv ./vhdl_libs/stratixiv_V vcom -93 -work stratixiv $vhdl_dir/stratixiv_atoms.vhd vcom -93 -work stratixiv $vhdl_dir/stratixiv_hssi_atoms.vhd vlib vhdl_libs/stratixiv_components_V vmap stratixiv_components ./vhdl_libs/stratixiv_components_V vcom -93 -work stratixiv_components $vhdl_dir/stratixiv_components.vhd vcom -93 -work stratixiv_components $vhdl_dir/stratixiv_hssi_components.vhd
