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Steve-Mowbray-ENL's avatar
Steve-Mowbray-ENL
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Hi

In passive serial configuration the Linux platform powers on and is booted with FPGA in unconfigured state -- our RBF file is then configured via passive serial and working but is not detected as a PCIe connected device in Linux -- the command "echo 1 > /sys/bus/pci/rescan" has no effect...

Is there a user guide or instructions anywhere as to how to establish the PCIe connection in Linux after passive serial configuration

Thanks

Steve

Configuration
  • Wincent_Altera's avatar
    Wincent_Altera
    12 months ago

    Hi Steve,

    Thanks for your confirmation, I will transition this support thread to community.
    I saw corestar have reply some workaround, perhaps you may refer to that and see if that able to help you or not.

    Any time in future, if you having any problem, you may file a new thread.
    Someone will be there to support you. If you need my support on PCIe IP, please mention my name "Wincent" so that this will route to my support Q.

    If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

    Regards,

    Wincent_Altera

    p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.

28 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    May I know which Device that you are using for this ?

    Also, are you using any PCIe design example ?


    Regards,

    Wincent


    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Wincent

      Arria 10 (10AX066H4F34E3SG) and not using a design example but system is working fine in active serial mode but we are planning on using passive serial mode in product deployment

      Thanks

      Steve

    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Wincent

      I dont see any Linux guidance related to the above link -- specifically it is the Linux steps required to get the PCIe endpoint correctly detected in the Linux PCIe master device after passive serial configuration that we need

      Regards

      Steve

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        2 years ago

        Hi Steve,

        I am supporting PCIe IP area, based on your reply.
        I believe you try to convert the Programming Files RBF into passive serial configuration in order to run the design , am I get this right ?
        This is out of my support area actually, however I can try my best to assist

        In order to successful run the passive serial file please check below guide
        https://cdrdv2-public.intel.com/705024/ug-qpp-programmer-19-3-683039-705024.pdf

        1. Can you try to use JTAG mode and see if it can be configure successfully?

        2. If in JTAG mode it can be configure successfully, it can be something is wrong with the connection on board or flash. Do you follow the pin connection guidelines? https://www.intel.com/content/www/us/en/docs/programmable/683814/current/intel-arria-10-gx-gt-and-sx-device-family.html

        3. How is the MSEL setting?


        Hope my suggestion able to help you to move a step forward, Please accept my apology that this is out of my support area.
        IF your issue is still unable to solve, I suggest to file a new forum thread with title example "Arria 10: Passive Serial Configuration-programming failure" . So that our configuration team support specialist is able to look at this.

        Let me know if you have different thoughts.

        Regards,
        Wincent

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,
    in my view it's unwanted to get the FPGA reconfigured unconditionally during PC reboot. This should only happen on power-on reset or explicite request. I can confirm that evaluation boards like Terasic Arria TR10a-HL are keeping FPGA configuration during PC reboot.

    This allows to check if the initial PCIe device enumeration works with your design.

    You previously mentioned you are not sure if NCONFIG is triggered in your hardware during reboot, but it should be easy to find out, e.g. by loading a test configuration over JTAG.

    Does the remove/configure/rescan sequence work for your with other configuarion methods, e.g. JTAG or AS?

    Regards
    Frank

    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Frank

      • "Does the remove/configure/rescan sequence work for your with other configuration methods, e.g. JTAG or AS?"
        • yes when we do an AS build and load the FPGA flash device with resulting JIC and also change the MSEL pins the FPGA PCIe device is enumerated and we can remove/rescan at will -- we can also change the MSEL pins while still running then do a passive serial write of our passive serial build RBF and remove/reset/rescan the PCIe devices into a working condition -- but what we want is power on in PS mode and do the FPGA configuration that way

      you mention the Terasic Arria TR10a-HL -- does that run with PC Linux and if so what is the sequence to rescan the PCI device when the FPGA is configured?

      Regards

      Steve

  • corestar's avatar
    corestar
    Icon for Contributor rankContributor
    12 months ago

    Hello @Steve-Mowbray-ENL ,

    I had the exact same problem. On a Raspberry Pi CM4, the solution outlined in the following link works by PeartreeStudios:

    PCIe Hot Swap

    The "rescan" idea does not work as you discovered. I have two scripts.

    bind_pci contains:

    echo "Bind PCIe Driver"
    sudo bash -c 'echo fd500000.pcie > /sys/bus/platform/drivers/brcm-pcie/bind'

    and unbind_pci contains:

    echo "Unbind PCIe Driver"
    sudo bash -c 'echo fd500000.pcie > /sys/bus/platform/drivers/brcm-pcie/unbind'

    These are clearly system dependent. But each time I update the FPGA firmware:

    1. Run unbind_pci if it was already bound
    2. Update the firmware via PS or JTAG
    3. Run bind_pci.
  • Scarletios's avatar
    Scarletios
    Icon for New Contributor rankNew Contributor
    11 months ago

    <p>It seems the FPGA isn't being detected as a PCIe device after passive serial configuration. To resolve this, ensure the correct PCIe drivers are installed and verify the device tree setup if using embedded Linux. You might also want to manually trigger a rescan and check the FPGA vendor's documentation for specific instructions on setting up PCIe detection. If the issue persists, contacting the FPGA manufacturer's support could provide further guidance.</p>