Forum Discussion
Occasional ContributorFPGA passive serial configuration -- detect as PCIe device in Linux after configuration
Hi Steve,
Thanks for your confirmation, I will transition this support thread to community.
I saw corestar have reply some workaround, perhaps you may refer to that and see if that able to help you or not.
Any time in future, if you having any problem, you may file a new thread.
Someone will be there to support you. If you need my support on PCIe IP, please mention my name "Wincent" so that this will route to my support Q.If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.
Regards,
Wincent_Altera
p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.
Regular ContributorHi Steve,
For Passive serial configuration overall, you can refer to below link for the guide
Hope that able to help you to move forward, let me know if there is any further clarification is needed.
Regards,
Wincent
Occasional ContributorHi Wincent
I dont see any Linux guidance related to the above link -- specifically it is the Linux steps required to get the PCIe endpoint correctly detected in the Linux PCIe master device after passive serial configuration that we need
Regards
Steve
- Wincent_Altera
Hi Steve,
I am supporting PCIe IP area, based on your reply.
I believe you try to convert the Programming Files RBF into passive serial configuration in order to run the design , am I get this right ?
This is out of my support area actually, however I can try my best to assist
In order to successful run the passive serial file please check below guide
https://cdrdv2-public.intel.com/705024/ug-qpp-programmer-19-3-683039-705024.pdf- Can you try to use JTAG mode and see if it can be configure successfully?
If in JTAG mode it can be configure successfully, it can be something is wrong with the connection on board or flash. Do you follow the pin connection guidelines? https://www.intel.com/content/www/us/en/docs/programmable/683814/current/intel-arria-10-gx-gt-and-sx-device-family.html
- How is the MSEL setting?
Hope my suggestion able to help you to move a step forward, Please accept my apology that this is out of my support area.
IF your issue is still unable to solve, I suggest to file a new forum thread with title example "Arria 10: Passive Serial Configuration-programming failure" . So that our configuration team support specialist is able to look at this.
Let me know if you have different thoughts.
Regards,
Wincent
FvMSuper Contributor
Hi,
not sure if the observed problem is failed configuration or only missing PCIe device enumeration by PC Bios. In the latter case, the problem may be simply too late configuration. Depending on Bios behaviour, rescan doesn't necessarily help, a reboot may be necessary.- Wincent_Altera
Thanks @FvM , for your help.
Hi Steve,
Do you try to reboot the system and see if the PCIe is able to enumerate ?
Regards,Wincent
- Steve-Mowbray-ENL
Hi Wincent -- reboot doesn't appear to force Linux to recognise the FPGA PCIe endpoint but there is the suspicion that the reboot causes the GPIO line tied to NCONFIG to go low...
Regards
Steve
- Steve-Mowbray-ENL
Hi Wincent -- passive serial programming seems to be working fine as indicated by other non PCIe behaviour is fully functional -- problem is specifically the FPGA endpoint is not recognised in the Linux system after programming and a PCIe rescan doesnt work
Regards
Steve
- Wincent_Altera
Hi Steve,
Since the Intel FPGA stores its configuration data in SRAM memory, and the PCIe HIP is part of the configuration that needs to happen, this gets configured each time the system boots up, or if a full reconfiguration happens. The Arria 10 handbook (link) briefly describes the configuration sequence and how to trigger a reconfiguration, in specific the configuration step is the one in which the data is written to the FPGA, however it does not explicitly mention what happen to the PCIe HIP block. The Configuring Altera FPGAs doc (link) describes in more detail the configuration and the reconfiguration process.
- Can you please check and ensure that those is been followed ?
As far as I know, At the time the FPGA will be configured via PS, but that needs about 12 secs. To speed up, you may want to change the initialization to CvP. Still the minimal configuration to start the CvP will be done via PS and afterwards just to load the application via PCIe.
- Could you give some time more than 12 secs and see if the system is able to enumerate due to late configuration of FPGA via PS ?
IF those still unable to solve your problem, I suspect to look it can be something is wrong with the connection on board or flash. Do you follow the pin connection guidelines? https://www.intel.com/content/www/us/en/docs/programmable/683814/current/intel-arria-10-gx-gt-and-sx-device-family.html . IF the design didn’t have the PCIe component that it is expected you are not seeing the FPGA as end point.
- Did you see the conf_done asserted high in the fail scenario ?
Looking forward to hear back from you.
Regards,Wincent
