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Re: Power Rating Required for RZQ Resistor on Cyclone V SE
Hi, different FPGA families have calibration blocks with different properties. Cyclone 10 LP e.g. has separate Rup/Rdn and specifies that the applied voltage during calibration can be up to VCCIO (90 mW/100 ohm at highest VCCIO of 3V). But calibration completes in about 100 us, considering chip resistor time constant > 1 ms, there will be a huge power margin even for small 63 mW 0402. Cyclone V may apply lower maximal voltage to RZQ, but if not, I don't expect problems.6Views0likes1CommentRe: intel_onchip_Memory II RAM: r/w doesn t work from FPGA but from HPS
Hi Linus, reported results suggest that RAM control signals don't implement required write sequence. Unfortunately relevant details are hidden in posted Verilog code. E.g. no clock sensitive always statement is shown. It's also not clear how xxx_reg output connects to RAM interface. Seeing complete code would allow to understand the problem. Regard Frank45Views0likes1CommentRe: ALT PLL GUI MESSDED UP ON INVOCATION
Hi Barry, unlike altera_pll (e.g. used for Cyclone V) altpll IP doesn't accept MHz values. You can however add arbitrary integer multiply_by and divide_by values, e.g. assuming 1 MHz reference frequency. They are automatically converted to appropriate PLL parameters. Also input frequency should be specified in ps. module vpll_min ( inclk0, c0, c1, c2, c3); input inclk0; output c0; output c1; output c2; output c3; wire [4:0] clk; assign c0 = clk[0]; assign c1 = clk[1]; assign c2 = clk[2]; assign c3 = clk[3]; altpll altpll_component ( .areset (1'b0), .inclk ({1'b0, inclk0}), .locked (), .clk (clk)); defparam altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 25, altpll_component.clk0_multiply_by = 100, altpll_component.clk1_divide_by = 25, altpll_component.clk1_multiply_by = 5, altpll_component.clk2_divide_by = 25, altpll_component.clk2_multiply_by = 50, altpll_component.clk3_divide_by = 25, altpll_component.clk3_multiply_by = 125, altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 40000, altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", altpll_component.self_reset_on_loss_lock = "OFF", altpll_component.width_clock = 5; endmodule Regards Frank1View0likes1CommentRe: ALT PLL GUI MESSDED UP ON INVOCATION
Hi, VHDL example, inclock 16 MHz, outclock 50 MHz library ieee; use ieee.std_logic_1164.all; entity plltest_min is port ( inclk0 : in std_logic := '0'; c0 : out std_logic ); END plltest_min; architecture inst of plltest_min is component altpll generic ( bandwidth_type : string; clk0_divide_by : natural; clk0_duty_cycle : natural; clk0_multiply_by : natural; clk0_phase_shift : string; inclk0_input_frequency : natural; operation_mode : string; pll_type : string; compensate_clock : string := "CLK0"; self_reset_on_loss_lock : string ); port ( inclk : in std_logic_vector (0 downto 0) := (others => '0'); areset : in std_logic := '0'; clk : out std_logic_vector (0 downto 0); locked : out std_logic ); end component; begin mypll : altpll generic map ( bandwidth_type => "AUTO", clk0_divide_by => 16, clk0_duty_cycle => 50, clk0_multiply_by => 50, clk0_phase_shift => "0", inclk0_input_frequency => 62500, -- 16 MHz operation_mode => "NORMAL", pll_type => "AUTO", self_reset_on_loss_lock => "ON" ) port map ( inclk(0) => inclk0, clk(0) => c0 ); end inst; Verilog example module vpll_min ( inclk0, c0); input inclk0; output c0; wire [4:0] clk; assign c0 = clk[0]; altpll altpll_component ( .areset (1'b0), .inclk ({1'b0, inclk0}), .locked (), .clk (clk)); defparam altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 16, altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 50, altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 62500, altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", altpll_component.self_reset_on_loss_lock = "OFF", altpll_component.width_clock = 5; endmodule Regards Frank0Views1like3CommentsRe: questasim unable to checkout a license
Hi, old forum contributions moved to Altera web site. You can search thread title to find it, e.g. Questa 2021.1, Fatal License Error: Unable to checkout a viewer license | Altera Community There are however many recent discussions helping with Questa license issues.7Views0likes0CommentsRe: ALT PLL GUI MESSDED UP ON INVOCATION
Hi, I can confirm that the corrupted display occurs with altpll (Cyclone IV and 10 LP), not altera_pll (Cyclone V) Megawizard in recent Quartus 25.1 std. Previous 24.1 std is o.k. You can basically use any Quartus version with full MAX10 support, e.g. starting with 19.1. Regards Frank52Views0likes1Comment