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Re: Feasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LP
Hi Huang, I implemented soft CDR in Cyclone 10 LP utilizing PLL dynamic phase shift (requires 1 PLL output per RX channel). I'm effectively using SDR sampling of input data stream, the other RX clock edge is used to detect and track data edge. According to design requirements, I didn't go above 250 MHz but 350 MHz should basically work. Unfortunately I can't share implementation details. Regards FrankRe: System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi, PCIe reference clock is spread spectrum modulated on most system boards, this may cause locking issues. PCIe IP core PLL should have bandwidth settings that tolerate spread spectrum clocking, but system PLL probably has not. To check if the issue is related to spread spectrum clocking, you can disable it in BIOS setup. Regards FrankRe: Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
Hi, Agilex 5 065B SoM has fixed 1.2 V supplied to Bank 2A. The same power supply rail is also supplying other 1.2 V loads and can't be changed on the module. Original LVDS spec (TIA 644, IEEE Std 1596.3) have rather tight Vocm spec of 1.25 V +/- 10% (1.125 to 1.375 V). It's not achieved by TDS 1.3V IO-standard with Vocm range of 0.9 to 1.1 V. To meet LVDS Vocm spec strictly in a 1.2 V supplied bank, you'd need a resistor network with external voltage offset. Most LVDS receivers have however much wider Vicm range than required by the standard, respectively they can tolerate deviating driver Vocm. Possible range also depends on data rates, see as an example Cyclone 10 GX LVDS receiver spec. I'm quite sure that TDS 1.3 V IO-standard won't fail if the bank is actually supplied, Vocm will be respectively lower but still accepted by most LVDS receivers. If it's an acceptable solution for your project depends on many prerequisites that we don't know. Regards FrankRe: Floating point operation on Cyclone 10 GX
Hi, I believe specification of Multiply Accumulation operation in IP user guide is quite clear Out(t) = [Ay(t) * Az(t)] + Out (t-1) But it's essentially a question of hardware features. Description of DSP block architecture in Device Handbook clarifies that FP adder output is a 32-bit word, no features to recirculate a result with higher resolution as required by FMA. Regards FrankRe: Warning at Standard 25.1 by Arria 10
Hi, I read the warning so that 25.1 Std. or possibly a succeeding 25.x Std. version is the latest Quartus Standard version supporting Arria 10 series. This has nothing to do with 25.3.1 Pro, a special update for Agilex FPGA. It has been also recently announced that separate Quartus Std. development will be dropped in the future, but without a schedule yet. Personally I'm not sure if we'll see a 26 Std. version at all. Thoughts of a Quartus user. Regards FrankRe: QSPI DDR Interface with Cyclone10LP: Maximum frequency
Hi, I'd expect that single-ended IO, e.g. 1.8V standard can basically work for the interface. Maximum IO speed on the pin level is mainly limited by capacitive load and driver current strength. Achieving timing closure for DDR RX and TX is the other point. You don't only care for maximal pin toggle rate of a specific IO standard but also for delay skew from slowest to fastest pin timing over process and temperature variations, which narrows the sample window. Respectively setup- and hold margin may be more critical than simple clock speed. Mentioned 166 MHz speed is only achieved in FlexSPI mode 3 with DQS RX strobe, it has to be provided by your interface design. DDIO registers should be used. I don't know if 166 MHz can be reliably achieved, something like 100 MHz should hopefully work. B.t.w., I'm also planning QSPI DDR interface for a similar chip, but without DQS because it's occupied by other usage in my application. Regards FrankRe: Questa Not Accepting My License
Hi, I agree that things are a bit complicated since Altera switched to QuestaSim Altera Starter Edition a few years ago. But it's clearly stated in installation instructions that Questa uses a separate license file indicated by the SALT_LICENSE_SERVER environment variable. License files are readable text, a Questa license should contain a feature "intelqsimstarter". A free QuestaSim ASE license can be obtained from Self Service Licensing Center if you don't already have it. Currently the SSLC license generator seems to have issues, hopefully fixed soon. Regards Frank
