ContributionsMost RecentMost LikesSolutionsRe: Is it possible to attach PCIe to a Dev kit? Hi Mads, DE25 Nano uses AE5EB device variant which has no transceivers. Thus no PCIe interface available. Regards Frank Re: Dedicated Clock Pins for MAX 10 Hi Martin, Pin Planner info is correct. Please compare with your previous post that confuses in- and outputs. Only difference is wheter PIN_L1 (outclk_n) can be alternatively used as single ended dedicated clock output. According to Quartus compilation result it can. Regards Frank Re: Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1 Hi jAlter, you are right, I forgot about the new Legacy Download Center. Thanks for correcting me. Regards Frank Re: Dedicated Clock Pins for MAX 10 Hi Martin, "Pins J4, J5, K4, and K5 can be used as PLL OUTPUTs. Pin P2 can be used as a PLL INPUT." No and no, it's the other way around. As I mentioned, PIN_N1 is the other dedicated PLL output of 10M02SC153. If you are not obliged to achieve lowest jitter and skew, you can route PLL output to any IO pin and also use other dedicated clock inputs not directly routed to PLL1, e.g. CLK[2,3][p,n]. Regards Frank Re: Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1 Hi, as you guess, you need a subscription license to generate Cyclone code with Quartus 13.0.1. Latest web edition supporting Cyclone is Quartus 11.0.1, but it's no longer available for download at Altera. Most developers maintaining Cyclone code have older Quartus versions archived. Quartus 11.0.1 also available at archive.org: https://archive.org/download/11.0sp-1-quartus-free-windows/11.0sp1_quartus_free_windows.exe Regards Frank Re: Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1 Hi, Cyclone .sof generation works for me with 13.0.1 SP1 Full Version (Build 232 06/12/2013). Tested with EP1C12Q240. You should see an error message indicating why no .sof is generated. What is it? Regards Frank Re: Dedicated Clock Pins for MAX 10 Hi Martin, you are correct. PIN_N1 can be additionally used as single ended clock output. CLK[6,7] pins mentioned in my previous post aren't available for 10M02. Regards Frank Re: Dedicated Clock Pins for MAX 10 Hi Martin, your questions are basically answered in MAX10 Device Handbook and Pinout documents. Your device has only PLL1 (left side) and one pair of dedicated clockout pins. Dedicated input pins for PLL1 are CLK[0,1][p,n] and CLK[6,7][p,n], but not CLK2p pin J12 selected in your design. Also pin K4 is no dedicated clockout pin. Depending on your application, non-dedicated clock routing warnings can be possibly ignored. Regards Frank Re: Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference) Cyclone 10 GX, Arria 10 and Agilex have specific requirements for power rail sequencing, partly including power-down sequence specifications. Active discharge can be required to fulfill it. I feel that respective device handbooks give detailed reasoning which parameters should be implemented. Can you tell which DE10 board schematic are you quoting? Regards Frank Re: The entire ALTPLL configuration interface is glitching. Anyone know how to fix this? Hi Martin, known bug, see ALT PLL GUI MESSDED UP ON INVOCATION | Altera Community - 337656 Need to install a Patch for 25.1 Std. Regards Frank