User Profile

FvM

Super Contributor

Joined 3 years ago

1412 Posts214 LikesLikes received162 Solutions

View All Badges

User Widgets

Contributions

Re: Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?
Hi Barry, according to TSE IP User Guide, tx_clk has to be send to RGMII PHY and TSE IP by your design. A programmable clock divider is required to support 10 and 100 MBit mode. Regards Frank
1 day ago Place IP & Transceiver
6Views
0likes
0Comments
Re: Correct way to configure the RGMII input and output pins on a MAX10 FPGA
Hi Barry, not sure why you're instantiating dedicated DDR IO. TSE IP in RGMII mode already interfaces to DDR RX and TX data. Regards Frank
1 day ago Place IP & Transceiver
7Views
0likes
0Comments
Re: Correct way to configure the RGMII input and output pins on a MAX10 FPGA
Hi Barry, not sure why you're instantiating dedicated DDR IO. TSE IP in RGMII mode already interfaces to DDR RX and TX data. Regards Frank
1 day ago Place IP & Transceiver
4Views
0likes
0Comments
Re: Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?
Hi Barry, according to TSE IP User Guide, interface between FPGA and RGMII PHY looks like this means 5/25/125 MHz clock has to be generated in your design. That's valid for all PHY with RGMII interface, not specifically Marvell 88E1111. Regards Frank
1 day ago Place IP & Transceiver
4Views
0likes
0Comments
Re: USB Blaster not available
Hi Terry, that looks good. Unless you don't install manually, jtagserver of last installed Quartus version will be used. However if you have Quartus Std and Pro versions on your computer, you'll use Quartus Pro jtagserver because Quartus Std. server won't recognize some advanced FPGA. Regards Frank
3 days ago Place FPGA Device
10Views
0likes
3Comments
Re: How to set initial register values after powerup
Hi, possible reason for an external reset input are - power managment (e.g. power supply sequencer) signals good state of all power rails - external cold start (reset button, reset signal provided by a system controller) is wanted Both external and internal generated reset should be released synchronous to respective clock, in case of doubt you want a synchronous reset line for each clock domain involving state machines or other register content that may be corrupted by asynchronous reset. Regards Frank
3 days ago Place FPGA Device
8Views
0likes
0Comments
Re: USB Blaster not available
Hi Terry, same driver versions work for me both with Windows 10 and Windows 11. There's apparently another factor but I don't know what it is. Is Quartus using 24.1 JTAG server? jtagserver --status jtagconfig --serverinfo Regards Frank
3 days ago Place FPGA Device
17Views
0likes
1Comment
Re: How to set initial register values after powerup
Hi, internal register POR state is generally inferred from initialization statements. While std_logic entities have a default initial value of 'U' in simulation, the default initial value of synthesized signals and variables is '0'. It can be overridden by an explicite initial value in declaration. Besides initial value, POR can be also set by a reset statement. If reset value is different from initial value you get a synthesis warning that initial value is ignored. Regards Frank P.S. Automatic POR and external reset signal don't necessarily cause consistent design state because they are asynchronous to design clock. They can cause unexpected initial counter or even illegal FSM states. Synchronous reset release avoids this problem and should be coded in HDL if no respective IP is available. It must be used with explicite reset statement for respective signals.
3 days ago Place FPGA Device
19Views
1like
0Comments
Re: NOR Flash IC programming using 3rd party Programmer
Hi, why no reading back jic programmed flash in your programmer and compare the content? May be trivial bit order problem. Writing binary image files to altasmi IP needs a bitrevers conversion, I guess it's also required for your programmer. Regards Frank
3 days ago Place FPGA Device
7Views
0likes
0Comments
Re: USB Blaster not available
Hi Terry, what's rabbit USB driver version? (Device control manager >>> driver details) P.S. Are they using a customized or original FTDI low level driver? Sure it can't be replaced by recent FTDI driver?
5 days ago Place FPGA Device
28Views
0likes
1Comment