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Re: Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hi, checked phasedone timing in real hardware with MAX10, PLL block is basically identical to Cyclone III/IV and 10. See pulsewidth of phasedone varying with fvco/fscanclk ratio. Between 0.65*tscanclk for ratio 24 (fscanclk=50 MHz, fvco=1200 MHz) and up to 1.6*tscanclk for ratio 3 (fscanclk = 100 MHz, fvco=300 MHz). 300 MHz is beyond specification but still locking. Means step rate of 1/4 fscanclk can be always safely achieved. Even step rate of 1/3 fscanclk works with phasedone pulse > 1*tscanclk. Apparently the requirement to await phasedone rising edge before setting phasestep isn't strict. Phasedone rising edge shows a certain jitter against scanclk, showing that it's actually asynchronous, timed by vco. Regards FrankRe: Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hi, thanks to Aqid for linking Knowledge base articles about phasedone timing. It addresses the problem why some dynamic phaseshift controllers take more time per step than probably possible, also some of my previous implementations. If you process asynchronous phasedone in a scanclock driven state machine, you need to add synchronization logic to avoid timing violations and possible metastable states. On the other hand, according to user manual, a phase step pulse of two scanclock periods, typically starting and ending at scanclk rising edge, seems sufficient to trigger a step. I also don't see cases in real hardware where phasedone is longer than one scanclk cycle, although user manual and application notes suggest it can be the case. PLL simulation model sends phasedone of fixed 0.5 scanclk period, possibly a simplification that can't be take as a prove of hardware behaviour. But you have always a large factor between vco and scanclk frequency, maximum 100 MHz scanclk and minimum 600 MHz vco in case of Cyclone devices. Even if you utilize lower vco frequency values apparently supported by hardware (down to about 320 MHz), phasedone seems to finish within 1 scanclk period. Thus above stated sequence of one phase step per 3 scanclk cycles should work unconditionally. If you are not completely sure, you can wait another scanclk cycle, still without reading phasedone. Regards FrankRe: Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hi, I can't answer the question officially. I see in simulation, that for the given parameters (fvco = 21*inclk0, scanclk = inclk0), a phase step can be performed every 3 scanclk cycles. I'm not waiting for phasedone = 0 but setting phasestep for two scanclk cycles. Regards FrankRe: LVDS support on Agilex 7
Hi Vigneswaran, I think, you don't need additional margin for datasheet specifications of maximal Vicm and Vid. We can assume that the specificatons are well considered. Possible exeedance during power on should be however avoided. I'd assume that unterminated LVDS driver can have a least doubled voltage swing, worst case up to supply rails. If this is critical, you should use external instead of programmed internal termination. Regarding ZL30733 usage on Altera Development Kits, I can't determine if it keeps maximum Agilex 7 ratings, I don't have a device datasheet. According to product brief, output Vocm is programmable and has factory configurable power-on configuration. So it might use safe parameters. Said device kit is however using VDD of 1.2V for GPIO banks containing respective TDS clock inputs, thus limits are lower than discussed for 1.5V TDS. Regards FrankRe: LVDS support on Agilex 7
Hi Vigneswaran, regarding Si5391 interfacing with TDS 1.5 I/O standard, I think that VDD of 1.8 V (sub-LVDS with Vocm of 0.9 V) will better fit Agilex 5. As for power supply requirements, they strongly depend on clock frequency and switching activity. Therefore Quartus final power estimation is performed for a synthesiszed design. Regards FrankRe: Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hi, Dynamic Phase Shifting paragraph in Cyclone IV device handbook explains that step timing is set by a combination of Scanclk and VCO frequency. Respectively there's no simple phase step duration specification. In a specific implementation, we are seeing about 10 scanclk cycles required for a phase step. Regards FrankRe: Max10 FPGA Programming with .pof file
Hi, did you try to reduce JTAG frequency of USB Blaster II in Programmer Hardware Setup? If this doesn't help, there may be a problem of TCK signal quality with your PCB design, causing crosstalk of other clock signals or ringing TCK edges. A small capacitive load (10 - 20 pF) at TCK near FPGA can help in some cases. Regards FrankRe: LVDS support on Agilex 7
Hi Vigneswaran, you are right, DS90LV804 driver is at risk to exceed Agilex 7 absolute ratings due to larger Vocm tolerances. It should be also considered that on-chip rd termination is disabled in unconfigured FPGA state, resulting in even higher initial Vid. To keep on the safe side, I would either use a driver chip with tighter Vocm tolerance, add resistors that pull down common mode level or implement voltage dividers that shift signal level towards ground. Regards Frank
