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Re: MAX10 FPGA IOs not entering Tri-state (Hi-Z)
Hi Patrick, I believe this is a misunderstanding. DEV_OE pin is only functional in user mode (with valid configuration loaded) when enabled in device and pin options. Default IO pin state is three-state with weak pull-up, that's what you'll see before loading .sof or configuration from non-volatile memory. Regards FrankRe: Agilex5: How to use a GTS refclk to clock the FPGA fabric?
Hi, posted minimal design doesn't work because it doesn't connect system PLL output to anything, thus the PLL is discarded during synthesis. Modified top.sv respectively assign {//pad_rled0, pad_gled0, pad_bled0, pad_rled1, pad_gled1, pad_bled1, pad_rled2, pad_gled2, pad_bled2, pad_rled3, pad_gled3, pad_bled3} = 11'o213; //12'o4213; assign pad_dbg_tx = pad_dbg_rx; assign pad_rled0 = clk101p768092; assign clk101p768092_ready = 1'b1; Connecting the PLL reveals another error. The fact that you never got to this point suggests that the PLL wasn't implemented in your design, e.g. due to missing connectivity. Error(22849): Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file. Added set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ Get still complains about missing constraints, but design basically compiles now. Regards Frank P.S.: Don't know, if DEVICE_INITIALIZATION_CLOCK is actually required to run system_pll. GTS PHY itself needs it according to device handbook.Documentation of recent low-level and WYSIWYG primitives
Hello, it has been previously stated that Altera doesn't provide documentation of low-level primitives for newer FPGA series, e.g. Cyclone 10 GX or Agilex. See e.g. WYSIWYG documentation | Altera Community - 273853 What if I want to implement e.g. an octal SPI interface utilizing DDR and DQS driven data sampling with calibration? I presume that my IP would use tennm_io_12_lane and tennm_tile_ctrl primitives. They are published in Quartus as interface definition in tennm_components and a .xml parameter list. Can you provide additional information under NDA? Regards FrankRe: PL-UB3-CABLE spec
Hi Aaron, there's a User Guide available. Don't know if the part is actually available at distributors. I have seen UB3 hardware only implemented as on-board programmer with development boards. https://docs.altera.com/r/docs/864466/current/usb-blaster-iii-fpga-development-cable-user-guide Regards Frank
