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FvM
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Re: 10CL040YF484 Programming fails
Hi Suvarna, thanks for clarification about MSEL1. Didn't notice jumper resistor option. As you are supplying B6 with 3.3V, MSEL can be connected to 3.3V. 2.5V should be accepted as well. Having configuration correct, I wonder what causes failure of your board. I would probably try without C160-163 and D10/11 to be sure that they don't interfer with AS configuration load. Regarding 2.5 V switching regulator, I said I'd prefer LDO. it's exclusively loaded by VCCA and programming connector. Efficiency in normal operation is probably better for 3.3V supplied LDO. But your solution should work, too. Regards Frank P.S.: I notice that Figure 99. Combining JTAG and AS Configuration Schemes also has 10 pF capacitors, but without additional series resistors.Re: 10CL040YF484 Programming fails
Hi Survarna, reviewing your schematic, I notice that it fails to set AS configuration mode due to floating MSEL1. For apparently intended mode 0010, MSEL1 has to be connected to 3.3V. FPGA actually reads mode 0000 (PS) and won't load AS flash. Volatile JTAG configuration should nevertheless work. Regarding JTAG failure (programmer doesn't detect connected FPGA), you can focus on JTAG connection and FPGA power supply. All POR monitored voltages must be present and in range. Isolation of GNDA pins through ferrite bead isn't complying with Altera pin connection guidelines but probably does no harm. I would also prefer a LDO for 2.5V PLL supply. I believe that I last implemented separate AS programming ("ISP") connector 15 or 20 years ago. Since then we used JIC programming through JTAG connector. I understand that failing and (at least partly) working boards share the same hardware design. Regards FrankRe: Cyclone 10 LP Bitstream Compression Failing
Hi, I believe there are some misunderstandings involved with your post. 1. The .sof file, which is used for direct JTAG configuration and as a source for AS programming file generation is never compressed. 2. Compression can be enabled in Programming File Generator for .jic and .rpd AS programming files. It doesn't reduce .jic file size, which always reflects capacity of chosen flash device, but the non-erased file content (different from 0xFF) is reduced, also .rpd file size. Respectively flash programming time and time to load the configuration is shorter. 3. Compression option is somehow hidden in PFG GUI under properties of the .sof file.Re: Cyclone IV drop in replacement confirmations
Hi Brian, I apologize for not reading your question thoroughly. I didn't realize that you asked about feeding 2.5 VCCA supply to a 1.8 V GPIO due to migration compatible pin assignment. That should always work. To be sure, you can check the respective assignment in Quartus pinout table. I checked that Quartus indicates connection of VCCA4 (PIN_L12) to 2.5 V for EP4CE10F17 if you select migration compatibility to CE22, no matter that's in a 1.8 V bank. Regards FrankRe: LVDS Output of FPGA
Hi, observing "triangle" (slow rise/fall time) waveform suggests that you are no terminating LVDS outputs correctly. To see expected waveform according to LVDS standard, output need to be terminated with 100 ohm differential respectively 50 ohm single ended. Expect trf of e.g. 0.3 ns with correct termination. Regards FrankRe: Cyclone IV drop in replacement confirmations
Hi Brian, reading Cyclone IV datasheet strictly, Table 1-15 has also to be observed. It specifies Vinh,max of 2.25 V for 1.8 V banks. Don't no why and how the spec is related to general 3.6 Vin,max in table 1-3 and 1-4. According to device handbook, PCI diode isn't used vor 1.8 V and below I/O standards. Regards FrankRe: quartus ram gen full HDL
Hi, presume you are asking about synthesizable HDL code? Embedded RAM is a hardware feature of FPGA, HDL code provided by Quartus Megawizard or e.g. Xilinx RAM generator is only a wrapper. Respectively many parameters (memory organization, synchronous or asynchronous read/write, behaviour of additional signals) are target dependant, the code can't be easily ported to other devices. Regards Frank
