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FvM
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Re: My signaltap test has some problem
Hi, shown waveforms are rather an example of trigger condition is fulfilled instantly than "doesn't trigger". Can you please show related trigger settings? Generally speaking, triggering can be a problem if triggered waveform isn't synchronous to sampling clock, causing timing violation in Signaltap logic. Regard Frank14Views0likes0CommentsRe: Investigation of HIGH-Level Voltage Fluctuations on MAX 10 3.3 V LVTTL Output Signals
Hi, some additional questions: Are you seeing level variations in static voltage (DC or slow signal) or in high level of a pulse waveform (MHz speed)? In the latter case, are you sure that it's no measurement artifact, e.g. due to unsuitable probing? You say external device is DS90CR287, presume you are feeding CMOS inputs without additional load? Regards Frank5Views0likes0CommentsRe: ModelSim Intel FPGA Ed. 2020.1 not updating changes to HDL File
Hi, additional remark about requiring prior compilation in Quartus. NativeLink simulation flow needs apparently a compiled hierarchy to build the compilation script. If the design structure changes, a recompilation is necessary for NativeLink flow, functional changes of entities need only recompilation in simulator. This can be achieved in NativeLink flow by copying respective compile commands from .do script and pasting in Simulator gui. Regards Frank104Views0likes1CommentRe: ModelSim Intel FPGA Ed. 2020.1 not updating changes to HDL File
Hi, ModelSim and QuestaSim normally don't copy or "archive" source files, unless you specify so when adding the files to simulation project. As stated above, you however need to recompile modified files in ModelSim before restarting the simulation. Compile in ModelSim is much faster than in Quartus which isn't required for simulation. Regards Frank74Views0likes0CommentsRe: Quartus Prime Lite 25.1 - Issue with the Verilog generate loops
Hi ElShang, there's a change in generate block specification from Verilog 2001 to 2005. Verilog 2005 states (12.4 Generate constructs, page 181) The keywords generate and endgenerate may be used in a module to define a generate region. A generate region is a textual span in the module description where generate constructs may appear. Use of generate regions is optional. There is no semantic difference in the module when a generate region is used. Verilog 2001 requires generate - endgenerate (12.1.3 Generated instantiation, page 169) All generate instantiations are coded within a module scope and require the keywords generate - endgener ate. Quartus Prime Std implements only Verilog 2001 and not exactly defined Subset of System Verilog. In Quartus Prime Pro, the keywords are optional as you expect. Regards Frank148Views1like1CommentRe: Can MAX10-DC compact device supports RSU feature?
Hi, as stated Compact MAX10 doesn't support Dual Config IP and respective features, e.g. reconfig command. Rewriting CFM in user mode is nevertheless possible. You'll just miss the fallback to factory image in case of programming error or unexpected power fail. As long as no reconfig is issued, you can however verify and possibly correct flash content. I'm not sure if a built-in way to cause reconfiguration without external NCONFIG asserting or power cycle. In case of doubt, NCONFIG can be wired to a GPIO pin. Regards Frank121Views0likes0CommentsRe: MT25QL128 Not Available in ALTASMI_PARALLEL Configuration Device List
Hi, In ASMI II User Guide, Altera is suggesting to use Generic Serial Flash Interface IP for third party flash devices. Personally I prefer ASMI for its simple low level interface that fits best my communication interface. I can confirm that MT25QU512 works with ASMI in EPCQ512 configuration. I guess that MT25QL128 will work with EPCQ128 settings as well, but I didn't test. I'm using Winbond flash that's fully compatible with EPCQ128, both for ASMI IP and .jic generation. Regards Frank89Views1like0CommentsRe: Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hi, open cmd shell with administrative privileges and execute netstat -a -b You can stop netstat output after first few lines with <STRG>C You'll directly see which application is listening on port 1309.22Views0likes0Comments