New Contributor
Super ContributorHi,
I'd expect that single-ended IO, e.g. 1.8V standard can basically work for the interface. Maximum IO speed on the pin level is mainly limited by capacitive load and driver current strength. Achieving timing closure for DDR RX and TX is the other point. You don't only care for maximal pin toggle rate of a specific IO standard but also for delay skew from slowest to fastest pin timing over process and temperature variations, which narrows the sample window. Respectively setup- and hold margin may be more critical than simple clock speed.
Mentioned 166 MHz speed is only achieved in FlexSPI mode 3 with DQS RX strobe, it has to be provided by your interface design. DDIO registers should be used. I don't know if 166 MHz can be reliably achieved, something like 100 MHz should hopefully work.
B.t.w., I'm also planning QSPI DDR interface for a similar chip, but without DQS because it's occupied by other usage in my application.
Regards
Frank
New ContributorHi, thank you for your answer. I am aware that I have to implement a DQS strategy to achieve high frequencies. I'm trying to find information about setup and hold times of the pins on the datasheet but I can't find it. Is there something I am missing?
