Forum Discussion

SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
7 days ago

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Hi all,

The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge.

Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven from PCIE card edge.

After power up, IO PLL locked but System PLL cannot be locked, PCIE hard IP remains in reset status, regardless the configuration method of FPGA (that is, via JTAG or QSPI flash).

Here are my questions:

1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source.

2、If the answer of above question is positve, how should I debug to make the System PLL work?

Best regards.

Programmable Logic Device

1 Reply

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 hours ago

    Hi SYiwe ,

    1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source.
    >> Yes, it shall be independent and free running

    2、If the answer of above question is positve, how should I debug to make the System PLL work?
    >> did you compile the design ? is it running full compilation without any issue ?
    >> IF yes, please tap a signaltap , or you may use lspci to check either the ltssm is able to link up or not/
    >> Next, which design that you are using ? is this custom design or from our design example - I suggest to try direct the design example from Quartus IP catalog

    Sorry for late reply due to Lunar New Year holiday, Happy New year to you as well.
    Looking forward to hear back from you.

    Regards,
    WincentChiah_Altera