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Occasional ContributorSystem PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi all,
The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge.
Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven from PCIE card edge.
After power up, IO PLL locked but System PLL cannot be locked, PCIE hard IP remains in reset status, regardless the configuration method of FPGA (that is, via JTAG or QSPI flash).
Here are my questions:
1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source.
2、If the answer of above question is positve, how should I debug to make the System PLL work?
Best regards.
13 Replies
Wincent_AlteraRegular Contributor
Hi SYiwe ,
1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source.
>> Yes, it shall be independent and free running
2、If the answer of above question is positve, how should I debug to make the System PLL work?
>> did you compile the design ? is it running full compilation without any issue ?
>> IF yes, please tap a signaltap , or you may use lspci to check either the ltssm is able to link up or not/
>> Next, which design that you are using ? is this custom design or from our design example - I suggest to try direct the design example from Quartus IP catalog
Sorry for late reply due to Lunar New Year holiday, Happy New year to you as well.
Looking forward to hear back from you.
Regards,
WincentChiah_Altera
SYiweHi Wincent，
Thank you for your reply, wish you happ new year.
- The design is a full compiled Agilex5 PCIE example design,
- A signal tap is instanced and I found the system PLL cannot be locked with signal tap,
- I've used lspci and no FPGA PCIE EP found,
- Please let me know if you have any more suggestions.
Regards.
- Wincent_Altera
Hi SYiwe ,
Which device that you are using ?
Agilex 5 Modular devkit ? IF yes, I would suggest to try out the design example from IP Catalog.
A signal tap is instanced and I found the system PLL cannot be locked with signal tap,
>> Do you capturing the ltssm signal ?
>> What is the ltssm status ?
At the meantime, you may try out the suggestion provided by our community expert FVM as mentioned above
Regards,
Wincent_Altera
FvMSuper Contributor
Hi,
PCIe reference clock is spread spectrum modulated on most system boards, this may cause locking issues. PCIe IP core PLL should have bandwidth settings that tolerate spread spectrum clocking, but system PLL probably has not. To check if the issue is related to spread spectrum clocking, you can disable it in BIOS setup.
Regards Frank
- SYiwe
Hi Frank,
Thank you for your reply.
- How Can I confirm whether system PLL support spread spectrum modulated reference clock or not? I read PCIE IP and Native PHY user guide but no relative information found.
- Do you mean that I can try to disable PCIE card edge reference clock spread spectrum modulated function in BIOS when the main board linux system start up?
I will be appreciated if you can show me more suggestions, regards.
- FvM
Hi SYiwe,
system PLL has usually low bandwidth setting while PCIe PLL is set for wide bandwidth. My understanding is that wide bandwidth setting is necessary to support spread spectrum reference clock. You may try to change system PLL setting also to wide bandwidth and check if it will lock then.
Regards
Frank
