Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks!
Does the 1SG280LU2F50E2VG support bitfile encryption
I am attempting to encrypt and load an image to the 1SG280LU2F50E2VG on our Stratix 10 GX development kit following the instructions in AN 970: Intel® Stratix® 10 Security Tutorial. When I attempt to download the "root.qky" to the FPGA I see: Info(209060): Started Programmer operation at Thu Feb 12 18:01:59 2026 Info(18942): Configuring device index 1 Info(18943): Configuration succeeded at device index 1 Info(20091): Programming public key on device 1 Error(209012): Operation failed Info(209061): Ended Programmer operation at Thu Feb 12 18:02:02 2026 Is the FPGA on the development kit compatible with encryption?
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi all, The device is Agilex 5 E series FPGA, development kit is plugged in main board via a x16 card edge. Both System PLL reference clock and PCIE AXI Stream Hard IP reference clock are driven from PCIE card edge. After power up, IO PLL locked but System PLL cannot be locked, PCIE hard IP remains in reset status, regardless the configuration method of FPGA (that is, via JTAG or QSPI flash). Here are my questions: 1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source. 2、If the answer of above question is positve, how should I debug to make the System PLL work? Best regards.Unable to Generate .sof File in Quartus Prime Standard Edition 15.1 – 30‑Day Evaluation Mode
Hello, I am using Quartus Prime Standard Edition v15.1.0.185 in 30‑day evaluation mode. My goal is to compile a design and generate a .sof file during the evaluation period, but I am unable to produce the .sof file after full compilation. When Quartus starts, I get the following evaluation window: The option I am using is: Continue the 30‑day evaluation period with no license file (no device programming file support) But in the evaluation mode, Quartus completes compilation, but does not generate the .sof programming file. My Questions: Is it possible to generate a .sof file during the 30‑day free evaluation period? If not, what is the correct way to enable programming file support during the trial? Does the Standard Edition evaluation require a separate free trial license to allow .sof generation? If a temporary license is needed, where can I request/download it for Standard Edition v15.1.0.185? System Details: Quartus Prime Standard Edition 15.1.0.185 Device : Cyclone V 5CSEBA5U23I7 Any guidance would be greatly appreciated, as I need to confirm whether the evaluation period supports .sof file generation or if a license is mandatory. Thank you. Regards, Prateek
Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Dear Intel, Really having a hard time on switch to soft reset. According to datasheet and forum discussion. Hard reset on the hard PCIe require a specified pin or pins to work. In order to fully make use all LVDS pairs inside the same bank of the hard PCIe reset pin, it is a must to use soft reset. Under testing the hard reset pin can function properly on root port design. Once we changed to soft reset under xxxx.qsys: <parameter name="force_src" value="1" /> After loading the driver on linux via insmod xxx.ko It immediately stuck. The reset is based on https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/PCIe_Hard_IP assign pcie_npor_pin_perst = pcie_reset ? ~pcie_reset : 1'bz; assign pcie_npor_npor = hps_fpga_reset_n & pcie_npor_pin_perst .pcie_cv_hip_avmm_0_npor_npor (pcie_npor_npor), .pcie_cv_hip_avmm_0_npor_pin_perst (pcie_npor_pin_perst), "pcie_reset" signal is generated by PIO IP Thanks, Brian
