How to set initial register values after powerup
Hello, A topic that has been written about a few times. But how to make sure a specific register value is set, after the FPGA has powered up? I have learned that setting an initial value have no effect other than in simulation. I have a specific case where I want a specific value to by 10. So far I have made it so, that I use an external reset signal/pin to force all my registers into their "start" state. But is there a more clever way that this can be done in VHDL instead. I use Cyclone IV and have read that some Altera devices have this "Reset Release" IP avilable that do a reset after powerup. Thank you.
NOR Flash IC programming using 3rd party Programmer
We have observed that programming the NOR Flash using the Altera USB‑Blaster via JTAG behaves differently compared to programming the same Flash device using a third‑party gang programmer. We have created an RPD file as mentioned in the below intel document, tutorial-write-raw-programming-data-rpd-into-flash-devices.pdf Observations During NOR Flash Programming 1.When the fresh NOR Flash IC is programmed using a third‑party programming tool and subsequently mounted on the Base Card, the card fails to boot. 2.However, the RPD image functions correctly when the following programming sequence is followed: -> Program the fresh NOR Flash of the CFPG A using the Altera USB Blaster via JTAG. -> Erase the NOR Flash. -> Reprogram the same RPD image, generated as per the procedure defined in the referenced document. When the above sequence is followed, the card boots and operates as expected. We would appreciate your input on whether any additional steps are required when using third‑party programmers to ensure compatibility with the FPGA boot mechanism.
Signal counts incorrectly on EP4CE6E22C8N while others signal work fine (same code Verilog)
I am facing a strange issue on FPGA EP4CE6E22C8N (Cyclone IV), i use quartus II 13.0 and signaltap to debug. I have three input signals running in parallel, using the same HDL code and the same timing standard. Two signals work correctly, but one signal always counts incorrectly, even though the input waveform itself looks correct so i donn't know problem is hardware,software, setup quartus or all of its. Design description - The module counts the length of LOW level of signal inside a valid window. - The longest LOW segment is stored as max_len and max_pos. - The input signal is synchronized using a 3 flip-flop synchronizer. - Debugging is done using SignalTap, and the input signals are confirmed to be correct. Verilog Source Code module counter_max_in_segN #( parameter SEG_N_START_PIXEL_NUMBER, parameter SEG_N_END_PIXEL_NUMBER, parameter OFFSET_SEG_N, parameter MAX_CLK_COUNTER ) ( input wire clk, input wire rst, input wire sp, input wire vN_signal, output reg [9:0] out_len, output reg [9:0] out_pos, output wire be_cover ); reg [2:0] vN_sync_reg = 3'b111; wire vN_clean; reg [9:0] clk_counter = 10'd0; reg [9:0] max_len = 10'd0; reg [9:0] max_pos = 10'd0; reg [9:0] counter_shadow = 10'd0; reg [9:0] counter_pos = 10'd0; reg becover = 1'b0; assign be_cover = becover; always @(posedge clk) begin vN_sync_reg <= {vN_sync_reg[1:0], vN_signal}; if (sp || ~rst) begin clk_counter <= 10'd0; max_len <= 10'd0; max_pos <= 10'd0; out_len <= 10'd0; out_pos <= 10'd0; counter_pos <= 10'd0; counter_shadow <= 10'd0; becover <= 1'b0; end else begin clk_counter <= clk_counter + 1'b1; if (clk_counter > 10'd71 && clk_counter <= SEG_N_END_PIXEL_NUMBER + 10'd71) begin if (vN_clean == 1'b0) begin becover <= 1'b1; counter_pos <= clk_counter - 10'd71; counter_shadow <= counter_shadow + 10'd1; end else begin becover <= 1'b0; if (counter_shadow >= max_len) begin max_len <= counter_shadow + 10'd3; max_pos <= counter_pos; end counter_shadow <= 10'd0; counter_pos <= 10'd0; end end else if (clk_counter > 10'd288 + 10'd71 && max_len != 10'd0 && max_len <= max_pos) begin out_len <= max_len; out_pos <= max_pos + OFFSET_SEG_N + 1'd1; end end end assign vN_clean = (vN_sync_reg == 3'b000) ? 1'b0 : 1'b1; endmodule Declare in top module counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd0), .MAX_CLK_COUNTER(10'd380)) counter_seg1( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v1), .out_len(out_len_1), .out_pos(out_pos_1) ); counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd216), .MAX_CLK_COUNTER(10'd380)) counter_seg2( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v2), .out_len(out_len_2), .out_pos(out_pos_2) ); counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd287), .OFFSET_SEG_N(10'd432), .MAX_CLK_COUNTER(10'd380)) counter_seg3( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v3), .out_len(out_len_3), .out_pos(out_pos_3) ); Summary I try change pinout but has same problem above, the third signal always read wrong so i want to know what and why make this problem and also how to fix it? Thanks for all help. Result of signaltap
Agilex 7 R-Tile RBES FPGA – CXL Device Enumeration Failure with CXL IP Design Example
1. What is the failure symptom? Please elaborate on the failure symptoms in detail. The CXL device fails to enumerate when using the CXL Type-3 IP design example. • lspci -vvv | grep 0ddb does not detect the CXL device • numactl -H does not report a CXL NUMA node The issue persists across multiple system reboots and bitstream rebuilds. A factory reset was attempted but did not resolve the issue. 2. When did the failure happen? When did you buy the part, and when did you receive it? The device failed at some point around October 2025. 3. How did you discover the failure? Please describe it in detail. We found OS failed to find the CXL device and confirmed the issue after factory recovery. 4. In which part of your process did you find the issue (Lab, production, quality, etc.)? Lab environment.4.1 Was the device already in the field? How many times has it been used? No. The device has only been used in a controlled lab environment for bring-up and testing. 5. How many units failed and how many units were used/tested by you? Which is the production code? • Failed units: 1 • Units tested: Multiple Agilex FPGA boards • Production code: Not available Only this unit exhibits the failure. 6. How did you determine the failure? Please elaborate on the procedures. Multiple bring-up attempts were conducted using known-good hardware, software, and bitstreams. • 6.1 Internal Debug: No internal physical failure analysis was performed. • 6.2 Device Swap: Yes. Replacing the board with a known-good FPGA resolves the issue. 7. Was the failing unit ever working before the failure? Yes. The device was functioning correctly before the failure. 8. How did you rule out electrical overstress (EOS) or electrostatic discharge (ESD)? There is no visible physical damage on the FPGA or PCB. The board has been handled according to standard ESD-safe lab procedures. 9. What are your expectations from this failure analysis? Identify the root cause of the failure and restore proper CXL IP functionality, or provide a replacement device. 10. Have you re-balled your device? If yes, was it lead-free reballing? No. The device has not been re-balled, and no third-party rework was performed. 11. Please add pictures of the device from the top and the bottom. See attached. 12. Is there any other relevant information that could assist in the failure analysis? No additional information at this time. 13. Are there any known changes to the process, materials, or design that could have contributed to the failure? No.
Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!Agilex 7 R-Tile RES FPGA – CXL Device Enumeration Failure with CXL IP Design Example
OPN:DK-DEV-AGI027RES (Power Solution 1) SN: AGIPCIE8000296 1.Failure Symptom The CXL device fails to enumerate when using the CXL Type-3 IP design example. • lspci -vvv | grep 0ddb does not detect the CXL device • numactl -H does not report a CXL NUMA node The issue persists across multiple system reboots and bitstream rebuilds. A factory reset was attempted but did not resolve the issue. 2. When did the failure happen? When did you buy the part, and when did you receive it? The device was received approximately two years ago. The failure was observed during initial bring-up and has been present since first use 3. How did you discover the failure? Please describe it in detail. We programmed the FPGA with the CXL Type-3 design example; however, the host server failed to enumerate the device. The same bitstream works correctly on other Agilex FPGA boards, indicating the issue is specific to this unit 4. In which part of your process did you find the issue (Lab, production, quality, etc.)? Lab environment. 4.1 Was the device already in the field? How many times has it been used? No. The device has only been used in a controlled lab environment for bring-up and testing 5. How many units failed and how many units were used/tested by you? Which is the production code? • Failed units: 1 • Units tested: Multiple Agilex FPGA boards • Production code: Not available Only this unit exhibits the failure. 6. How did you determine the failure? Please elaborate on the procedures. Multiple bring-up attempts were performed using known-good hardware, software, and bitstreams. • 6.1 Internal Debug: No internal physical failure analysis (e.g., X-ray or short-circuit testing) was performed. • 6.2 Device Swap: Yes. Replacing the board with a known-good FPGA resolves the issue. 7. Was the failing unit ever working before the failure? No. The unit has never functioned correctly since initial use. 8. How did you rule out electrical overstress (EOS) or electrostatic discharge (ESD)? There is no visible physical damage on the FPGA or PCB. The board has been handled according to standard ESD-safe lab procedures. 9. What are your expectations from this failure analysis? Identify the root cause of the failure and either restore proper CXL IP functionality or provide a replacement device 10. Have you re-balled your device? If yes, was it lead-free reballing? No. The device has not been re-balled, and no third-party rework has been performed. 11. Please add pictures of the device from the top and the bottom.See attached. 12. Is there any other relevant information that could assist in the failure analysis? No additional information at this time.Agilex 5 FPGAs D-Series Availability
Hi Team, I am currently designing a new system and intend to use the Agilex 5 D-Series 160 FPGA (Part Number: A5DF-D-I-160-AB37-A-I-1-S) but in website no such part is shown kindly share the availability details of D series FPGA in market. Thanks in Advance, Regards, Indujha S
IO speed limit while implementing high resolution PWM on Cyclone 10
I would like to implement high resolution PWM on a Cyclone 10 LP. One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ended IOs (3.3V LVTTL for example) cannot switch that fast, when I compiled the design I got a [limit due to minimum port rate restriction (tmin)] with original Fmax=425MHz restricted to 223MHz. But for my application I know I can control the minimum pulse width in software. So my question is where does the IO speed limit actually apply? Does it apply in the IO buffer or does it apply in the double data rate register? In the former case that should not create a problem because I am not switching every cycle, I only want to tune the pulse width with fine steps. In the later case it would. I want to ask this for both input and output, as I might want to measure the realized switching pattern as well. I am aware that another possible way is to add a delay to the IO. However correct me if I am wrong, I don't see how I can dynamically choose the IO delay in any of the IP / primitives. You can dynamically change the phase of the PLL I guess, but I am not sure how fast does it stabilize at the new phase. Also If I use multiple output in my design then I would need a dedicated clock output for each output.
MAX10 nCONFIG pin slew rate requirement
Hello, is there any requirement for nCONFIG pin of MAX10 family with regards to signal transition time (signal slew rate)? Unfortunately MAX10 data sheet does not include any parameter for the same. It also does not specify, if the nCONFIG includes a Schnitt-Trigger feature which makes any slew rate demand redudant. Best regards Frank
