Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, BrianQuartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
M9K utilization is different for the same RAM IP for two different projects.
I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects. The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks. For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below: The settings for the RAM-IP are as shown in the image below: Quartus Tool Version : Quartus 18.1 Standard FPGA Device : MAX-10 10M50DAF256I7G Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks. Thank you, Akhilesh.Unable to checkout a viewer license
I was given this license for free as a part of a course at my university. It expires in August 2026, but when I tried using it again after about 4 months, I'm getting an error message when launching Questa. The error message reads: "Unable to checkout a viewer license necessary for use of the Questa Intel Starter FPGA Edition graphical user interface. Vsim is closing." I tried contacting my university's IT department, and we tried debugging this error for around a week back and forth. After exhausting the common potential fixes like making sure the LM_LICENSE_FILE environment variable points to the correct path and trying to run the software connected to my school's VPN, we had no luck. We determined that the MAC Address of my machine was the same as that of the NIC expected in the license file except the last two digits of my machine are 11 instead of the 15 that the license file expects. This software worked completely fine for me when I took the course, and it was only after around 4 months that when I launched the product, I ran into this issue. The IT department said: "Because you used the software through a Mines (my university) course, it was most likely pulling from a campus floating license or on the university's license server. You can either try to replace environment variable with LM_LICENSE_FILE=27000@ece-license.mines.edu while on the VPN. Otherwise, you will need to request a corrected fixed‑node license from Intel." I would really love to solve this issue. I am happy to provide any other details that may help you to solve this problem!
How to Simulate the ADC IP from MAX 10
Hi, I want to simulate the ADC IP. I have generated a qsys file and then I have generated the Synthesis and Simulations files (both VHDL) in Quartus Prime Lite I have set the simulator to Questa Intel FPGA and also VHDL, and added my test Bench (also VHDL) then i start the simulation: Tools--> Run Simulation Tool--> RTL Simulation Its compiling, but then I get these errors. it seems that either some settings are wrong in the Simulation files from the ADC IP, or an library include is missing. I have no idea how to fix it. The ADC block works in the synthesis on the Hardware. I also get 2 warnings in the IP files during compilation: ** Warning: (vlog-2083) d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/fiftyfivenm_adcblock_top_wrapper.v(11): Carriage return (0x0D) is not followed by a newline (0x0A). ** Warning: d:/quartus/tb_adc_to_parallel_vhdl/db/ip/adc_to_parallel/submodules/altera_merlin_master_translator.sv(536): (vlog-13528) Extra Parentheses after time system function. I have tried to simalate a none qsys IP block (FIFO) and this worked as expected. Used Software: Quartus Prime Lite 24.1 (because the 25.1 has problems with the PLL IP, but the same error message during Simulation) Questa Intel Starter FPGA Edition 2024.3 Kind Regrards JonasAgilex 3 PLL in Source Synchronous mode ?
Surprisingly, the compilation fails when we try to set a PLL in source synchronous mode in an Agilex 3, while this works as expected in Agilex 5. Compiles in "direct" mode. The pin assignment comes from the Atum A3-nano but we tried various dedicated clock inputs to no avail. The error messages are a bit puzzling too (I think there are 11 PLLs in the A3CZ135BB18AE7S ) : Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL IP pll_altera_iopll_2110_hws7ggy. Info (14596): Information about the failing component(s): Info (175028): The IOPLL name(s): u_pll|iopll_0|tennm_ph2_iopll Error (16234): No legal location could be found out of 5 considered location(s). Reasons why each location could not be used are summarized below: Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to "u_pll|iopll_0|tennm_ph2_iopll". Promote refclk to a global clock or use a dedicated IOPLL refclk pin. (4 locations affected) Info (175029): IOPLL_X106_Y53_N346 Info (175029): IOPLL_X121_Y31_N846 Info (175029): IOPLL_X106_Y2_N346 Info (175029): IOPLL_X1_Y3_N346 Error (175006): There is no routing connectivity between the IOPLL and the IOPLL Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements Info (175029): 1 location affected Info (175029): IOPLL_X121_Y6_N846 Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. Error (16297): An error has occurred while trying to initialize the plan stage. Error: Quartus Prime Fitter was unsuccessful. 8 errors, 11 warnings -------------------------------------------- This is very annoying for source synchronous interfaces (like RGMII). Test case available indeed.about cyclone 10gx transceiver
Hi, recently I am trying to debug cyclone 10 gx transceivers, and the settings are as the figures above. After reseting, I first send 32'h12345678 as the control world, and set tx_control[1:0] = 2'b10. During this time, in my logic I using rx_bitslip to slip the bits until rx_parallel_data is equal to 32'h12345678. After that, I continually send incremental counter value through transmitter with tx_control[1:0] = 2'b01, but the receiver gets rx_control[1:0] equal to 1, 2, 3, changing all the time, which is shown as following figure. So, did I set parameters wrongly? Or how can l solve it? Thank you.
