Worst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)
Hello, Please tell me the maximum time between the execution of Phasestep and the completion of Phasedone. The relevant link is below. Cyclone® IV Device Handbook - Chapter 5: Clock Networks and PLLs in Cyclone IV Devices - Figure 5–26. PLL Dynamic Phase Shift The reason for this is that the wait time for the phase shift to complete is required in the higher-level design. Regards
Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy
Hi, 1. The Agliex 7 F Series EMIF User Guide page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F series evaluation board DDR4 memory vendor datasheet (thisis publicly available one for the MT40A2G8VA used on above linked eval board) states RESET must be low while power rails ramp up as pictured below which implies it should be instead pulled down to ground. Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies? From above public Micron datasheet 2. Figure 143 in section 6.5.6.1 of Agilex 7 EMIF User Guide shows ADDR/CMD clock terminated to VDD through R and C network. Altera F Tile eval board has ADDR/CMD clock terminated to GND through R and C network. Can Altera explain why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation? From Eval board Thanks!
Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Country of Origin Request
Dear Team, Greetings!!! Can you please help to provide country of Origin info for below listed ALTERA parts. Part no Country of Origin PL-USB-BLASTER-RCN EPCQ128ASI16N EP4CGX30CF19C7N EP2C35F484C7N EP4CE22E22A7N EP4CE22E22C6N EP4CE22E22C7N EP4CE22E22I7N EP4CGX75CF23C8N 5M1270ZT144C5N 5M160ZM100C5N 5M240ZM100C5N 10M16SAU169C8G 10M25DCF484C7G 10M50DAF256C7G 10M50DCF484C7G EP3C40F484I7N 5CEBA5F23C7N 5CEBA5F23C8N 5CGXFC7C7F23C8N 5CSEMA5F31C8N DK-DEV-10M50-A EPCQ128SI16N EP1C20F400C6 EN5322QI EP2S30F672C5N DK-DEV-5CGTD9N
EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)
Hi Altera Support Team, We are trying to install two Micron 32GB 2Rx4 RDIMMs on the Agilex 7 I-Series FPGA Development Kit, PCB Rev. A (DK-DEV-AGI027R1BES), and would like to confirm the correct EMIF pin assignment for this board. We have already enabled these two DIMMs on a DK-DEV-AGI027RBES board. However, we noticed that the golden pin assignment provided in the installer package appears to be the same for both FPGA boards. Since these two boards use different power solutions and different pin assignments, we believe the DK-DEV-AGI027R1BES should require a different EMIF pin assignment. At the moment, we have not been able to find the correct pin assignment for the DK-DEV-AGI027R1BES board. Could you please provide this information, or point us to the appropriate documentation? Best regards, YangLVDS support on Agilex 7
HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?
Agilex5 - Timings configuration
Hi, in document 813918, I have a question regrading method to define NOR timing, table 115, using Text_delay as conditions for input timings. this parameter is said dependant of frequency of interface (note 195), but only one value (max) is given (no min), and this one is greater than half-period and even at clock frequency 166MHz which seems to be considered by datasheet. I don't understand. Can we get simply Setup and Hold timings for Agilex inputs for AS configuration interface ? Thanks and regards
