Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
Multi Port front end IP for the single port DDR4 memory controller - Stratix10 TX
Part 1ST085EN2F43I2LGAS Do we have IP core details or reference design for the Multi Port front end IP for the single port DDR4 memory controller. What we need is one external memory and EMI shared with multiple FPGA modules as shown below. We need the multi-port front end IP that will enable multiple FPGA modules to access a common external memory. Do we have solution here. Regards amolAgilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank you
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.Agilex 7M HBM Bus Width Converter Failure
While testing an HBM DMA design we found our DMA read was seeing the data from the HBM, but words were missing. We intended to read 36x 256-bit words. We are seeing 18 words read and 18 words beyond the end of the expected address range. Looking closer, we are seeing word 0, 3, 4, 7, 8 etc. so skipping 2 every 4 256-bit words. We suspect an issue between the 512-bit fabric NOC and the 256-bit AXI initiator. It looks like platform designer just has a huge limitation regarding AXI interconnects. What I think it automatically does, which it does not make the user aware of, is passing AXI burst information directly from master to slave when it does the “width conversion”, instead of actually doing a proper conversion of the AXI burst (ARSIZE, ARLEN, ARADDR). For most use-cases this is not the behavior that you would want, basically making this “automatic feature” unusable. I think this section in the platform designer user guide kind of hints at that: https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/width-adaptation-and-data-packing-in-platform-designer We believe it is passing the request as a “narrow AXI” request, which isn’t supported by the fabric NOC and/or NOC initiator/HBM. To work around this, I think we could either: - Update the DMAs to operate at 512b instead of 256b (would consume too many routing resources) - Implement our own 256b to 512b converters (redundant with the automatically inserted, non-functioning converters. so wastes ALM resources) - Update some of the NOC initiators for 256b instead of 512b (not fast enough, and we would lose the benefits of using the fabric NoC (available when doing 512b)) None of these work arounds are acceptable for us. Can you please help us make the automatically inserted bus width converters function properly? If we switch to Avalon bus would they work properly, and maintain single clock accesses to HBM? Note: We are using Quartus Prime Pro 25.1.0
Quartus 12 build from pipeline
I have an old project using Quartus 12 and NIOS2 IDE v12,build 178. This is a legacy system which I still have to maintain for a long time, so I wanted to see if I could get this into a pipeline build like all the new projects. Everything compiles without issues when using Eclipse, but as soon as I try to do this from commandline nothing works :) Guessing that Eclipse does some magic, but have not been able to figure out what. Does anyone here have any experience with building these old projects from commandline ? If so any suggestions and tips would be highly appriciated.
Trying to reach an EPCQ128A thought Cyclone V dedicated pins, after FPGA loaded in FPPx32
Hello. Considering the configuration in the table below. FPGA/HPS 5CSXFC6D6F31I7 EPCQ EPCQ128A MSEL 0b01010 (FPPx32) GSFI CSR addr 0xC0010000 Configuration HPS boot from µSD, loading a U-Boot HPS configures a FPGA design containing a Generic Serial Flash Interface (GSFI) HPS asserts 'Bridge enable" command EPCQ routed on the AS FPGA dedicated pins EPCQ/FPGA routage verification We firstly tried to test this connection using a Read ID command asseted on the GSFI CSR throughout the H2F-AXI in 0xC0000000 + 0x00010000 and we get the EPCQ ID 0xFF (Expected 0x18) Once we will succes in the read ID command, we will proceed to a write command to set our own value, and then read it back to check the commands execution. We will repeat several times following a defined scheme. Is there a way to boot in FPPx32 and then, while in user mode, drive the EPCQ as a master without MSEL modification ?Cyclone V PCIe Reconfigure Busy Signal
Hello, I am working on a Cyclone V GT PCIe endpoint system in Platform Designer (Quartus version 24.1 Standard Edition). The system is based on the ep_g2x4 reference design (using the Avalon-MM Cyclone V Hard IP for PCI Express). I am trying to figure out what needs to be done with the "reconfig_busy" input to the hard IP. It seems the reconfiguration busy signal is already used between the transceiver reconfiguration IP and the PCIe reconfiguration driver IP. There are two mentions that I see of this signal in the Cyclone V Avalon-MM Interface for PCI Express manual (document 683494). The first mention is in the transceiver control signals section. busy_xcvr_reconfig - Input - When asserted, indicates that the a reconfiguration operation is in progress. In the Revision History, it mentions that the reconfig_busy signal connection between the PCIe IP core and the reconfig controller was removed. Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver. In the Platform Designer reference design, this signal is exported, which doesn't help. This info doesn't help me determine how this signal needs to be driven. Since this is handled by the transceiver reconfiguration IP and the PCIe reconfiguration driver IP, is it sufficient to drive the reconfig_busy input to the PCIe IP to '0'? Thanks in advance.
