Forum Discussion

Asaf_Bloch's avatar
Asaf_Bloch
Icon for New Contributor rankNew Contributor
1 month ago

Cold Temperature Issue

Hallo,

We used the Agilex5 device in AS configuration connect to external QSPI Flash.

We apply Smart VID interface at the device demands. 

When we perform Cold power up at -40C the device is not configured, It seemed the device is not  output from the POR, No traffic on the PMBus.   

Power sequence and voltage ramp time and levels are OK.

Please advise

Thanks

Asaf

 

 

Configuration
Programmable Logic Device

19 Replies

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hello, 

     

    Can you share below information:

    1- QSPI flash part number

    2- VR(Voltage regulator) part number

    3- Agilex5 part number

     

    regards,

    Farabi

    • Asaf_Bloch's avatar
      Asaf_Bloch
      Icon for New Contributor rankNew Contributor
      1 month ago

      Hello Farabi,

      1 - QSPI Flash -  MT25QU256ABA8E12-1SIT by Micron

      2 - VR - LT7184SRV#TRPBF by Analog Device

      3 - Agilex5 - A5EC043AB23AI2E

      Thanks

      Asaf

       

      • Farabi_Altera's avatar
        Farabi_Altera
        Icon for Regular Contributor rankRegular Contributor
        1 month ago

        Hello Asaf, 

         

        If the device is not output from POR, do you have the oscilloscope capture the power rails ramping up? 

        Any abnormal voltage ramp up during power up? Especially all the power rails monitored by POR circuitry. 

         

        regards,

        Farabi

  • dpcsu_e's avatar
    dpcsu_e
    Icon for New Contributor rankNew Contributor
    1 month ago

    Hi,
    just a short question (do not want to deter this thread): how did you detect it is not out of POR?

    (maybe relevant maybe not) On 2 out of 50 Agilex3 devices we have met with similar issue and resulted that over JTAG idcode was read as F36FF0DD instead of 4365B0DD. Is it equivalent to this same issue that SDM ROM code is not coming out of POR? do you observe similar behavior?

    How does your power topology looks like?

    We have 1.8V and 3.3V HVIO and if 3.3V HVIO's VCCIO do not get some minor accidental backfeed which raises it to 0.6V then FPGA stays in POR. 
    Voltage rail sequence is 0.75V -> 1.8V -> 1.2V -> 3.3V.
    Is it ok to bring up 1.8V SDM and 1.8V VCCIO at the same time or should we bring up the 1.8V+3.3V VCCIO after 1.2V?

    Thanks,
    Peter

    • Asaf_Bloch's avatar
      Asaf_Bloch
      Icon for New Contributor rankNew Contributor
      1 month ago

      Hi dpcsu,

      Thanks for your reply

      Our voltage rail sequence is VID, 08V -> 1.8V -> 1.2V, 3.3 VCCIO

      We detect the POR issue because we don't see any signal transitions after power up (nStatus, PMBus), JTAG detect the device.

      How did you read the SDM ROM?

        Any way we repeat the test with other PCB and it pass successfully, so we examine if it specific PCB issue.

      regards

      Asaf 

      • dpcsu_e's avatar
        dpcsu_e
        Icon for New Contributor rankNew Contributor
        1 month ago

        Hi Asaf,

        thanks!
        I did not read ROM code out, it is assumed that SDM ROM code did not startup properly since the JTAG IDCODE is not fully populated.

        My assumption that it is (like in many hardware platforms, not just at altera) reading out some fuses to see what FPGA the ROM code sits and populating the IDCODE accordingly (that's where I could see F's instead of the real digits when boot is not correct, you can also check if you end up similarly (it is much easier to detect than reading i2c bus traffic)). If SDM ROM code starts up properly then those digits are populated and the rest is probably coming from hardwired JTAG logic (that's the only reasonable explanation to it, but Altera please correct me if I am wrong.)

        It would be really great to have some reliable boot debug guide/logic around this early SDM boot problems because of POR/Power, so we could proceed faster in design bring-up.

        Kind regards,
        Peter