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Asaf_Bloch's avatar
Asaf_Bloch
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3 months ago
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Cold Temperature Issue

Hallo, We used the Agilex5 device in AS configuration connect to external QSPI Flash. We apply Smart VID interface at the device demands.  When we perform Cold power up at -40C the device is not c...
Configuration
Programmable Logic Device
  • Farabi_Altera's avatar
    Farabi_Altera
    2 months ago

    Hi Asaf, 

     

    Good to hear that you solved the issue. Yes, all the configuration signals are sensitive can't let the voltage drop even few microseconds. 

Asaf_Bloch's avatar
Asaf_Bloch
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2 months ago

Hello Farabi,

The 3.3V ramping because there are pull-up resistors connected to the system 3.3V, it is low voltage level,

Anyway I moved it and it did not change the cold issue.

 I notice the MSEL and nconfige signals are pull up and down during Vccio_SDM ramping, is it normal behavior? See attached

Thanks 

Asaf

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

HI Asaf, 

 

No that is not normal. MSEL is a fixed connection either HIGH or LOW only. It should not toggle during configuration. 

Please connect MSEL pin directly to VCC for HIGH, and directly to GND for LOW setup. Dont control the MSEL. 

 

regards,

Farabi

  • Asaf_Bloch's avatar
    Asaf_Bloch
    Icon for New Contributor rankNew Contributor
    2 months ago

    Thanks Farabi,

    The issue is after configuration I see the MSE2 is rising to 1.8V, seemed it by the FPAG, is it normal?

    Can it harm the pin?

    Thanks

    Asaf

     

    • Farabi_Altera's avatar
      Farabi_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi Asaf, 

       

      Do you have further question? 

       

      regards,
      Farabi

      • Asaf_Bloch's avatar
        Asaf_Bloch
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        2 months ago

        Hi Farabi,

        Thanks for your reply,

        No further question, 

        It seemed the configuration failure at cold  temperature cause by voltage translator of the nSTATUS signal,

        The following is summarized of the FPGA cold start issue finding:

        The design:

        nCONFIG and nSTATUS signals pass trough voltage translator 3.3V to 1.8V, this translator is an Auto-direction sensing, when it detects rising or falling in one side it pulls the other side to proper state. 

        Finding:

        We observed that during 1.8V ramp up many signals connected to the FPGA pulled high or low for few micro- seconds – see below.

        (1.8V = Vccio_SDM – FPGA SDM voltage)

        After our understanding that the issue is not because the nCONGIF signal, we examine the nSTATUS signal.

        In normal operation nSTATUS should rise during power-up and then follow the nCONFIG signal.

        It should not pull low during power-up by external host.

        In cases the configuration failed we found that the nSTATUS is stack low, the reason is that the translator detect the nSTATUS falling during start-up and pull it low, if we change the pull-up resistor on the nSTATUS signal from 10K to 1K the translator is not able to pull it low and configuration succussed.

        Failed configuration

         

        Configuration succussed with 1K pull-up on nSTATUS

    • Farabi_Altera's avatar
      Farabi_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi Asaf, 

       

      After configuration MSEL is not sampled. So we dont care the status after configuration. but normally the status will not toggle(normally MSEL hardwired to either VCC or GND-this is stable HIGH or LOW). Still this observation is not normal. 

      Can it harm the pin- basically no harm, unless the voltage or current exceed the recommended operating condition(buffer damaged due to overstress).

       

      regards,

      Farabi