Cyclone 10 LP's Extended Industrial parts
[Question] Customer have questions about Cyclone 10 LP's Extended Industrial (Tj = -40degC to 125degC) in the Product Catalog at the following URL. https://www.intel.com/content/www/us/en/content-details/730595/altera-product-catalog.html What is part number of Extended Industrial of "10 CL010YM164I7 G" as part number of Normal Industrial? What should the customer do if they want to check the power consumption by EPE(Early Power Estimator)? How can the customer design with Extended Industrial part if they want to compile with Quartus? Best Regards
LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve
Hi Team, I am facing a pin assignment issue with LVDS TX and RX IP in Quartus Prime. I have tried all the suggestions provided earlier (bank selection, I/O standard, refclk, PLL connections, and pin constraints), but I am still encountering pin assignment errors during compilation. Details: - Device: AGIB022R31A2I2VB - Tool: Quartus Prime 25.1.1 - LVDS IP: TX and RX - Mode: External pll mode in both TX and RX - Issue: Pin assignment errors related to LVDS TX/RX signals I have verified: - Correct I/O banks and VCCIO - Differential pair placement - Dedicated reference clock usage - PLL lock status Despite this, the issue persists. I have attached all relevant files: - .qsf If possible, could someone please: 1. Review the attached files and point out what might be wrong, OR 2. Share a small working reference project for LVDS TX/RX pin assignment I am also open to discussing this over a call if needed, as it may be easier to debug. Any guidance would be appreciated. Thanks & Regards, HariMAX 10 FPGA POR trip Levsl and tRAMP
I am intending to use a 36 pin count dual power supply MAX 10 part for a lower power application. From Fig 3 of UG-M10PWR (pasted below), nStatus is asserted when POR trip level is met within tRAMP. The battery for my application may have a longer ramp up time than tRAMP (10 msec for my part). What is the consequence of this. Will device not come out of reset if tRAMP condition is not met? Are there any workarounds for this?
License Server new License File
Hallo, I have to set up a new license server on a new machine. I am capable of doing this; my problem is the license itself. I only have the old license.lic from the old machine — but due to the corporate change from Intel to Silver Lake I can't reach any of the former Intel contacts anymore. I am also unsure if the "Intel® FPGA Licensing Support Center" is still responsible. Any insights on what the procedure is and who to contact? Viele Grüße Oliver Schumann Siemens AG, Nürnberg
Reset offset for Cyclone 10 GX 085
Hello! I have in my system a Cyclone 10 GX 085 FPGA (10CX085YF672I6G) and connected throught the Active Serial interface (4x) to a Winbound W25Q256JW device (256 Mbit). If I use the reset vector (set in Platform designer in the NiosV parameter window) as 0x02000000, then when I run niosv-bsp command it gives me the follwowing error: 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry]" 2026.02.04.14:45:36 Info: Saving BSP settings file. 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: .entry section mapping not created because reset memory region not located at base address: 0x2000000 2026.02.04.14:45:36 Error: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry]" 2026.02.04.14:45:36 Error: BSP not valid. 2026.02.04.14:45:36 Error: CPU "My_NiosV" reset memory "intel_generic_serial_flash_interface_top_0_avl_mem" has no matching memory region. But if I us use the reset vector at 0x01000000 I don't get the error anymore. The problem is that when I load the hex file I eventually produce into the "Convert programming file" window, I get the following error: The requested address range for page app.hex (0x02000000 - 0x0201DFCF) overlaps with the address range for page Reserved Option Bits on flash device 2 (0x02000000 - 0x0200001F) If I change the reeet vector to 0x01000000 then I don't get the error. So in summary reset vector 0x02000000 : error when I generate the BSP reset vector 0x01000000: error when I generate the JIC file Any idea what might be happening? I included the project folder.
Trouble Getting started with Stratix 10 SOC
I've recently purchased a Stratix 10 SOC board for experimentation. Although I've got the out of the box GHRD loaded and working, I've been struggling to get ANY changes I've made properly loaded into it. For example just changing the sysid in qsys and recompiling, generating the .sof and then converting it to an .rbf and loading it in uboot causes an error: command 'load' failed: Error -110 I understand that the Stratix 10 has a lot of security to ensure the bitstreams are validated and consistent, etc, and I'm sure this is useful in some contexts. But is there a way to disable some of this security to help a beginner get to the point where they can quickly start seeing designs loaded and working? NOTE: I'm not a total beginner. I've been experimenting with the Cyclone family (DE10-Nano, etc) for a few years now. But the Stratix is obviously a whole other level. Thanks,Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
