LVDS support on Agilex 7
HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?
Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required
Quartus 25.1 usually crashes during fitter, with a number of different crash reports. Here below are two examples: Problem Details Error: *** Fatal Error: Access Violation at 000000BC2DC1E830 Module: quartus_fit.exe Stack Trace: Other 0xbc2dc1e82f: Other 0xbc2dc1e6af: Other 0x1bf404d29ff: End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ------------------------------- Problem Details Error: *** Fatal Error: Module: quartus_fit.exe Stack Trace: Quartus 0x5fb4b: RaiseException + 0x6b (KERNELBASE) Quartus 0x26ad: __ExceptionPtrRethrow + 0x15d (MSVCP140) Quartus 0x19cfe: tbb::detail::r1::current_context + 0x277e (tbb12) Quartus 0x19d78: tbb::detail::r1::current_context + 0x27f8 (tbb12) Quartus 0x17695: tbb::detail::r1::current_context + 0x115 (tbb12) Quartus 0xa2567: FDRGN_EXPERT::run_place_flow + 0xd17 (fitter_fdrgn) Quartus 0xa0018: FDRGN_EXPERT::run_place + 0x188 (fitter_fdrgn) Quartus 0x95135: FDRGN_EXPERT::place + 0x195 (fitter_fdrgn) Quartus 0x2c120: fit2_fit_place_auto + 0xc0 (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x4e6b: fit2_fit_place + 0x33b (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x230ac: qexe_evaluate_tcl_script + 0x66c (comp_qexe) Quartus 0x21be9: qexe_do_tcl + 0x8f9 (comp_qexe) Quartus 0x2a1ad: qexe_run_tcl_option + 0x6cd (comp_qexe) Quartus 0x4119f: qcu_run_tcl_option + 0x6ef (comp_qcu) Quartus 0x29969: qexe_run + 0x629 (comp_qexe) Quartus 0x2abd6: qexe_standard_main + 0x266 (comp_qexe) Quartus 0xbd32: qfit2_main + 0x82 (quartus_fit) Quartus 0x28708: msg_main_thread + 0x18 (ccl_msg) Quartus 0x29912: msg_thread_wrapper + 0x82 (ccl_msg) Quartus 0x2b063: mem_thread_wrapper + 0x73 (ccl_mem) Quartus 0x265df: msg_exe_main + 0x17f (ccl_msg) Quartus 0xcfab: __scrt_common_main_seh + 0x10b (quartus_fit) Quartus 0x1259c: BaseThreadInitThunk + 0x1c (KERNEL32) Quartus 0x5af37: RtlUserThreadStart + 0x27 (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ----------------------------- this happens with every design and with Arria10, Stratix 10 and also Agilex 7. The only way to avoid these Quartus crashes is to run the fitter in Windows "Efficiency Mode", but that makes fitting time more or less double. Any hints?
Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.
Hello sir , i am also facing same kind of problem. when i am debugging my code , it working fine and i can access the EPCQ64A but when i run the code in standalone mode it, code works but cannot access the memory or write inside epcq64a. I have quartus prime standard edition 23.1 with license of both NiosII and NiosV. I am using 10CL055YU484I7G and niosv/g as my processor .This whole projects works fine with NiosII processor. but now i want to migrate to NiosV. Kindly help me out.
Different FPGA model shows: DEV-AGM039EA
Dear Altera Team, Thank you for your support. We have received the following inquiry from our customer regarding the development kit DK-DEV-AGM039EA. When checking the device using the tool, the FPGA device recognized by the tool appears to be different from the device listed in the catalog. Catalog device: **AGMF039R47A** Device detected by the tool: **AGME039R47A** Could you please confirm whether the correct FPGA device is implemented on this development kit? Additionally, the customer is currently conducting evaluation work with a target completion date of **March 20**. However, since the FPGA device appears to be different, the sample design for the evaluation board does not run properly. Along with confirming the FPGA device difference, could you also advise whether a **sample design compatible with AGME039R47A** is available? Your advice would be greatly appreciated. Kind regards, Takashi T4908715
R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hello, I am implementing a custom soft PCIe/CXL link layer and LTSSM using R-Tile Avalon Streaming IP in PIPE Direct mode, configured as x16. At the moment, link training does not reliably move forward because some lanes receive valid COM/K-code alignment, but the following ordered-set symbols are corrupted. Environment Device / board: AGIB027R29A IP: R-Tile Avalon Streaming FPGA IP for PCI Express Mode: PIPE Direct Link width: x16 Current focus: Gen1 training / Polling / Configuration Custom implementation: custom LTSSM custom symbol lock using COM (K28.5) custom TS1/TS2 decode logic Symptom In Polling.Active and Polling.Configuration , I can see that some lanes captures/decodes TS1/TS2 correctly, but some lanes do not. For example, in the attached SignalTap screenshot: Lane 9 appears to decode the TS2 sequence correctly. Lane 8 shows COM (K28.5) and PAD (K23.7) correctly, but the symbols after that are unstable / corrupted. From the screenshot: Lane 9 example: K28.5, K23.7, K23.7, D24.0, D30.0 D00.0, repeated Lane 8 example: K28.5, K23.7 are visible, but the following TS2 fields fluctuate and do not remain valid/stable. So it looks like: COM-based symbol lock is working at least partially but after COM/PAD, the ordered-set contents on some lanes(random) are corrupted before my soft IP can decode them correctly To verify whether this was caused by my own logic, I captured the affected lanes directly in SignalTap using the first raw 10-bit RX data from the PIPE Direct IP (`ln*_pipe_direct_pipe_rxdata_o`), before any symbol lock/decoding stage in my soft IP. I searched for the COM symbol directly in this raw 10-bit stream and confirmed that the corruption is already present at the PIPE Direct IP output. So this does not appear to be caused by my combinational decode logic; the raw RX data delivered by the IP is already corrupted on those lanes. What I already checked I already checked the following items carefully: Gen1 rxdata interpretation I only decode valid 10-bit portions for Gen1 I do not interpret the don't-care bits in rxdata[31:10] and rxdata[63:42] rxdatavalid qualification TS decode / symbol shift only happens when rxdatavalid0/1 are valid Sampling clock SignalTap capture is done in the corresponding lane RX clock domain not with a shared TX/fabric clock Reset sequence pld_pcs_rst_n_i release is gated after per-lane tx_transfer_en_o I also reviewed cdrlock2data, reset_status_n, phystatus, powerdown sequencing Deskew-related status active channels are detected Current question At this point, I suspect one of the following: lane-specific analog/RX quality issue inside or before PIPE Direct output lane-specific reset/power-up timing issue internal alignment / deskew behavior that I am misunderstanding some required PIPE Direct control/sideband setting that I am missing What I would like to ask In PIPE Direct x16 Gen1, if one lane shows valid K28.5 / K23.7 but the following TS2 symbols are corrupted, what should I check first on the R-Tile side? Are there any lane-specific PMA / RX / PIPE Direct controls that should be reviewed for this symptom? Is there any recommended way to determine whether this is: a true lane analog/RX problem, a deskew/alignment issue, or a reset/bring-up sequence issue? Are there any known recommendations for validating lane integrity directly at the PIPE Direct output during Polling.Configuration?PIPE Direct Reset Release Sequence
Hello, I am debugging R-Tile Avalon Streaming FPGA IP for PCI Express in PIPE Direct mode on an Agilex 7 device. My goal is a custom PCIe/CXL soft controller. I was originally targeting x16, but I am currently reducing the setup to x1 for bring-up/debug. I have questions about the PIPE Direct Reset Release Sequence (Figure 50). Clock domain for reset release control It is not clear to me when ln0_pipe_direct_pld_tx_clk_out_o becomes valid enough to be used for control sequencing. Should lnX_pipe_direct_pld_pcs_rst_n_i be released(Step 4 in Figure 50) by logic clocked with ln0_pipe_direct_pld_tx_clk_out_o after lnX_pipe_direct_tx_transfer_en_o (Step 3 in Figure 50)is observed, or is it acceptable to control this sequence from another stable FPGA system clock domain with synchronization? SignalTap trigger for reset release debugging I tried using ln0_pipe_direct_pld_tx_clk_out_o as the SignalTap clock and triggering on the first rising edge of lnX_pipe_direct_phystatus_o(Step b in Figure 50)during DETECT, but I cannot reliably capture that pulse. What is the recommended trigger/event to verify that the reset release sequence is operating correctly in hardware? Missing phystatus_o before cdrlockstatus_o in P0 From Figure 50, I expected a phystatus_o pulse (Step g in Figure 50)in the P1 power state before cdrlockstatus_o asserts. In my test, that phystatus_o pulse does not appear, cdrlock2data_o never becomes 1(Step m in Figure 50), but reset_status_n_o still goes high (Step n in Figure 50), in conclusion the raw RX data from PIPE Direct IP appears corrupted/unstable. Is there a known reason this can happen? Also, I would like to verify this reset release sequence in RTL simulation, not only on hardware. However, for PIPE Direct mode, there are no example design available, so at the moment I do not have a way to validate this behavior with RTL simulation. If anyone has experience debugging Figure 50 on real hardware, I would appreciate guidance. Thank you.MAX10 Dual Configuration
I am using the MAX10 Dual Configuration. The device settings in the Quartus are shown in the image below. The settings for the generation of the .pof file and the .rpd files are shown below: The CONFIG_SEL file is set by a jumper via a 10K resistors either high or low. I can update the flash memory, but it appears that both CFM0 and CFM1 are programmed with the same image. Also, when I use JTAG to program CFM0 and CFM1 with two different images, it seems that the programming of CFM1 overwrites the CFM0 image. What could be wrong?
Cyclone I (EP1C3) Configuration Issues: Sequence and Environment Dependent Failures
Hi, I am aware that Cyclone I is a legacy device, but we are maintaining a long-life product and would appreciate any insights from experienced engineers. [ Environment and System Configuration ] I am maintaining a legacy system developed 20 years ago. I am facing inexplicable configuration and boot issues that depend on the programming environment (PC/location) and the sequence of file versions written. FPGA: Cyclone EP1C3T100C8 Configuration Device: EPCS4SI8 Software: Quartus II 9.1sp2 Web Edition OS: Windows 7 Professional SP1 Download Cable: Terasic USB Blaster Setup Locations: A) Design Office (Me): 2 boards (with JTAG access), PC "A" B) Factory: Multiple boards (AS mode only, no JTAG), PC "B" [ Description of Phenomena ] Phenomenon 1: Spontaneous Mode Change (Factory / 2-year-old board) In Dec 2025, a board worked correctly. In March 2026, it behaved as if it were in a different operation mode. Details: The mode is hard-wired within the internal logic and should not transition. Action: Re-writing the same POF file restored normal operation. Note: This happened within only a few months of storage. Phenomenon 2: Failure to Transition from Initial State (Office / 10-year-old board) A JTAG-enabled board was stored for one year. Now, it fails to function even with known-good files. Details: Even writing the original SOF that worked in Feb 2025, the FPGA stays in its initial state and fails to perform state transitions. Quartus reports "Success," but the hardware logic does not execute. Phenomenon 3: Sequence-Dependent Success (Factory / New 2026 boards) When writing a Dec 2025 POF to five new boards: Behavior A (3 boards): Initially stayed in the initial state. However, after writing an older Feb 2025 POF, they started working. Over-writing them with the Dec 2025 POF then resulted in success. Behavior B (2 boards): Worked perfectly from the first attempt. Why would a specific version history be required for some boards to work? Phenomenon 4: Lack of Compatibility (Office vs. Factory) A POF verified to work when written by Factory PC (B) does not work when written by Office PC (A). Details: When written by PC A, the board stays in the initial state and fails to transition, identical to Phenomenon 2. [ Discussion and Questions ] Incomplete Initialization: Is it possible for the configuration to reach "Done" while internal registers fail to initialize correctly due to power supply slew rates or noise? Silent Data Corruption: Are there known issues with Quartus 9.1sp2 and Terasic Blasters where bit errors occur during programming without being caught by the verification process? EPCS4 Residual State: Why would writing an older version "prime" the board to accept a newer version? Could this be related to EPCS sector erase issues? Since these are legacy devices, any insights would be greatly appreciated. Regards, HKana17
EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)
Hi Altera Support Team, We are trying to install two Micron 32GB 2Rx4 RDIMMs on the Agilex 7 I-Series FPGA Development Kit, PCB Rev. A (DK-DEV-AGI027R1BES), and would like to confirm the correct EMIF pin assignment for this board. We have already enabled these two DIMMs on a DK-DEV-AGI027RBES board. However, we noticed that the golden pin assignment provided in the installer package appears to be the same for both FPGA boards. Since these two boards use different power solutions and different pin assignments, we believe the DK-DEV-AGI027R1BES should require a different EMIF pin assignment. At the moment, we have not been able to find the correct pin assignment for the DK-DEV-AGI027R1BES board. Could you please provide this information, or point us to the appropriate documentation? Best regards, Yang
