Trouble Getting started with Stratix 10 SOC
I've recently purchased a Stratix 10 SOC board for experimentation. Although I've got the out of the box GHRD loaded and working, I've been struggling to get ANY changes I've made properly loaded into it. For example just changing the sysid in qsys and recompiling, generating the .sof and then converting it to an .rbf and loading it in uboot causes an error: command 'load' failed: Error -110 I understand that the Stratix 10 has a lot of security to ensure the bitstreams are validated and consistent, etc, and I'm sure this is useful in some contexts. But is there a way to disable some of this security to help a beginner get to the point where they can quickly start seeing designs loaded and working? NOTE: I'm not a total beginner. I've been experimenting with the Cyclone family (DE10-Nano, etc) for a few years now. But the Stratix is obviously a whole other level. Thanks,
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
License Server new License File
Hallo, I have to set up a new license server on a new machine. I am capable of doing this; my problem is the license itself. I only have the old license.lic from the old machine — but due to the corporate change from Intel to Silver Lake I can't reach any of the former Intel contacts anymore. I am also unsure if the "Intel® FPGA Licensing Support Center" is still responsible. Any insights on what the procedure is and who to contact? Viele Grüße Oliver Schumann Siemens AG, Nürnberg
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
MAX 10 FPGA POR trip Levsl and tRAMP
I am intending to use a 36 pin count dual power supply MAX 10 part for a lower power application. From Fig 3 of UG-M10PWR (pasted below), nStatus is asserted when POR trip level is met within tRAMP. The battery for my application may have a longer ramp up time than tRAMP (10 msec for my part). What is the consequence of this. Will device not come out of reset if tRAMP condition is not met? Are there any workarounds for this?MAX10 fiftyfivenm encrypted module
Hi, I use GPIO lite IP to generate an ODDR, it needs the fiftyfivenm_ddio_out/io_obuf/in_ibuf modules. But in fiftyfivenm_atoms.v, it also call the encrypted file as blew, fiftyfivenm_ddio_out_encrypted/fiftyfivenm_io_obuf_encrypted/fiftyfivenm_io_ibuf_encrypted. If I want to use other simulator (not quartus-sim or modelsim), how do I simulate it? Thanks, DoverHsu
PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit
Hello, I recently got this dev board, and I was trying to load the PCIe example design up on the board however it seems that it is not working, as it fails to enumerate! I followed the instructions on the PDF guide, and I also have my switches set correctly, however it is not working unfortunately! I assume that its an issue with the MAX 10 file, however the only other one I found on the forum is incompatible with my board! I also have the switches set correctly (SW13.1 ON), but any idea or thing helps! Thanks in advance for the help!Can not program Agilex-5 device
Quartus programmer stops at 44% with error: Error(18950): Device has stopped receiving configuration data Error(18948): Error message received from device: Bitstream error. (Subcode 0x0093, Info 0x00000003, Location 0x00000800) Error(18948): Error message received from device: Device specification (SKU ID) of the target device used in bitstream generation does not match physical device. Error(23925): Debug suggestion: Verify that the device OPN selected in Quartus Prime matches exactly with the OPN of your hardware device. Error(209012): Operation failed What can be the cause, the device is selected correctly.Unable to Generate .sof File in Quartus Prime Standard Edition 15.1 – 30‑Day Evaluation Mode
Hello, I am using Quartus Prime Standard Edition v15.1.0.185 in 30‑day evaluation mode. My goal is to compile a design and generate a .sof file during the evaluation period, but I am unable to produce the .sof file after full compilation. When Quartus starts, I get the following evaluation window: The option I am using is: Continue the 30‑day evaluation period with no license file (no device programming file support) But in the evaluation mode, Quartus completes compilation, but does not generate the .sof programming file. My Questions: Is it possible to generate a .sof file during the 30‑day free evaluation period? If not, what is the correct way to enable programming file support during the trial? Does the Standard Edition evaluation require a separate free trial license to allow .sof generation? If a temporary license is needed, where can I request/download it for Standard Edition v15.1.0.185? System Details: Quartus Prime Standard Edition 15.1.0.185 Device : Cyclone V 5CSEBA5U23I7 Any guidance would be greatly appreciated, as I need to confirm whether the evaluation period supports .sof file generation or if a license is mandatory. Thank you. Regards, Prateek
Arria 10 SoC – USB devices always enumerating as Full-Speed (Yocto 4.1, dwc2)
Hello, My name is Ángel Manuel and I am currently working with an Intel SoC FPGA Arria 10. I am trying to connect an Intel RealSense SR300 camera to my system, but I am experiencing USB speed negotiation issues. Environment: Platform: Intel SoC FPGA Arria 10 OS: Linux (custom image built with Yocto 4.1 Langdale) USB driver: dwc2 librealsense built with -DFORCE_RSUSB_BACKEND=ON When I connect the RealSense SR300 camera, the USB link does not negotiate correctly and the device is always enumerated as Full-Speed (12M) instead of High-Speed or SuperSpeed. At first, I suspected a problem with the USB 3.0 connector of the SR300. However, when I tested with a standard USB 2.0 webcam, I observed exactly the same behavior: the device is still enumerated only as Full-Speed (12M). This suggests the issue is likely related to the USB controller configuration on the Arria 10 rather than the camera itself. System Output lsusb -t: /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=dwc2/1p, 480M |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=, 12M |__ Port 1: Dev 2, If 1, Class=Audio, Driver=, 12M |__ Port 1: Dev 2, If 2, Class=Audio, Driver=, 12M dmesg: [ 204.765768] usb 1-1: new full-speed USB device number 2 using dwc2 Yocto local.conf: MACHINE = "arria10" DISTRO_FEATURES:append = " systemd vfat" DISTRO_FEATURES:remove = " sysvinit" VIRTUAL-RUNTIME_init_manager = "systemd" IMAGE_INSTALL:append = " kernel-module-uvcvideo" KERNEL_MODULE_AUTOLOAD += "uvcvideo" IMAGE_INSTALL:append = " \ packagegroup-core-boot \ pciutils \ usbutils \ v4l-utils \ i2c-tools \ librealsense2 \ " EXTRA_OECMAKE:append:pn-librealsense2 = " -DFORCE_RSUSB_BACKEND=ON"
