USB Blaster not available
Hi, The USB blaster programs my Max 10 device fine until I plug in another usb cable that controls a Rabbit micro-controller (FTI device) I am interfacing to the MAX10 device. When this happens I get the message "No Hardware" under hardware setup. I amusing Quartus 24.1 std. I have tried the following: Changed the com port on the rabbit serial connection. Plugged the two cables into two separate powered USB hubs Reinstalled the USB blaster driver. Re-booted several times Tried a different USBB blaster device Has anyone got any ideas? I need to run signal tap at the same time as the rabbit development program so need both working at the same time. Thanks
Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.nSTATUS is sometimes asserted low during Agilex-F configuration when operating in PMBus slave mode
I am using Passive Avalon-ST 16 mode to configure the Agilex-F device. There is external PMBus master to run the ARA process of the SmartVID protocol immediately after sensing ALERT low signal. Sometimes when trying configuration after power up (starting the process by asserting nConfig low), nStatus goes low before reaching the point of ALERT signal going low. Retry of the configuration after such failure always succeeds. Any idea? Thanks, Itzik
Requesting you to resolve the programming on Cyclone V SX SoC Development Kit
Board: Cyclone V SX SoC Development Kit FPGA: 5CSXFC6D6F31 Quartus: Prime Lite 20.1 (Windows 11) JTAG Cable: USB-Blaster II Observed JTAG devices: SOCVHPS 5M1270ZF324 Expected device missing: 5CSXFC6D6F31 SW4 set to FPGA-only, SW2 all OFF, power-cycled Conclusion: FPGA JTAG appears isolated / held in reset by board controllerRequesting you to resolve the programming and GUI issues on Cyclone V SX SoC Development Kit
Board name: Cyclone V SX SoC Development Kit FPGA Device: 5CSXFC6D6F31 (Cyclone V SX SoC) JTAG interface: On-board USB-Blaster II (J23) Software: Intel Quartus Prime lite 20.1 OS: windows 1.When we are attempting to program the FPGA using Quartus programmer, the operation fails with, Status: Progress Failed. Although the USB-Blaster II cable is detected, the FPGA does not program successfully. 2.when we click on the auto detect, it is showing "The auto detected device chain does not match the programming Device list. Do you want to update the programmer's device list, overwriting any existing settings". 3.we are trying to test the Board system (Built-in-test). As per the Datasheet we are referring, GUI need to open in the folder. But it is showing BoardTestSystem.bat not found, GUI does not open, examples folder missing or incomplete. can you please resolve above the issues we are facing now.
Cyclone10LP Remote System Upgrade
Hi guys, I am working on implementing Remote System Upgrade for my Cyclone 10LP FPGA, which loads its configuration data from an external flash device (MT25QL128). I've reviewed multiple documents on RSU and concluded that I need to have two broad sections in my design: firstly, a flash controller for writing configuration data to the flash device, and secondly, a remote update IP for switching between the factory and application image. (Please correct me if I misunderstood something) 1.) Now I've been facing a problem with finding a suitable IP for the flash controller section that can access the SPI pins with the flash device. I've tried using the generic serial flash interface IP, but it supports MT25* flashes with sizes above 256Mb only. So, is there any suitable IP for this purpose that supports both Cyclone10LP and MT25QL128? Or is it possible to write a state machine for this purpose and access those SPI pins through my design (which are normally not accessible)? 2.) The Remote Update IP again doesn't have MT25QL128 in its supported devices. Some sources suggest selecting Macronix flash device with a similar density in the parameter editor gui. Does that really work or are there any better alternatives? 3.) Also what does changing configuration mode to "Remote" in Quartus GUI actually do? Gives access to Flash SPI pins in some way? Looking forward to your responses, thanks.
