Cyclone10LP Remote System Upgrade
Hi guys, I am working on implementing Remote System Upgrade for my Cyclone 10LP FPGA, which loads its configuration data from an external flash device (MT25QL128). I've reviewed multiple documents on RSU and concluded that I need to have two broad sections in my design: firstly, a flash controller for writing configuration data to the flash device, and secondly, a remote update IP for switching between the factory and application image. (Please correct me if I misunderstood something) 1.) Now I've been facing a problem with finding a suitable IP for the flash controller section that can access the SPI pins with the flash device. I've tried using the generic serial flash interface IP, but it supports MT25* flashes with sizes above 256Mb only. So, is there any suitable IP for this purpose that supports both Cyclone10LP and MT25QL128? Or is it possible to write a state machine for this purpose and access those SPI pins through my design (which are normally not accessible)? 2.) The Remote Update IP again doesn't have MT25QL128 in its supported devices. Some sources suggest selecting Macronix flash device with a similar density in the parameter editor gui. Does that really work or are there any better alternatives? 3.) Also what does changing configuration mode to "Remote" in Quartus GUI actually do? Gives access to Flash SPI pins in some way? Looking forward to your responses, thanks.
IS25LP064A interface with Cyclone V HPS
Hi all, has anyone tried accessing serial NOR flash IS25LP064A using QSPI driver within hwlib ? I have successfully performed initialisation, setup device configuration. The problem is that a read attempt (Normal Read and Fast Read) after executing erase sequence returns all zeros instead of all ones. has anyone else faced similar issue ? Best Regards Naresh
Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
We are trying to use the Infineon S25FS512S QSPI NOR Flash with Cyclone 10 GX in Active Serial x4 (AS x4) configuration by creating a Custom Flash Definition based on AN229767. JTAG programming completes successfully, but FPGA configuration fails in AS x4 mode. We have performed extensive debugging and would like to understand whether this is a supported use case or if there are any known limitations. Observations Flash Programming JTAG programming completes successfully. Flash verification completes successfully. Configuration Behavior Active Serial x1 configuration works correctly. Active Serial x4 configuration fails. The FPGA successfully issues the RDID (0x9F) command. The FPGA then attempts to read the Boot Information from address 0x00000000. Logic Analyzer Observation During AS x4 configuration, the FPGA issues the EBh (Quad I/O Read) command. According to the Infineon S25FS512S datasheet, the expected transaction is: EBh → 4-byte Address → Mode Byte (8 bits) → Dummy Cycles → Data However, the captured waveform shows: EBh → 4-byte Address → Dummy Cycles → Data No Mode Byte is observed between the address and dummy cycles. Based on the S25FS512S command protocol, this could cause the flash to interpret the transaction differently and return misaligned data. We would like Altera to confirm whether this behavior is expected from the Cyclone 10 GX configuration controller. Additional Information We reviewed AN229767, but could not find any mechanism in the Custom Flash Definition to configure or insert the Mode Byte required by the EBh command. We also observed that the Custom Flash Definition supports Read Register commands only for fixed register opcodes and does not appear to support RDAR (0x65) with a register address. Questions Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command? If not, is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer? Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition? Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference? Environment FPGA: Cyclone 10 GX Flash: Infineon S25FS512S Configuration Mode: Active Serial x1 (working), Active Serial x4 (failing) Programming Method: Quartus Programmer using a Custom Flash Definition based on AN229767 We would appreciate any guidance, clarification, or a reference implementation for using the S25FS512S with Cyclone 10 GX in Active Serial x4 mode.Build error on tutorial, missing CMakeLists.txt
I previously built the tutorial helloworld project with no errors. I then made small changes to the BSP generation settings and re-generated the BSP. I did not try to re-import the BSP code into my project because it was already imported. I immediately re-built the whole project in RiskFree, I get the following error: CMake Error: The source directory "C:/fpga_projects/an985/helloworld" does not appear to contain CMakeLists.txt. I verified that there is no CMakeLists.txt file in the folder C:/fpga_projects/an985/helloworld. This is because that folder contains a subfolder Software which has subfolders for hal_app and hal_bsp, each of which contains their own CMakeLists.txt file. Where would I change a file or a configuration so that the build knows there there are two subprojects, each with their own CMakeLists.txt file? See attached screenshot of folders and files.
FPGA simulation and real HW behavior discrepancy
Dear Altera Quartus 18.1 sim lib could try 20.1 or newer but not sure this is due to Quartus version as it is sim lib. I am encounter an unexplainable experiment result that contradicts simulation and real HW. Background when interfacing a DQS DQ readout a IDDR with CCD sync flops are used. For these primitives, it should expected 1 + 2 and clock +ve edge should expect data push out. [A] This can simply considered as early push out but it should not act as such. With the use of "__ALTERA_STD__METASTABLE_SIM" we expected some metastable on the output. [B] Now things are more reasonable where 2 +ve clocks are expected. If we consider a full data w/o xx, things become unrecognizable. [C] The most interesting part when apply on real HW, it do produce correct data and the latencies do obeyed. altddio_in#( .intended_device_family ( "Cyclone IV E" ), .invert_input_clocks ( "ON" ), .lpm_hint ( "UNUSED" ), .lpm_type ( "altddio_in" ), .power_up_high ( "OFF" ), .width ( 8 ) )ddi_d_l( .aclr (reset), .datain (foo[7:0]), .inclock (bar[0]), .dataout_h (foobar_h[0+:8]), .dataout_l (foobar_l[0+:8]), .aset (1'b0), .inclocken (1'b1), .sclr (1'b0), .sset (1'b0) ); + altera_std_synchronizer_bundle#( .width (foobar_bw *2), .depth (2) )async_flops( .clk (clock), .reset_n (~reset), .din (foobar), .dout (foobar_ccd) );
