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ModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。pw batch cancellation refund money 09196,427102
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Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi, I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be: ARM/HPS writes input data -> HPS2FPGA bridge -> FPGA-side DDR4 via EMIF_IO96B_DDR4COMP FPGA IP reads input data from FPGA-side DDR4 FPGA. IP computes and writes result back to FPGA-side DDR4 ARM/HPS reads result back from FPGA-side DDR4 via HPS2FPGA My current Platform Designer connection is roughly: HPS hps2fpga master -> EMIF_IO96B_DDR4COMP AXI memory-mapped slave FPGA accelerator memory port -> same EMIF_IO96B_DDR4COMP EMIF pins -> external DDR4 The EMIF configuration and DDR4 pin assignments are matched carefully against the example design: /agilex5e_installer_package/examples/bts_emif/bts_ddr4_2b downloaded from the agilex5e installer package. I also tested the original bts_ddr4_2b style flow in the example using: JTAG -> pattern adaptor -> EMIF -> DDR4 and DDR4 read/write tests pass without errors. So the FPGA-side EMIF DDR4 calibration/pattern test appears to work. However, when I try to access the same FPGA-side DDR4 from Linux on HPS through the HPS2FPGA bridge using devmem2, the access fails badly. For example, accessing the HPS2FPGA mapped address causes a bus error / fatal SError. One example log: root@agilex5dka5e065bb32aes1:~# devmem2 0x40000000 w /dev/mem opened. [ 1017.877669] SError Interrupt on CPU2, code 0x00000000be000011 -- SError [ 1017.877707] CPU: 2 PID: 791 Comm: devmem2 Not tainted 6.12.19-altera-g7b497655d942 #1 [ 1017.877717] Hardware name: SoCFPGA Agilex5 SoCDK (DT) ... [ 1017.877814] Kernel panic - not syncing: Asynchronous SError Interrupt ... Bus error For comparison, I connected the same HPS2FPGA bridge to an on-chip memory in the FPGA fabric. Accessing that on-chip memory from HPS with devmem2 works correctly. So the HPS2FPGA bridge itself seems functional. Current observations: HPS2FPGA -> on-chip memory works. JTAG -> pattern adaptor -> EMIF -> DDR4 works. EMIF calibration appears to pass. HPS2FPGA -> EMIF DDR4 causes SError / bus error / Linux kernel panic. Here is my current Platform Designer connection. In the screenshot, you can see that I copied over the EMIF-driving logic from the installer package. For emif_axi4, one connection goes to my IP’s memory port, and the other goes to the HPS hps2fpga interface, although that HPS connection is not shown in this screenshot. Does anyone have any clues about what might be wrong here? Is this expected to work, or is this use case currently not supported, i.e. HPS reading/writing data directly to FPGA-side DDR through HPS2FPGA while an FPGA IP also accesses the same DDR through the EMIF AXI4 interface? If any additional files would be helpful, I can provide them. Thank you in advance!
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
Cold Temperature Issue
Hallo, We used the Agilex5 device in AS configuration connect to external QSPI Flash. We apply Smart VID interface at the device demands. When we perform Cold power up at -40C the device is not configured, It seemed the device is not output from the POR, No traffic on the PMBus. Power sequence and voltage ramp time and levels are OK. Please advise Thanks Asaf
Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.Not received badge verilog hdl basics after completion .
No idea which forum it is relevant for, just completed verilog hdl basics my first course on intel. Was excited to get the badge but any option to avail the same is unavailable what must I do to get the badge for the same? Please someone let me know,
