DK-DEV-AGI027RBES CXL Type-3 example remains in reset and is not detected by host
Hi, I have several Agilex 7 FPGA I-Series Development Kits with serial numbers 8100035 and 8020138. My goal is to run the boards as CXL Type-3 devices and verify that they can be enumerated by the host. I am currently debugging board 8020138 with the following setup: Board: DK-DEV-AGI027RBES FPGA: AGIB027R29A1E2VR3 Power configuration: Power Solution 2 Quartus Prime Pro: 24.3 Connection: PCIe edge connector Design: CXL Type 3 with DDR4 Link width: CXL x16 Number of slices: 2 PLD clock: 400 MHz Reference clock mode: Common Refclk source is global clock: Enabled The board can successfully enumerate as a normal PCIe endpoint when using the pcie_ed example design included in: agilex_agib027r29a1e1vb_fpga_revc_v24.3b194_v1.1 However, when I generate and compile the RBES CXL Type-3 DDR4 example design, the host cannot detect the device and it does not appear in lspci. I added JTAG debug registers and Signal Tap probes. The observed status is: config_done = 1 pll_lock = 1 sip_rst_n = 0 cxl_warm_rst_n = 0 cxl_cold_rst_n = 0 ip2hdm_reset_n = 0 ip2cafu_avmm_rstn = 0 ip2csr_avmm_rstn = 0 pf0_bus_master_en = 0 pf0_memory_access_en = 0 pf0_msix_enable = 0 The fabric heartbeat counter(refclk4) is running, so FPGA configuration and the debug fabric clock are working. However, the CXL cold, warm, and SIP resets never deassert, and host enumeration never starts. Could you please confirm: Are these CXL IP settings correct for board 8020138, Power Solution 2, and the PCIe edge connector? For CXL x16 with two slices, must both refclk0 and refclk1 be active? What conditions control cxl_cold_rst_n, cxl_warm_rst_n, and sip_warm_rstn_o? How can I observe the physical PERST# status, R-Tile reset status, PHY initialization status, LTSSM state, and link-up status? Should Enable PIPE Mode Simulation be disabled for hardware operation? Is 400 MHz the correct PLD clock frequency? Is there a known-good CXL Type-3 DDR4 example project or SOF for DK-DEV-AGI027RBES with FPGA AGIB027R29A1E2VR3? Are there any required Quartus 24.3 patches for this board and CXL IP? The normal PCIe example works, but the CXL example remains in reset. This suggests the issue may be related to the CXL IP configuration, reference-clock/reset requirements, or the generated example-design constraints. I can provide the IP configuration, QSF/SDC files, Signal Tap captures, compilation logs, and host logs if needed. Thank you. Best regards, Jeffrey
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