How to set initial register values after powerup
Hello, A topic that has been written about a few times. But how to make sure a specific register value is set, after the FPGA has powered up? I have learned that setting an initial value have no effect other than in simulation. I have a specific case where I want a specific value to by 10. So far I have made it so, that I use an external reset signal/pin to force all my registers into their "start" state. But is there a more clever way that this can be done in VHDL instead. I use Cyclone IV and have read that some Altera devices have this "Reset Release" IP avilable that do a reset after powerup. Thank you.
VID setting is incorrect for Stratix 10. I am using MP2975GU as the voltage regulator.
Hi everyone, The circuit board for the 1SM21CHU1F53E2VG we design ourselves is stuck when programming and loading the .sof file. The system log said that : Device has stopped receiving configuration data Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00200008, Location 0x00001800) Error message received from device: Detected a PMBUS error during configuration. Debug suggestion: Potential errors: VID setting is incorrect in the Intel Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. I configure the Power Management & VID Setting follow the files i attached. The MPS software detach the address is 7C so I set the Slave address 0 is "7C". I also set the Slave devices type is Others and some coefficients follow the Altera Guildelines but it still stuck at between 9 - 11%. Actually , we want turn off the VID Mode because my board is not using the SmartVID with .ini files added : force_vid_off=on. I dont know whether we have to redesign the board with suitable Voltage regulator ,examples is LTM4677 or not. Please suggest for me some possible solutions and help me because I changed everything about 3 weeks ago but no results.
NOR Flash IC programming using 3rd party Programmer
We have observed that programming the NOR Flash using the Altera USB‑Blaster via JTAG behaves differently compared to programming the same Flash device using a third‑party gang programmer. We have created an RPD file as mentioned in the below intel document, tutorial-write-raw-programming-data-rpd-into-flash-devices.pdf Observations During NOR Flash Programming 1.When the fresh NOR Flash IC is programmed using a third‑party programming tool and subsequently mounted on the Base Card, the card fails to boot. 2.However, the RPD image functions correctly when the following programming sequence is followed: -> Program the fresh NOR Flash of the CFPG A using the Altera USB Blaster via JTAG. -> Erase the NOR Flash. -> Reprogram the same RPD image, generated as per the procedure defined in the referenced document. When the above sequence is followed, the card boots and operates as expected. We would appreciate your input on whether any additional steps are required when using third‑party programmers to ensure compatibility with the FPGA boot mechanism.
USB Blaster not available
Hi, The USB blaster programs my Max 10 device fine until I plug in another usb cable that controls a Rabbit micro-controller (FTI device) I am interfacing to the MAX10 device. When this happens I get the message "No Hardware" under hardware setup. I amusing Quartus 24.1 std. I have tried the following: Changed the com port on the rabbit serial connection. Plugged the two cables into two separate powered USB hubs Reinstalled the USB blaster driver. Re-booted several times Tried a different USBB blaster device Has anyone got any ideas? I need to run signal tap at the same time as the rabbit development program so need both working at the same time. Thanks
Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.nSTATUS is sometimes asserted low during Agilex-F configuration when operating in PMBus slave mode
I am using Passive Avalon-ST 16 mode to configure the Agilex-F device. There is external PMBus master to run the ARA process of the SmartVID protocol immediately after sensing ALERT low signal. Sometimes when trying configuration after power up (starting the process by asserting nConfig low), nStatus goes low before reaching the point of ALERT signal going low. Retry of the configuration after such failure always succeeds. Any idea? Thanks, Itzik
