Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
Manual checksum verification of CFM0
I am working on some post-build scripting for generating firmware update programming files for the Max 10 series FPGA. My goal is to generate 2 separate files: POF file, for use with USB Blaster. Proprietary file, for use through a different communication channel. The POF file is easy; the file is basically auto-generated when you compile in Quartus. When loading the POF into the Quartus programmer software, it shows "Checksum" and "Usercode Checksum". The usercode checksum can also be found in the RPT file. So I have used my post-build scripting to make a copy of the POF file, with the usercode checksum appended to the POF filename. That is all working great and goal #1 is satisfied. I have been working on the proprietary file. In this case, I would be storing something that amounts to the raw data that will end up written to the CFM0 section of the FPGA. To get the raw data, I used quartus_cpf to generate RPD files from the compiled SOF file. The raw data can then make its way into the FPGA's CFM0 section through undisclosed means other than USB-Blaster. All of that is OK, but the problem I have is that I wish to use the SAME usercode checksum as the POF file for consistency, and I have not been able to figure out how to correctly calculate that. One thing that I did where I got close was, I added this argument to the quartus_cpf command when generating the MAP file: -o memory_map_file=on The MAP file generated shows a totally different checksum. However, when I do a simple 32-bit checksum on the RPD data (just adding all 32-bit words of the file and coming to a 32-bit result), it DOES exactly match the checksum in the MAP file. In summary: I want the consistency between one of the POF's checksums shown in Quartus Programmer, vs. what I can calculate from the raw RPD data. Since both methods of programming the FPGA should produce identical results, I want to be able to have the same checksum in both methods. How may I correctly use the RPD data to calculate the same checksum shown in Quartus programmer when loading the POF file?
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.Agilex 5 configuration via Avalon-ST x8 issues
I have a MAX10 device controlling the configuration of an Agilex 5 device (A5EC065BB23AI4S) set for Avalon-ST x8. We use the MAX10 to translate serial programming from our processor to AvalonST x8 for the Agilex 5. I am able to program both the MAX10 and Agilex 5 device via JTAG and verify we can talk to these devices via SPI busses in the hardware. For the configuration via the MAX10 we bring nCONFIG low and nSTATUS returns from the Agilex 5 low. We next bring nCONFIG back high and nSTATUS returns to high. We start the Avalon-St transfer but never see INIT_DONE go high. The odd thing is we also never see CONF_DONE go low even with nCONFIG low? Any idea what else to check? Below is a pic of the SDM_IO connections from the Agilex5 to the MAX10.
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
M9K utilization is different for the same RAM IP for two different projects.
I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects. The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks. For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below: The settings for the RAM-IP are as shown in the image below: Quartus Tool Version : Quartus 18.1 Standard FPGA Device : MAX-10 10M50DAF256I7G Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks. Thank you, Akhilesh.ASx4 Interface debug in MSEL=111 (JTAG mode)
Hi, could you, please, help me understand what is happening here: I am working with an Agilex3 FPGA (fuses are on factory default, no keys programmed, etc.) MSEL=111, so we are in JTAG mode I am trying to debug the NOR flash interface through Configuration Debugger / QSPI Controller and SFDP page. I have connected an oscilloscope. When I press Read button without QSPI Debug Session Activate button pressed, I see some NOR flash transactions on the oscilloscope and get back an Error 0x515 Unknown error and nothing is read in the SFDP window. So I try the QSPI debug session active way, and when I press it I get a lot of content but anything below the SFDP line in the tree structure is random at each read button press AND I do not see any NOR flash transaction at all on the ASx4 interface. (Did it several time, so yes, I did not forgot press the trigger active button.) So questions: is this an expected behavior? Copilot suggest that ASx4 interface is not initialized when MSEL=111 and I am reading some internal "garbage" If this is expected, should not the Quartus Programmer tool (which reads MSEL=111 correctly) warn me that I should not expect any meaningful output in this debug window? Is there any way to use the JTAG interface here as supposed: test the interfaces for problems? if yes, how?! (I stuck for a few more days/weeks with MSEL=111, so if that is the solution just let me know.) Thanks, Peter
How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Timing analyser reports CLKUSR at 125MHz but target system has 100MHz on this pin to accommodate AS in combination with transceiver calibration as per the manuals -- there doesn't seem to be any consequences as the project seems to run fine but is a bit unsettlingMAX10 FPGA IOs not entering Tri-state (Hi-Z)
Hello Team, I am using 10M16 FPGA and observed that the IOs are not getting tri-stated/ Hi-Z state after: The Reset is released through a switch / press button on "DEV_CLRN" pin, considering there is no .sof/ .pof code flashed. Hardware Configuration: "DEV_OE" pin is Grounded with 10K resistor. Reference: Intel® MAX® 10 Device Handbook - Combined Pin Name Pin Functions Pin Description Connection Guidelines DEV_OE Input, I/O This is a dual-purpose pin. Optional pin that allows you to override all tristates on the device. When this pin is driven low, all I/O pins are tristated. When this pin is driven high, all I/O pins behave as programmed. You can enable this pin by turning on the Enable device wide output enable (DEV_OE) option in the Quartus Prime software. Altera recommends you to tie the DEV_OE pin to GND when the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. You can also tie the DEV_OE pin to VCCIO or leave the DEV_OE pin unconnected provided that the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. When you leave the DEV_OE pin unconnected, Altera recommends you to set the DEV_OE pin to input tristate with a weak pull-up.
