EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)
Hi Altera Support Team, We are trying to install two Micron 32GB 2Rx4 RDIMMs on the Agilex 7 I-Series FPGA Development Kit, PCB Rev. A (DK-DEV-AGI027R1BES), and would like to confirm the correct EMIF pin assignment for this board. We have already enabled these two DIMMs on a DK-DEV-AGI027RBES board. However, we noticed that the golden pin assignment provided in the installer package appears to be the same for both FPGA boards. Since these two boards use different power solutions and different pin assignments, we believe the DK-DEV-AGI027R1BES should require a different EMIF pin assignment. At the moment, we have not been able to find the correct pin assignment for the DK-DEV-AGI027R1BES board. Could you please provide this information, or point us to the appropriate documentation? Best regards, Yang
Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.LVDS support on Agilex 7
HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?
Max10 FPGA Programming with .pof file
Hello All, we are using 10M16 FPGA in our design. Observation is that we are able to program the FPGA using .sof every time but .pof gets installed on most boards 8/10 times and on few boards fails every time. Could you recommend the Hardware requirement for .pof flashing? (We are using USB Blaster II). With .pof, erase happens 100%. Blank check/ Program fails. Thanks and Regards
Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required
Quartus 25.1 usually crashes during fitter, with a number of different crash reports. Here below are two examples: Problem Details Error: *** Fatal Error: Access Violation at 000000BC2DC1E830 Module: quartus_fit.exe Stack Trace: Other 0xbc2dc1e82f: Other 0xbc2dc1e6af: Other 0x1bf404d29ff: End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ------------------------------- Problem Details Error: *** Fatal Error: Module: quartus_fit.exe Stack Trace: Quartus 0x5fb4b: RaiseException + 0x6b (KERNELBASE) Quartus 0x26ad: __ExceptionPtrRethrow + 0x15d (MSVCP140) Quartus 0x19cfe: tbb::detail::r1::current_context + 0x277e (tbb12) Quartus 0x19d78: tbb::detail::r1::current_context + 0x27f8 (tbb12) Quartus 0x17695: tbb::detail::r1::current_context + 0x115 (tbb12) Quartus 0xa2567: FDRGN_EXPERT::run_place_flow + 0xd17 (fitter_fdrgn) Quartus 0xa0018: FDRGN_EXPERT::run_place + 0x188 (fitter_fdrgn) Quartus 0x95135: FDRGN_EXPERT::place + 0x195 (fitter_fdrgn) Quartus 0x2c120: fit2_fit_place_auto + 0xc0 (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x4e6b: fit2_fit_place + 0x33b (comp_fit2) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x230ac: qexe_evaluate_tcl_script + 0x66c (comp_qexe) Quartus 0x21be9: qexe_do_tcl + 0x8f9 (comp_qexe) Quartus 0x2a1ad: qexe_run_tcl_option + 0x6cd (comp_qexe) Quartus 0x4119f: qcu_run_tcl_option + 0x6ef (comp_qcu) Quartus 0x29969: qexe_run + 0x629 (comp_qexe) Quartus 0x2abd6: qexe_standard_main + 0x266 (comp_qexe) Quartus 0xbd32: qfit2_main + 0x82 (quartus_fit) Quartus 0x28708: msg_main_thread + 0x18 (ccl_msg) Quartus 0x29912: msg_thread_wrapper + 0x82 (ccl_msg) Quartus 0x2b063: mem_thread_wrapper + 0x73 (ccl_mem) Quartus 0x265df: msg_exe_main + 0x17f (ccl_msg) Quartus 0xcfab: __scrt_common_main_seh + 0x10b (quartus_fit) Quartus 0x1259c: BaseThreadInitThunk + 0x1c (KERNEL32) Quartus 0x5af37: RtlUserThreadStart + 0x27 (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 11 OS version: 10.0.22631 Quartus Prime Information Address bits: 64 Version: 25.1.0 Build: 129 Edition: Pro Edition ----------------------------- this happens with every design and with Arria10, Stratix 10 and also Agilex 7. The only way to avoid these Quartus crashes is to run the fitter in Windows "Efficiency Mode", but that makes fitting time more or less double. Any hints?
Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.
Hello sir , i am also facing same kind of problem. when i am debugging my code , it working fine and i can access the EPCQ64A but when i run the code in standalone mode it, code works but cannot access the memory or write inside epcq64a. I have quartus prime standard edition 23.1 with license of both NiosII and NiosV. I am using 10CL055YU484I7G and niosv/g as my processor .This whole projects works fine with NiosII processor. but now i want to migrate to NiosV. Kindly help me out.
