Device migration about DD and DA
Hi Sir, 10M50DDF256C8G vs 10M50DAF256C8G My understanding is that the DD and DA packages are the same, or at least pin-to-pin compatible. However, when I tried using Quartus, I found that Device Migration cannot be set between these two devices. What is the reason for this? Are these two devices actually not pin-to-pin compatible? Thanks. Best Regards, AaronMAX10 Single end I/O low/high speed bank frequency
In single-ended I/O use cases, the actual performance differences between low-speed and high-speed I/O pins are still unclear, particularly with respect to the maximum safe operating frequency. Are there any official documents or guidelines that describe this difference? In our case, the protocol is SPI with a required maximum operating frequency of 100 MHz. We would therefore like to ask: if the SPI signals are routed to low-speed I/O pins, what is the maximum frequency at which stable operation can realistically be achieved? Are there any recommended limits, characterization data, or application notes that address this scenario?
USB Blaster not available
Hi, The USB blaster programs my Max 10 device fine until I plug in another usb cable that controls a Rabbit micro-controller (FTI device) I am interfacing to the MAX10 device. When this happens I get the message "No Hardware" under hardware setup. I amusing Quartus 24.1 std. I have tried the following: Changed the com port on the rabbit serial connection. Plugged the two cables into two separate powered USB hubs Reinstalled the USB blaster driver. Re-booted several times Tried a different USBB blaster device Has anyone got any ideas? I need to run signal tap at the same time as the rabbit development program so need both working at the same time. ThanksLTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
Agilex 9 Port Synchonization within A Tile
I am currently using Agilex 9 Evaluation Board AGRW014. I am trying to perform synchronization across 4 ports. I connected the sysref request from DRF IP to the respective pin connected to sync of LMK. Once powered ON, i issued the Start Latency Alignment command by writing the basic mode register 0x0400 bit[0] as 0x1. But i am facing the issue of SYSREF Response Error. Please share the proper sequence to be performed to achieve the Synchronization across port. As well as please provide the method or sequence of register writes to achieve proper phase synchronization (DDC NCO sync) over the bandwidth. Please list the things to be taken care while performing synchronization
NOR Flash IC programming using 3rd party Programmer
We have observed that programming the NOR Flash using the Altera USB‑Blaster via JTAG behaves differently compared to programming the same Flash device using a third‑party gang programmer. We have created an RPD file as mentioned in the below intel document, tutorial-write-raw-programming-data-rpd-into-flash-devices.pdf Observations During NOR Flash Programming 1.When the fresh NOR Flash IC is programmed using a third‑party programming tool and subsequently mounted on the Base Card, the card fails to boot. 2.However, the RPD image functions correctly when the following programming sequence is followed: -> Program the fresh NOR Flash of the CFPG A using the Altera USB Blaster via JTAG. -> Erase the NOR Flash. -> Reprogram the same RPD image, generated as per the procedure defined in the referenced document. When the above sequence is followed, the card boots and operates as expected. We would appreciate your input on whether any additional steps are required when using third‑party programmers to ensure compatibility with the FPGA boot mechanism.
