Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
Licence in Altera 2 Complete Design Suite version 13.0 SP1 For cyclone 1
"I am using Quartus II 13.0 Subscription Edition to compile code for a Cyclone I device (EP1C3T100C8). While the build compiles successfully, the software does not generate the .sof file needed to create a .jic file. Since this device family might have limited support, does anyone know how to enable or generate the .sof file in this version?"
Cold Temperature Issue
Hallo, We used the Agilex5 device in AS configuration connect to external QSPI Flash. We apply Smart VID interface at the device demands. When we perform Cold power up at -40C the device is not configured, It seemed the device is not output from the POR, No traffic on the PMBus. Power sequence and voltage ramp time and levels are OK. Please advise Thanks Asaf
ALTPLL - BANDWIDTH OPTION ?
Here is a professional and technically accurate English translation: Hi, I would like to ask about the meaning of the following setting in ALTPLL: Bandwidth - Preset Options: Auto, Preset (Low, L, H), Custom What is the purpose of this setting? I am using the FPGA device 10M02SCM153C8G and implementing an SCFIFO. Due to the signal logic requirements, I need to generate a stable 180-degree phase-shifted version of the signal and feed it into the SCFIFO, as well as to the FX2 IFCLK connected after the SCFIFO. Currently, I am encountering a very rare issue: image tearing (or frame splitting). My system architecture is: sensor → FPGA (FIFO) → FX2 → PC. Although this issue occurs very infrequently, I would still like to explore possible improvements. Previously, the FPGA setting was configured as Auto, and under this condition, the image tearing issue occurred more frequently. After changing the setting to Low, the system became significantly more stable. I am now considering whether to try the Medium setting, but before making further changes, I would like to understand what this bandwidth setting actually controls. Would you like me to refine this into a more formal email style (for vendor support like Intel/Altera), or keep it as a technical discussion tone?
Stratix III FPGA Development Kit
"Hello! I am currently facing an unusual issue when trying to use the Stratix III FPGA Development Kit. After installing Quartus II 13.1 Subscription Edition (the last version supporting the Stratix III family) along with the respective device files (.qdz) for Cyclone, Arria, and Stratix III, and properly configuring the license on Windows 11, the Stratix III family does not appear in the device selection wizard. Interestingly, the Quartus Device Installer states that the family is already installed, but it remains hidden inside the software. To isolate the issue, I have tested multiple operating systems and Quartus versions, but the problem persists: 1) Windows 11 & Windows 7 (Quartus II 13.1, 13.0, and 12.1 Subscription): Arria and Cyclone families work perfectly. Stratix III shows as installed in the device manager but is unavailable inside Quartus. 2) Windows 7 (Quartus II 9.0 Web Edition): The Stratix III family appears in the family selection menu in Quartus, but our specific device (EP3SL150F1152) is listed as unsupported. 3) Ubuntu 12.04 (Quartus II 13.1 Subscription): Same behavior as Windows; the installer claims it is there, but Quartus does not show it. Given these cross-platform results, I suspect the root cause might be: 1) A corrupted or flawed Stratix III device installer file (.qdz). 2) A licensing restriction, where our current license might need a specific feature enabled for the Stratix III family, even though the software allows the installation. Could you please guide me on how to get this Stratix III Development Kit operational (which features the EP3SL150F1152 device)?" Thank you for your time and assistance. I look forward to your guidance. Best regards!
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh ChavanModelSim-Intel FPGA Starter Edition 18.1 exits with code 211 when pressing Restart button
Hello, I am using ModelSim-Intel FPGA Starter Edition included with Quartus Prime Lite Edition 18.1. When I press the Restart button in the ModelSim GUI after running RTL simulation, ModelSim exits with the following message: "ModelSim is exiting with code 211. Check the transcript file for more information on the fatal error." Environment: - Quartus Prime Lite Edition 18.1 - ModelSim-Intel FPGA Starter Edition 18.1 - Windows PC - ModelSim path: C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem 確認したこと: - Quartus / ModelSim は再インストールされました。 - 環境変数とPATH設定を確認しました。 - 同じプロジェクトが別のPCで正しく再起動できる場合。 - このPCではGUIの再起動ボタンを押すと問題が発生します。 - PCにはTrend Micro Apex Oneがインストールされています。 - リアルタイムスキャンからIntel FPGA / ModelSimフォルダを除外した後、ModelSimは正しく動作しました。 質問: GUIの再起動ボタンを使う場合、ModelSim-Intel FPGA Starter Edition 18.1で既知の問題として、終了コード211はありますか? また、この問題はウイルス対策ソフトやエンドポイントセキュリティソフトに関係している可能性はありますか? この問題に対するおすすめの設定や回避策はありますか? ありがとうございます。
Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.
Regarding Cyclone 10 LP AS Configuration Timing Parameters
We are currently planning to verify the configuration between Cyclone 10 LP and an external Flash ROM. In order to confirm whether the Flash side specifications (setup / hold, tSLCH, etc.) are satisfied, we need to check the following timing parameters. However, these values are not described in the Cyclone 10 LP Datasheet. Could you please share any available information on the following? Minimum values (ns) of DCLK High time and DCLK Low time Minimum and maximum delay time (ns) from the DCLK edge to when the data output (e.g., ASDO) changes Time (ns) from nCSO going Low to the first DCLK edge Time (ns) from the last DCLK edge to nCSO going High Any information or reference document you can provide would be greatly appreciated. Best regards,Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi, I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be: ARM/HPS writes input data -> HPS2FPGA bridge -> FPGA-side DDR4 via EMIF_IO96B_DDR4COMP FPGA IP reads input data from FPGA-side DDR4 FPGA. IP computes and writes result back to FPGA-side DDR4 ARM/HPS reads result back from FPGA-side DDR4 via HPS2FPGA My current Platform Designer connection is roughly: HPS hps2fpga master -> EMIF_IO96B_DDR4COMP AXI memory-mapped slave FPGA accelerator memory port -> same EMIF_IO96B_DDR4COMP EMIF pins -> external DDR4 The EMIF configuration and DDR4 pin assignments are matched carefully against the example design: /agilex5e_installer_package/examples/bts_emif/bts_ddr4_2b downloaded from the agilex5e installer package. I also tested the original bts_ddr4_2b style flow in the example using: JTAG -> pattern adaptor -> EMIF -> DDR4 and DDR4 read/write tests pass without errors. So the FPGA-side EMIF DDR4 calibration/pattern test appears to work. However, when I try to access the same FPGA-side DDR4 from Linux on HPS through the HPS2FPGA bridge using devmem2, the access fails badly. For example, accessing the HPS2FPGA mapped address causes a bus error / fatal SError. One example log: root@agilex5dka5e065bb32aes1:~# devmem2 0x40000000 w /dev/mem opened. [ 1017.877669] SError Interrupt on CPU2, code 0x00000000be000011 -- SError [ 1017.877707] CPU: 2 PID: 791 Comm: devmem2 Not tainted 6.12.19-altera-g7b497655d942 #1 [ 1017.877717] Hardware name: SoCFPGA Agilex5 SoCDK (DT) ... [ 1017.877814] Kernel panic - not syncing: Asynchronous SError Interrupt ... Bus error For comparison, I connected the same HPS2FPGA bridge to an on-chip memory in the FPGA fabric. Accessing that on-chip memory from HPS with devmem2 works correctly. So the HPS2FPGA bridge itself seems functional. Current observations: HPS2FPGA -> on-chip memory works. JTAG -> pattern adaptor -> EMIF -> DDR4 works. EMIF calibration appears to pass. HPS2FPGA -> EMIF DDR4 causes SError / bus error / Linux kernel panic. Here is my current Platform Designer connection. In the screenshot, you can see that I copied over the EMIF-driving logic from the installer package. For emif_axi4, one connection goes to my IP’s memory port, and the other goes to the HPS hps2fpga interface, although that HPS connection is not shown in this screenshot. Does anyone have any clues about what might be wrong here? Is this expected to work, or is this use case currently not supported, i.e. HPS reading/writing data directly to FPGA-side DDR through HPS2FPGA while an FPGA IP also accesses the same DDR through the EMIF AXI4 interface? If any additional files would be helpful, I can provide them. Thank you in advance!
