Arria 10: Remote Update may brick FPGA and Factory Fallback won't work
Hello, we have observed some critical failures when doing tests with various potential error scenarios concerning a remote Update of the FPGA bitstream in the attached SPI Flash device. We could repeatedly trigger cases, when the FPGA internal fallbeck mechanism to the factory load does not work. We do not use any bitstream encryption. Test scenarios: Erased flash & partially programmed application load image --> Fallback mechanism works as expected Invalid application load image location, i.e. start of application load is shifted by1-10 Byte (Manually induced error scenario) --> The reprogramming sequence starts but never completes and no fallback to the factory load is performed. => The FPGA is completely unresponsive unless programmed via JTAG It is obvious, that the 2nd scenario might be a more exotic error scenario, however we require a robust setup and have to make sure, that the FPGA remains accessible under any circumstances, so we need the Factory Fallback mechanism to work reliable! As a best guess I could assume it might be related to this Note in 1.3.1. Remote System Configuration Mode that the factory fallback mechanism won't work for Arria 10 FPGAs if the last 576 Bytes of the bitstream are corrupted. Note: The fallback to the factory image does not work under the following conditions: If the last 576 bytes of an unencrypted application image bitstream are corrupted. Intel recommends that you examine the last 576 bytes of the unencrypted application image before triggering the application image configuration. But I have noticed that the binary images of the FPGA bitstream vary in size. So there is no way to check explicit memory locations for these 576 Bytes. Is there any way to identify this section? My Questions: Why is the factory configuration fallback mechanism not working in the above described scenario? The Factory load image is valid! What method does intel recommend to reliable make the factory fallback mechanism work? How can I examine/validate a FPGA bitstream in flash memory before executing it? Thanks a lot for any help Best regards Fabian
Unable to program EPCQ16A on custom cyclone IV board - error during jic flashing.
Hello, I have created a custom FPGA PCB board with cyclone IV EP4CE6E22C8N FPGA. For flash I have a EPCQ16A. When I try to configure my FPGA in jtag mode MSEL (2:0) = "011", and use the .sof file. - everything is working properly. But when I try to flash using .jic - it fails to program and shows an error. While generating the jic file I did select the correct flash device - EPCQ16A. And I changed my MSEL(2:0) to "010" (AS mode). When I give autodetect before adding the .jic file, it does recognise my FPGA device and after I have added the .jic file I can see the EPCQ16A in the JTAG chain. However, when I program it fails. I have attached the programmer window screenshot and the error message: Info (209060): Started Programmer operation at Thu Nov 27 12:04:37 2025 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x020F10DD Info (209007): Configuration succeeded -- 1 device(s) configured Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly. Error (209012): Operation failed Info (209061): Ended Programmer operation at Thu Nov 27 12:04:39 2025 Please can anyone tell me where I am going wrong and how to fix it?
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
Multirate IP FHT Support
Hello I am trying to create a reconfigurable FPGA device using FHT transceivers to generate the highest possible speed PAM4 outputs. I'd like to create a device that can switch between many speeds at the same time, however, the F-Tile PMA and FEC Direct PHY Multirate IP currently does not support FHTs being reconfigured in any way (neither does the dynamic reconfiguration IP). Is there any news about when this feature is to be added? ThanksTiming Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Cyclone V Clamping Diode Electrical Specification
Hi, Please provide the below information for the Cyclone V Device IO Banks signals. what is the clamping voltage for the internal diode when enabled. what is the normal protection voltage for IO pin when clamping diode is not enabled. What is the diode used for an Clamping diode, is it an Zenor Diode or TVS Diode or Schottky Diode
Allow encrypted POF only
Hi! Can someone explain what this is security feature (Allow encrypted POF only) is supposed to do? In the description it says, "When enabled, devices accepts encrypted POF". However, this is not the case. After creating a .pof with "Allow encrypted POF only" and encryption, then loading this .pof + ekp file, everything after this first program/configure fails. This means you cannot program/configure/verify/blankcheck/examine with the same or different .pof/.ekp. The only solution is erase. But this feature should have allowed for encrypted pof to be programmed. Originally, I thought it would allow you to load a new .pof as long as you use the same key (.ekp). After experimenting with various cases, I cannot get pass the failure of reconfiguring the device. (CONFIG_DONE pin failed to go high in device 1. .... Operation Failed). The only solution is to erase. Which brings me back to the question of what is "Allow encrypted POF only" supposed to do? Can you provide procedures to get this feature to actual work? I am on Quartus Prime Standard Edition version 23.1 using a Max10 (m50) FPGA. Thank you!
Max10M-16-SA-U-169 program without having the project file
Hi, I am trying to program the already designed and programmed Intel Max 10M-16-SA-U-169 to change the states of some of the components connecting to the FPGA. I do not have the project file and the pin assignment of the FPGA. I only have some .pof files that I can program the FPGA through the JTAG connection with a USB blaster. Is there any way to access the design of the FPGA through Quartus, or is there any way to do it with any other tools or software? Can I find out the pin assignment of the FPGA? I would appreciate it if anybody could help me with this situation.
