How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?
Timing analyser reports CLKUSR at 125MHz but target system has 100MHz on this pin to accommodate AS in combination with transceiver calibration as per the manuals -- there doesn't seem to be any consequences as the project seems to run fine but is a bit unsettling
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
LTC Connector DE10-Standard FPGA
I am trying to access the I2C bus on the LTC connector on the DE10 Standard FPGA board. I have enabled the i2c controllers on the HPS. How do I now gain access to the i2c2 pins that are connected to the ltc connector from the HPS? I was able to communicate to the g-sensor that shares the same bus with the ltc connector, but I need to access the LTC connector to communicate with a separate board. I see that there is a TS3A5018 switch. Am I required to set the HPS_LTC_GPIO to low to switch communication from spi to i2c? Kindly help.
Agilex5 / IBIS HSIO - LPDDR4
Hi, number of IBIS models for banks HSIO listed in ag-5-device-list-of-ibis-models.xlsx, is very important (several thousands). We are interfacing LPDDR4 on our HSIO banks at standard LVSTL11 single and diff. When generating an EMIF IP for that need, without touching defaults parameters (hereafter) , which are IBIS models to use among that list ? We are supposing « lvstl11_io_s3r40c_doff » and « dlvstl11_io_s3r40c_doff ».
Error : Arria 10 emif_reset_ interrupt acknowledge
Hi All, I am currently working with an Arria 10 FPGA on a custom board and have encountered an issue where the PCB restarts after the following error message appears: "Error: Arria 10 EMIF reset interrupt acknowledge" I have verified all supply voltages and clock signals, and they are within the expected ranges. Initially suspecting a DDR-related issue, I replaced the DDR component; however, the problem persists. Additionally, all status pins appear to be functioning as expected. I would appreciate any guidance or suggestions on how to further debug this issue. Thank you in advance for your support.
Cannot access SSLC portal for Questa License
Hi everyone, I am a final-year ECE student and a newcomer to this community. Please excuse me if this is not the right place for this query, but I am looking for some help with the licensing process. I am currently setting up a professional VLSI verification environment on my Linux workstation. I have installed the Questa*-FPGAs Standard Edition to support my learning in UVM (Universal Verification Methodology) and advanced SystemVerilog Assertions for my final-year project. I am trying to obtain the free Starter Edition license through the Altera/Intel FPGA Self-Service Licensing Center (SSLC). However, when I attempt to log in to the portal, I receive the following error: "You do not currently have access to this site. Please follow the instructions on the help page to request access." I have a registered account, but being new to the Altera ecosystem, I am a bit confused on how to "request access" or verify my account to use the licensing portal. Could someone please guide me on: How to properly activate my account for the SSLC portal? The correct steps for a student to get a zero-cost license for Questa? I am really excited to start working with Questa and any guidance would be incredibly helpful! Thank you for your patience and support, Mayank Anand
Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank youTiming Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
