Arria 10 GX Remote Update Circuitry
Hello, We are using an 10AX066 FPGA connected to an MT25QU01 flash. It's connected through Active Serial. We are looking to use a system setup that will allow us to boot into a user image, before falling back to a factory image if it fails to configure 3 times, we do not need a watchdog, or the AnF bits. Is the default behaviour of the Arria 10 device to provide the features provided in this flow chat (https://www.intel.com/content/www/us/en/docs/programmable/683461/current/configuration-sequence-in-the-remote.html)? Is the Remote Update IP core necessary for any functions that we want?
M9K utilization is different for the same RAM IP for two different projects.
I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects. The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks. For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below: The settings for the RAM-IP are as shown in the image below: Quartus Tool Version : Quartus 18.1 Standard FPGA Device : MAX-10 10M50DAF256I7G Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks. Thank you, Akhilesh.
Device migration about DD and DA
Hi Sir, 10M50DDF256C8G vs 10M50DAF256C8G My understanding is that the DD and DA packages are the same, or at least pin-to-pin compatible. However, when I tried using Quartus, I found that Device Migration cannot be set between these two devices. What is the reason for this? Are these two devices actually not pin-to-pin compatible? Thanks. Best Regards, Aaron
Agilex 9 Port Synchonization within A Tile
I am currently using Agilex 9 Evaluation Board AGRW014. I am trying to perform synchronization across 4 ports. I connected the sysref request from DRF IP to the respective pin connected to sync of LMK. Once powered ON, i issued the Start Latency Alignment command by writing the basic mode register 0x0400 bit[0] as 0x1. But i am facing the issue of SYSREF Response Error. Please share the proper sequence to be performed to achieve the Synchronization across port. As well as please provide the method or sequence of register writes to achieve proper phase synchronization (DDC NCO sync) over the bandwidth. Please list the things to be taken care while performing synchronizationConfiguration via Protocol (CvP) fail after loading the periphery image
Hi, May I know if this issue has been resolved in newer versions of the CvP driver? I am still facing CvP intermittent failing problems and was wondering whether there are other workarounds other than the need for a power recycle. "Due to a CvP upstream driver issue, CvP may intermittently fail after successfully loading the periphery image into all Intel Agilex® devices with package code R31C / R31B.". Here is the link where I found the article: https://www.intel.com/content/www/us/en/support/programmable/articles/000089044.html Thanks, Jon
