Forum Discussion
New ContributorConfiguration via Protocol (CvP) fail after loading the periphery image
Hi,
May I know if this issue has been resolved in newer versions of the CvP driver? I am still facing CvP intermittent failing problems and was wondering whether there are other workarounds other than the need for a power recycle.
"Due to a CvP upstream driver issue, CvP may intermittently fail after successfully loading the periphery image into all Intel Agilex® devices with package code R31C / R31B.".
Here is the link where I found the article:
https://www.intel.com/content/www/us/en/support/programmable/articles/000089044.html
Thanks,
Jon
24 Replies
freddy3366Hey, I’m not sure if it’s fixed in the newer CvP driver versions, but the intermittent failures seem to still be a thing for some. If power recycling isn’t ideal, maybe reach out to Intel support—they might have alternative workarounds. Good luck!
thedentaku67The issue has been fixed in Quartus 22.2.
- JohnT_Altera
Regular Contributor
HI,
Thanks for confirming that updating the timeout value resolved the issue in our call discussion
- JohnT_Altera
Hi,
Are you able to try with the increasing the timeout value?
- JohnT_Altera
Hi,
While I am working with the engineering team on this, can you help try to increase the timeout value to see if it can resolve the issue?
drivers/fpga/altera-cvp.c file.
Change "#define V2_CREDIT_TIMEOUT_US 40000" to "#define V2_CREDIT_TIMEOUT_US 60000"
Thanks.
- JohnT_Altera
Hi,
If you are still facing intermittent failure can you provide the log file from this command "dmesg | tail -4"? This will provide more detail on what is happening when you are performing CvP programming
JonGohHi @JohnT_Intel ,
Yes I am still facing intermittent failures. Here are the log files.
[12201.065931] altera-cvp 0000:01:00.0: Timeout waiting for credit
[12201.065934] altera-cvp 0000:01:00.0: Wait Credit ERR: 0xffffff92
[12201.065936] fpga_manager fpga0: Error while writing image data to FPGA
[12201.066005] fpga_manager fpga0: fpga_mgr_load returned with value -110Thanks,
Jon
- JohnT_Altera
Hi,
Please try out 5.10.110-lts version as that is verified kernel that is working.
Thanks.
John Tio
- JohnT_Altera
Hi,
Can you try modify the source code of 5.15.3-lts as below?
drivers/fpga/altera-cvp.c file.
Change "#define V2_CREDIT_TIMEOUT_US 20000" to "#define V2_CREDIT_TIMEOUT_US 40000"
Thanks.
- JonGoh
Hi @JohnT_Intel ,
The original source code for 5.15.30-lts is already set as 40000. For kernel version 6.6.37-lts, may I know if the problem of /sys/kernel/debug/fpga_manager directory not being created is replicable?
Thanks
Jon
- JohnT_Altera
Hi,
Can you try Kernel 5.1*.50 and above? I have check internally and it is updated in 5.1*.50 and later kernel version. Maybe you may try 5.15.100-lts.
- JonGoh
Hi @JohnT_Intel ,
Yes the design of PCIe Gen3x8 is loaded into the FPGA. I am using Ubuntu 22.04, and used kernel version of 5.15.30-lts at first, and also tried 6.6.37-lts and encountered the problem mentioned above. I also attempted to compile 5.15.100-lts, but there seems to be an error in compiling, here is the error.
fs/ksmbd/smb2pdu.c: In function ‘smb2_write’:
fs/ksmbd/smb2pdu.c:6478:13: error: ‘is_rdma_channel’ undeclared (first use in this function)
6478 | if (is_rdma_channel == false) {
| ^~~~~~~~~~~~~~~
fs/ksmbd/smb2pdu.c:6478:13: note: each undeclared identifier is reported only once for each function it appears in
make[2]: *** [scripts/Makefile.build:289: fs/ksmbd/smb2pdu.o] Error 1
make[1]: *** [scripts/Makefile.build:552: fs/ksmbd] Error 2
make: *** [Makefile:1910: fs] Error 2Meanwhile, I'll try other versions from what you mentioned above,
Thanks,
Jon
- JohnT_Altera
HI,
Please also provide the OS and initial kernel version used.
