JohnT_Altera
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Re: ASx4 Interface debug in MSEL=111 (JTAG mode)
Hi, You will be able to access the QSPI Flash when you are using MSEL set to JTAG mode. https://docs.altera.com/r/docs/847422/25.3.1/device-configuration-user-guide-agilextm-3-fpgas-and-socs/debugging-guidelines-for-the-as-configuration-scheme May I know which board are you using and if you are using custom board, can you share with me your board schematic so that I can understand what is actually causing the issue? If you are able to provide some screenshot of the SFDP then it will be also provide some basic information.18Views0likes0CommentsRe: AI Suite System Throughput Issue
Hi, 1. Are the handbook AGX7 IP+Host numbers measured using S2M streaming architecture or M2M ? The Agilex 7 performance is based on the PCIe + FPGA AI Suite IP benchmarking. This benchmarking will be different compare to the HPS method as the CPU use it higher performance compare to the HPS processor. With S2M implementation, it is relying on the Nios V to offload the HPS task. 2. Is there a recommended method to measure true end-to-end throughput on AGX5 ? Do you need the full system performance throughput? If yes, what type of implementation are you looking at as the current implementation might not be suitable to showcase the throughput of the full system. 3.Are there any known bottlenecks in the Agilex 5 SoC Example Design S2M Bitstream and SD Card Image. The current S2M implementation is to emulate the data by copying the data to buffer before it is being stream into the FPGA AI Suite IP. In order to have the real throughput for the S2M implementation, the streaming data will need to directly pass it to the FPGA AI Suite. You may refer to https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-5/e-series/modular/camera/camera_4k_ai/camera_4k_ai/ which implemented a direct data input to the FPGA without the use of the ARM processor to send the data to the streaming buffer. Thanks8Views1like0CommentsRe: AI Suite System Throughput Issue
Hi, The dla_benchmark is to run the testing to get the throughput of the IP. It is not suitable to be used to get the full system throughput as it will include the data transfer from Arm to the DMA buffer before sending it to the AI Suite IP. You will need to run the application below which is for the full system application example streaming_inference_app This application loads and runs a network and captures the results. image_streaming_app This application loads bitmap files from a folder on the SD card and continuously sends the images to the EMIF, simulating a running video source Thanks.27Views0likes0CommentsRe: Cyclone IV E Device VCCIO bank Power Supply related
Hi, Is this approach correct? Can 3.3 V LVTTL/LVCMOS signals be safely interfaced to an FPGA I/O bank powered at 3.0 V without violating input tolerance or causing long‑term reliability issues? Yes, you are correct. What about FPGA outputs? If the FPGA bank is powered at 3.0 V VCCIO, and the FPGA drives LVTTL/LVCMOS outputs to external circuitry that expects 3.3 V levels, will this work reliably? Are the VOL/VOH levels still compliant? You will need to check the ViL and ViH of the device to see if it is meeting the specs. Are there any risks of reduced noise margin? Please follow the guideline mention on the termination resistors. In summary: Is powering the bank at 3.0 V a valid method to avoid adding series termination? If you are using 3.3V IO standard then it is recommended to use 3.3V VCCIO. https://docs.altera.com/v/u/docs/654327/cyclone-iv-device-handbook-volume-3-device-datasheet What are the recommended practices for LVTTL/LVCMOS signaling in Cyclone IV E when the external system uses 3.3 V levels? I would recommend to the same IO Standard as the external systems. Thanks.16Views0likes1Comment