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JohnT_Altera
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Re: AI Suite - How to interpret these graphs in Model Analyzer GUI
Thank you for sharing the compiler reports. Below is how to read them, and why DeviceSubgraph appears. What you can learn from these subgraphs The compiler message: The input graph is split into 9 subgraph(s), FPGA:3 CPU:6 means the model does not run as one FPGA graph. OpenVINO HETERO splits it into contiguous islands: 3 on FPGA and 6 on CPU. Each island is a subgraph. Data that crosses FPGA ↔ CPU is copied through host memory, so extra islands usually mean extra latency. From your YOLO3 TensorFlow graph, the 9 partitions are: FPGA (3) — real DLA compute DeviceSubgraph_8061 (subgraph=15): backbone + conv2d_58 head DeviceSubgraph_8068 (subgraph=20): medium-scale path + conv2d_66 head DeviceSubgraph_8073 (subgraph=26): fine-scale path + conv2d_74 head CPU (6) — layout / upsample / outputs Input NHWC→NCHW (Transpose_169) and the stem that stays with it Two FPN upsample islands (up_sampling2d and up_sampling2d_1) Three output NCHW→NHWC transposes (conv2d_58/66/74 BiasAdd → Result) Why is there a node named DeviceSubgraph? DeviceSubgraph_8061 / _8068 / _8073 are not layers from your Keras/TF model. The HETERO plugin groups a run of consecutive FPGA layers into one hetero::DeviceSubgraph node so the top-level (_3) graph can show: CPU ops in full Each FPGA island as one “execute this blob on FPGA AI Suite IP” node That is why you see exactly three DeviceSubgraph boxes — they are the FPGA:3 count. To see the convolutions inside one box, open the matching file, for example: hetero_subgraphs_TensorFlow_Frontend_IR_3_node_DeviceSubgraph_8061_subgraph_#0.dot0Views0likes0CommentsRe: AI Suite - Why does the Sequential IP not take a model argument?
Hi, The Sequential IP can support multiple model as it is depend on how you implement the features into the IP. So the flow is to run "dla_compiler --network-file model.xml --march my_arch.arch" where it report what is the unsupported layer in the current Sequential IP. Thanks.80Views1like3CommentsRe: AI Suite - Various Questions
1. Estimating whether a model will fit on an FPGA using a formula What could be an approximating formula (It does not need to be accurate). And what are the typical limiting factors? You can run the dla_compiler to get the resources utilization base on https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/estimating-the-area-and-power-of-an-architecture 2. Impact of the enable_parameter_rom parameter Is it correctly understood that this parameter determines whatever the mif (Memory initialization files) containing the weights are put inside a rom or external memory? This function is depreciated. Use enable_on_chip_parameters and disable_external_memory instead. This will disable the use of external memory Does this actually impact the speed? I would assume that the external memory might be faster than some of the bottleneck components in the AI IP block. Yes, but will increase the M20K utilziation 3. Any architecture options for the Spatial IP? My model uses a 16bf * 6 input, so I think it would make sense to increase the input stream size so it matches. But I don't know if the same options from the sequential IP also applies to the spatial IP, since the example is just two lines. Please refer to $COREDLA_ROOT/example_architectures/AGX5_Simple_Spatial.arch $COREDLA_ROOT/example_architectures/AGX7_Robust_Spatial_Compilation.arch $COREDLA_ROOT/example_architectures/AGX7_Simple_Spatial.arch21Views1like0Comments