JohnT_Altera
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Re: yolov3_tiny_tf run_inference_stream problem
Hi, Have you performed some emulation to confirm if the model you are using is able to be run in FPGA? The reason is that the example provided is to have the model fully run in FPGA. But based on the log file provided, some of the layer is not able to performed in FPGA and it need to revert to CPU but the Application code does not support it. It is recommended you try to compile graph and check the output if it is fully supported or not. https://www.intel.com/content/www/us/en/docs/programmable/863373/2025-3/compiling-a-graph.html.7Views0likes2CommentsRe: Looking for Power Supply Supervisor Solution for Agilex-5 SoC (A5EDxxx) with Tight Voltage Tolerance
Hi, We do not have the information on the power supply supervision but if you refer to the schematic, it will provide the information on the regular power supply used with the FPGA device.38Views0likes0CommentsRe: Agilex7 m-series for llama
Hi, 1.Agilex7 m-series does not provide a BSP. If I want to deploy llama on Agilex7, can I only generate the BSP through OFS customization? Yes, you are correct. You will need to customize it. 2.In the RTL support provided by OFS, I did not find HBM. Is it necessary to generate it myself through Quartus Prime Pro? You can generate OFS for M-series dev kit from " ./ofs-common/scripts/common/syn/build_top.sh --ofss tools/ofss_config/mseries-dk.ofss mseries-dk:flat work_mseries-dk". Please refer to https://github.com/OFS/ofs-agx7-pcie-attach for all the supported BSP 3.In the 3.example_architecture folder, no information about hbm is provided. I would like to know how to modify the arch file in order to use hbm? The arch file does not need to make the changes as the you it is handle from the BSP. The performance will change when it is running through HBM compare to DDR. Thanks.50Views0likes1Comment