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Agilex 7 M series Open FPGA Stack support
Hello, We are using Agilex 7 M series FPGA and considering to evaluate Open FPGA Stack (OFS) at some point. Currently the latest OFS release (2025.1) contains only pre-release level support for Agilex 7 M reference shell design and lacks support for many key features (https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2025.1-1). Could we expect to get an official release level support some time in the near future? Best regards Otto5Views0likes0Comments
Deprecation Notice for FPGA Support Package for oneAPI DPC++/C++. What is the alternative?
Hi there, We recently began to port our HLS-C++ projects to oneAPI as the HLS-Compiler was no longer continued. Today I noticed the deprecation notice for "FPGA Support Package for Intel® oneAPI DPC++/C++ Compiler". See https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga.html . Hm. Looking at the Intel/Altera software page, it lists 4 HLS tools, of which two are the mentioned deprecated ones and the others are not suitable for continuation for our projects (no c++). So the questions are: * Is there a SYCL-for-FPGA-support in the future? * Is there a "HLS"ish C++-support planned in the future? (or other non-matlab languages) * What is the recommended High level approach for FPGA projects with an image processing background?Solved2.5KViews0likes5CommentsAgilex 7 I-Series "aocl diagnose acl0" error following OFS
Hello, I've been working through the Open FPGA Stack (OFS) guides to set up my Agilex 7 I-Series development kit for use with oneAPI. I've worked through prior SystemVerilog issues encountered by switching the generated FPGA Interface Manager (FIM) from a 1x16 PCIe configuration to a 2x8 configuration (although 1x16 would be more preferred). I am now on the final step of wrapping the FIM into a BSP and validating it for use with oneAPI by running the "aocl diagnose acl0" command. I should note that performing just "aocl diagnose" works fine. When I add "acl0" and execute, however, I find that all attempts to communicate between the host and FPGA via DMA fail (although we do see a single VTP L2 4KB hit). The exact output from the diagnose command is in the text file attached. I have tried using both a minimal FIM generated via command provided in the OFS guides, as well as pre-builts from the Github page. Why might this error be occurring, and how can I fix it? Any help is greatly appreciated, thank you! James308Views0likes9CommentsOneAPI Support for Agilex 5 and 7 Development Kits
Hello, I've recently acquired an Agilex 5 065B Modular development kit (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html) and an Agilex 7 I-Series development kit (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html). I've been working through setting up the development environments for these boards, and would like to use the oneAPI HLS toolkit for them, if possible. So far, I've found a tutorial to create an accelerator support package for the Agilex 7 development kit that I have (https://ofs.github.io/ofs-2024.3-1/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/). I'm planning to go through these steps shortly to setup my board for use with oneAPI, but I have yet to find any documentation for my Agilex 5 board. Is it possible to work with this Agilex 5 development kit using oneAPI, or is only the Quartus design flow supported at this time? Additionally, are there board support packages available (that I've just missed) - or soon to be available - for these cards if the HLS flow is an option? Thank you!1.6KViews0likes5Comments
Agilex 5 Precision DSP block simulations
Hi, I'm using the Precision DSP blocks in my Agilex 5 design; i have a floating point Add (FP_Add_native_DSP) and a floating point MAC (FP_MAC_native_DSP), but when i try and run simulations with these in place i'm seeing odd behavior: 1/ The adder is not doing an addition, the output is merely following one of the input pins. 2/ The MAC is giving an output but this does not match the output i'm seeing from a similar MAC targeted for the Arria 10 FPGA. The Arria 10 design is proven on silicon so i would have thought the simulation model for this is correct. The above is making me nervous and i'm seeking clarification that: 1/ There are indeed bugs in the simulations models - if so is there a patch available? 2/ The Floating Point DSP functions work correctly on the actual Agilex 5 silicon. I look forward to hearing from you. SimonSolved4.9KViews0likes10Comments
Creating PCB based on 10M08 Evaluation Board but with other MAX10 FPGA
Hello everyone, for a school project, I want to design a PCB for / around the MAX 10 FPGA. As I'm trying to make my life easier, I am using this (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/max/10m08-evaluation-kit.html) Intel Evaluation Board as a starting point. the FPGA used in the design is the 10M08SAE144C8G. However, it has only 8000 LE, which will not be enough, therefore I'm planning to use 10M16SAE144C8G as a (hopefully) drop in replacement. I think that this will work, why shouldn't it? All it really is, is a PCB which uses the same layout, but with more of the available GPIOs broken out and preferable the mentioned 10M16SAE144C8G (or even 10M25SAE144C8G). I checked the pinout of both FPGAs and they are the same. Also programming should be the same as far as i know. Thanks for reading!1.3KViews0likes1Comment
HAL Kernel Version Mismatch Error During FPGA Emulation with vector-add Sample
Hello Intel FPGA team, I'm currently working on the vector-add example from the official oneAPI-samples repository, specifically from: DirectProgramming/DPC++/DenseLinearAlgebra/vector-add I’m encountering the following runtime error when I attempt to run the emulation build: Error output: ./vector-add-buffers.fpga_emu HAL Kern: Version mismatch! Expected 0xa0c00001 but read 0x4130 Hardware version ID differs from version expected by software. Either: a) Ensure your compiled design was generated by the same ACL build currently in use, OR b) The host can not communicate with the compiled kernel. vector-add-buffers.fpga_emu: /nfs/sc/disks/swip_hld_1/ops/SC/hld/nightly/2022.1/96.2/l64/work/acl/acl/source/57c9d2bcb46afcf445b5da2406c0e6d85be93ef3/src/acl_kernel_if.cpp:733: int acl_kernel_if_init(acl_kernel_if*, acl_bsp_io, acl_system_def_t*): Assertion `0' failed. make: *** [Makefile.fpga:35: run_emu] Error 1 Environment details: Board: DE10-Agilex BSP Path: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/board/de10_agilex oneAPI version: Installed multiple versions. Active: 2022.0.2 dpcpp path: /opt/intel/oneapi/compiler/2022.0.2/linux/bin/dpcpp OS: Ubuntu (detected as Rocky Linux during install attempts) What I have tried: Verified the AOCL_BOARD_PACKAGE_ROOT is correctly set. Recompiled the design using make clean && make fpga_emu. Ran aoc -list-board-packages to confirm the installed board. Ensured Quartus, BSP, and compiler are aligned. Despite that, I still encounter the HAL version mismatch. Request: Could someone guide me on how to: Resolve this version mismatch issue? Confirm the correct environment and runtime versions are in sync? Completely clean older/duplicate oneAPI installations if that’s the root cause? @intel @OneAPI @fpga @agilex7 @de10 @intel65.1KViews0likes3Comments
writing and reading max10 ufm
hii i have the neek dev kit , and i did a project to write and read the max10 ufm i see in the signal tap in my project that i can write the data and read successfully i programmed the board with the pof so that my firmware is inside the board , but when i turn off the board and turn it on again , and read the data from ufm i see that the data is all zeros meaning that the data didn't get saved in the ufm , and i know that the ufm is non volatile memory . i am using the on chip flash ip , i expect the data to be saved in the ufm . when i program the pof and perform the write and the do the read while the board under power everything is ok , data get written and read . but the problem start when i turn the power down do i need to do a special thing in order to commit the data to the ufm and save so i can read it after power up ???1.9KViews0likes4Comments