Recent Discussions
Agilex 7 I-Series "aocl diagnose acl0" error following OFS
Hello, I've been working through the Open FPGA Stack (OFS) guides to set up my Agilex 7 I-Series development kit for use with oneAPI. I've worked through prior SystemVerilog issues encountered by switching the generated FPGA Interface Manager (FIM) from a 1x16 PCIe configuration to a 2x8 configuration (although 1x16 would be more preferred). I am now on the final step of wrapping the FIM into a BSP and validating it for use with oneAPI by running the "aocl diagnose acl0" command. I should note that performing just "aocl diagnose" works fine. When I add "acl0" and execute, however, I find that all attempts to communicate between the host and FPGA via DMA fail (although we do see a single VTP L2 4KB hit). The exact output from the diagnose command is in the text file attached. I have tried using both a minimal FIM generated via command provided in the OFS guides, as well as pre-builts from the Github page. Why might this error be occurring, and how can I fix it? Any help is greatly appreciated, thank you! James
Any date for the release of the Docker image alterafpga/fpgaaisuite-quartus-v2026.1.1?
The FPGA AI Suite Handbook v2026.1.1 refers to docker images alterafpga/fpgaaisuite-quartus-v2026.1.1 and alterafpga/fpgaaisuite-v2026.1.1 but docker desktop stops at alterafpga/fpgaaisuite-v2025.3. Could anyone give a best guess as to when it will become available? Best wishes, Jeremy
Is Spatial IP ready for LLM / transformer inference?
I am using FPGA AI Suite 2026.1.1 (with the new spatial compiler). Most of the FPGA AI Suite handbook examples I see are classical CNN / vision flows (ResNet-style) on PCIe, hostless JTAG, and SoC. Is transformer / LLM inference (attention layers, variable sequence lengths, large KV-cache activations, etc.) something we can target today with dla_compiler + Spatial IP, or is Spatial still aimed primarily at CNN-like graphs, or is custom RTL expected? And if yes, are there any LLM examples, guides, recommended flows, or known limitations? Thanks,
Agilex 7 FPGA Starter Kit with oneAPI Toolkit flow not detected over PCIe
Hello, I’m trying to use a Terasic Agilex 7 FPGA Starter Kit (A7SK, rev.A) with the Intel oneAPI toolkit, following Terasic’s official A7SK oneAPI manual. The ASP image appears to load successfully, but after reboot the host does not detect the board as a PCIe device. The system behaves as if no PCIe card were present. The board is powered correctly, SW4 is set for x8, and the USB/JTAG side is visible, but the PCIe endpoint never enumerates. Has anyone here successfully made the Terasic A7SK work with oneAPI? Has anyone seen a similar issue where the board never appears over PCIe after reboot? Any experience, confirmation, or suggestions would be very helpful. Thanks.Can Intel's AI Reference Kit LLM pipelines run on OpenVINO runtime inside FPGA AI Suite 26.1.1?
I run OpenVINO + FPGA AI Suite 26.1.1 in two setups: PCIe: OpenVINO on x86 Linux host → FPGA card SoC: OpenVINO on Arm Linux (HPS) → FPGA AI Suite IP over AXI Intel's AI Reference Kits include ready-made LLM inference pipelines built on OpenVINO. https://www.intel.com/content/www/us/en/developer/topic-technology/edge-5g/open-potential.html I want to take one of these pipelines and run it using the OpenVINO runtime that ships inside FPGA AI Suite, so the FPGA handles the inference instead of the CPU. Is the bundled OpenVINO runtime + FPGA plugin / spatial compiler in 2026.1.1 compatible with these Reference Kit LLM pipelines? If it does not work directly out-of-the-box, what modifications would be needed? Thanks,
MCTP over PCIe VDM routing to PMCI in OFS N6000 FIM configuration and datapath clarification
Hi Team, I am working on implementing PLDM over MCTP over PCIe VDM on the Intel N6000 platform OFS PCIe Attach FIM. I have referred the following documents: 1. OFS Linux MCTP driver documentation: https://github.com/OFS/linux-dfl/blob/2014c95afecee3e76ca4a56956a936e23283f05b/Documentation/networking/mctp.rst 2. OFS Agilex PCIe Attach FIM architecture guide: https://ofs.github.io/ofs-2025.1-1/hw/n6001/dev_guides/fim_dev/ug_dev_fim_ofs_n6001/#1211-top-level From my understanding, the PMCI module inside the FIM contains the MCTP over VDM controller which transmits MCTP payloads containing PLDM commands to the MAX10 BMC. The BMC communicates with PMCI via SPI. The host can access PMCI CSRs through PCIe MMIO and this is working in our setup using the intel-m10-bmc driver. However, the datapath for MCTP over PCIe VDM from the host is unclear. I have the following questions: 1. How are PCIe VDM packets generated from the host routed to the PMCI MCTP controller inside the FIM? 2. Is there any specific configuration or enablement required in the PCIe subsystem or FIM fabric to allow VDM packets to reach PMCI? 3. What is the role of the MCTP Management Interface or MCTP VDM controller IP in the OFS FIM design? 4. Is this a custom IP responsible for filtering or routing VDM packets? How is this block exposed to the host? 5. Are there any registers, BAR mappings, or configuration steps required to enable this datapath? Does the Linux MCTP stack directly interact with PMCI, or is routing handled entirely in hardware? Currently, we are able to generate PCIe VDM packets from the host, but they are not observed at the PMCI or BMC side. This suggests that the ingress path may not be enabled or packets are being filtered before reaching PMCI. Any clarification on the expected datapath and required configuration for enabling host to PCIe VDM to PMCI to BMC communication would be very helpful. Thanks and regards, Nafiah Siddiqha
