Recent Discussions
Intel BD-NVV-N3000-2 issue
After installing new FPGA card on PCIe x16 Slot, when we try to enter in BIOS server is halting in BIOS with error "Nmi activated - system halted". Note : It’s booting to OS without any issue. Server Product Code : LWF2208IR848505 Server S/N : BQF900200624 FPGA Model : BD-NVV-N3000-2 FPGA S/N : 644C36123B68 Intel BIOS : 02.01.0012 OS : CentOS 7.7 Please find attached lspci output. Need your help to resolve this issue, can you please escalate this issue to Intel core development team. We are assuming this is not an hardware failure issue, it could be due to compatibility issue or new modified/beta BIOS can resolve this issue.
X2GO client connection failure: Socket Disconnected
I am trying to open graphics port on DevCloud using X2GO clien and get socket disconnected error after starting the session I have followed the steps from https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#61-opening-port-for-graphics-usage-in-x2go Before launching the session I use the command ssh -L 4002:s001-n<available node from 130-139>:22 devcloud A minute after I launch the session, I get the error authentication failed-socket error :disconnected Please find the attached images of the session properties and the error message.
oneAPI on Cyclone10gx
Hi all, the official Intel fpga requirement page says the Cyclone10gx fpga is supported by oneAPI so I downloaded the latest version on my Ubuntu20 (Quartus Prime also installed), I tried to compile a sample-adder, the compiler (targeting the fpga) works but then when I run simple-add-buffer.fpga I get: tetto@ubuntuoffice:~/simple-add/build$ ./simple-add-buffers.fpga An exception is caught while computing on device. terminate called after throwing an instance of 'sycl::_V1::runtime_error' what(): No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (PI_ERROR_DEVICE_NOT_FOUND) Aborted (core dumped)
[FPGA SDK for OpenCL] External IO channel problem.
System integrator fails when the data type size of the external IO channel is different from 256b. You can reproduce the error using the attached code. $ make trigger_bug aoc -v -v -v -D__TRIGGER_BUG__ -rtl -report -g krnl_chtest.cl -o krnl_chtest.aocr -board="p520_max_sg280l" -no-interleaving=default ... !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at krnl_chtest/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 69% ; ; ALUTs ; 35% ; ; Dedicated logic registers ; 35% ; ; Memory blocks ; 31% ; ; DSP blocks ; 29% ; +----------------------------------------+---------------------------; remove krnl_chtest.bc /cm/shared/opt/intelFPGA_pro/18.1.1/hld/linux64/bin/system_integrator --cic-global_no_interleave --bsp-flow top --rand-hash 6e2a5000a9316341eb32862b79911918a518e834 /opt/intelFPGA_pro/18.1.1/hld/board/nalla_pcie/hardware/p520_max_sg280l/board_spec.xml "krnl_chtest.bc.xml" none Compiler Error: Trying to bind incompatible signal to input port Compiler Error: Port: avm_channel_id_kernel_input_ch0_read (N9custom_ic3hdl21AvalonStreamPortGroupE) / Signal: avm_channel_id_kernel_input_ch0_read (N9custom_ic3hdl23AvalonStreamSignalGroupE) Compiler Error: Bound signal: kernel_input_ch0 (N9custom_ic3hdl23AvalonStreamSignalGroupE) Compiler Error: Compiler Error: Port signal declaration: Compiler Error: logic avm_channel_id_kernel_input_ch0_read_valid; Compiler Error: logic avm_channel_id_kernel_input_ch0_read_ready; Compiler Error: logic [31:0] avm_channel_id_kernel_input_ch0_read_data; Compiler Error: Bound signal declaration: Compiler Error: logic kernel_input_ch0_valid; Compiler Error: logic kernel_input_ch0_ready; Compiler Error: logic [255:0] kernel_input_ch0_data; Error: System integrator FAILED. Refer to krnl_chtest/krnl_chtest.log for details. make: *** [trigger_bug] Error 1 The file krnl_chtest.log doesn't provides further details. Issue found in Intel FPGA OpenCL SDK 18.0.1 and 18.1.1 for Bittware 520N. The issue is not present in Intel FPGA OpenCL SDK 17.1 for Bittware 385A. This issue is important because the definition of channels with a smaller width let possible to exploit an higher 'Occupancy%' in the case of processing 256b (related to the external io channels) per clock cycle is not needed/wanted. For example, consider a network connection with a bandwidth of 40 Gbit/s. A channel 256b-wide can transfer data at 156 Mhz maximum. The usage of such a channel in a pipeline synthesized with an higher frequency will be a relevant source of 'Stall%' (e.g. 48% in a 300 Mhz design).Can I read and write buffers simultaneously with OpenCL.
Hello, I am using the FPGA board de5net from Terasic with a Stratix V FPGA. It is connected the to host via PCIe. To obtain a hight throughput I want to read an write buffers simultaneously but unfortunately openCL executes the commands consecutively. So is it possible to read/write simultaneously at all and if yes, how can I do it? I have one device and create one context for it. Furthermore I create one queue for the read command (clEnqueueReadBuffer) and another for the write command (clEnqueueWriteBuffer). Both are called as non-blocking (CL_FALSE).