New Contributor[FPGA SDK for OpenCL] External IO channel problem.
System integrator fails when the data type size of the external IO channel is different from 256b.
You can reproduce the error using the attached code.
$ make trigger_bug
aoc -v -v -v -D__TRIGGER_BUG__ -rtl -report -g krnl_chtest.cl -o krnl_chtest.aocr -board="p520_max_sg280l" -no-interleaving=default
...
!===========================================================================
! The report below may be inaccurate. A more comprehensive
! resource usage report can be found at krnl_chtest/reports/report.html
!===========================================================================
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 69% ;
; ALUTs ; 35% ;
; Dedicated logic registers ; 35% ;
; Memory blocks ; 31% ;
; DSP blocks ; 29% ;
+----------------------------------------+---------------------------;
remove krnl_chtest.bc
/cm/shared/opt/intelFPGA_pro/18.1.1/hld/linux64/bin/system_integrator --cic-global_no_interleave --bsp-flow top --rand-hash 6e2a5000a9316341eb32862b79911918a518e834 /opt/intelFPGA_pro/18.1.1/hld/board/nalla_pcie/hardware/p520_max_sg280l/board_spec.xml "krnl_chtest.bc.xml" none
Compiler Error: Trying to bind incompatible signal to input port
Compiler Error: Port: avm_channel_id_kernel_input_ch0_read (N9custom_ic3hdl21AvalonStreamPortGroupE) / Signal: avm_channel_id_kernel_input_ch0_read (N9custom_ic3hdl23AvalonStreamSignalGroupE)
Compiler Error: Bound signal: kernel_input_ch0 (N9custom_ic3hdl23AvalonStreamSignalGroupE)
Compiler Error:
Compiler Error: Port signal declaration:
Compiler Error: logic avm_channel_id_kernel_input_ch0_read_valid;
Compiler Error: logic avm_channel_id_kernel_input_ch0_read_ready;
Compiler Error: logic [31:0] avm_channel_id_kernel_input_ch0_read_data;
Compiler Error: Bound signal declaration:
Compiler Error: logic kernel_input_ch0_valid;
Compiler Error: logic kernel_input_ch0_ready;
Compiler Error: logic [255:0] kernel_input_ch0_data;
Error: System integrator FAILED.
Refer to krnl_chtest/krnl_chtest.log for details.
make: *** [trigger_bug] Error 1The file krnl_chtest.log doesn't provides further details.
Issue found in Intel FPGA OpenCL SDK 18.0.1 and 18.1.1 for Bittware 520N.
The issue is not present in Intel FPGA OpenCL SDK 17.1 for Bittware 385A.
This issue is important because the definition of channels with a smaller width let possible to exploit an higher 'Occupancy%' in the case of processing 256b (related to the external io channels) per clock cycle is not needed/wanted.
For example, consider a network connection with a bandwidth of 40 Gbit/s. A channel 256b-wide can transfer data at 156 Mhz maximum.
The usage of such a channel in a pipeline synthesized with an higher frequency will be a relevant source of 'Stall%' (e.g. 48% in a 300 Mhz design).
