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PGorl1's avatar
PGorl1
Icon for New Contributor rankNew Contributor
6 years ago

[FPGA SDK for OpenCL] External IO channel problem.

System integrator fails when the data type size of the external IO channel is different from 256b. You can reproduce the error using the attached code. $ make trigger_bug aoc -v -v -v -D__TRIGGER...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
Icon for Contributor rankContributor
6 years ago

Hi,

I have shared the case with our Engineering team, there is no change in HLD tools from 17.1 to 18.0 that would have caused this. System integrator now enforces bit width checking to prevent and mismatches in this case.

. In summary tool behavior in 17.1 (to let width mismatch compile) was a bug and the behavior is correct now.

You can just pad the unused 224 bits of the i/o channel in the kernel code to get the desired effect. Or better yet, make use of all 256 bits.

Thanks,

Arslan

  • HRZ's avatar
    HRZ
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    How was this a "bug" in v17.1 when everything worked correctly and there was no crash/data corruption/etc? I wrote a test for the serial I/O channel between the two FPGAs on the dual-Arria 10 Nallatech 510T board (https://github.com/zohourih/FPGAStream/blob/master/fpga-stream-kernel-sch.cl) and regardless of bit width (both lower and higher than the physical 256-bit width), I verified the integrity of data passing through the channel in all cases and nothing was ever corrupted [unless I did something wrong somewhere]. I also verified that channel throughput scaled linearly with data size until the channel's bandwidth was saturated. This led me to believe that the compiler adds a buffer between the kernel and the I/O interface to adjust the data width. In fact, such buffer will be required anyway since the kernel is running at a different clock than the I/O channel and I fail to see how the same buffer cannot be used to also adjust the data width.