[FPGA SDK for OpenCL] External IO channel problem.

Hi,

BittWare has recreated this behavior compiling against the 19.1 520 BSPs, and using the 19.1 OpenCL Compiler with an Arria10 BSP.

Attached is an example showing how to transfer data using the IO channels where the data is less than the 256b. Hopefully, this may be of some use whilst you await a response from Intel. The example transfers two 128b data words every 2nd kernel clock cycle. This enables the kernel to maintain the kernel clock rate and should alleviate the IO channels as a source of stall. In the examples case an even number of words must always be transmitted.

None of the previous and current versions of the Bittware BSPs contain any logic to resize IO channel interfaces automatically. Any success on previous BSPs is likely due to logic added by the Intel aoc compilation process.

Thanks,

Gildas,

BittWare