[rdnode@localhost paderborn_io_chan_bug]$ aoc -v -v -v -D__TRIGGER_BUG__ -rtl -report -g krnl_chtest_a10gx_hostpipe.cl -o krnl_chtest_pipe.aocr -board="a10gx_hostpipe" -no-interleaving=default ##aoc: Environment checks are completed successfully. ##aoc: Cached files in /var/tmp/aocl/ may be used to reduce compilation time ##aoc: Selected target board a10gx_hostpipe ##aoc: Running OpenCL parser.... /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-clang -cc1 -emit-llvm-bc -O3 -disable-llvm-passes -x cl -cl-std=CL1.2 -dwarf-column-info -ffpga -DINTELFPGA_CL=191 -triple spir64-unknown-unknown-intelfpga /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_a10gx_hostpipe.cl -include /opt/intelFPGA_pro/19.1.0/hld/share/lib/acl/opencl_lib.h -o /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe.411973.temp/krnl_chtest_a10gx_hostpipe.pre.bc -MT krnl_chtest_a10gx_hostpipe.bc -sys-header-deps -dependency-file /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe.411973.temp/krnl_chtest_a10gx_hostpipe.d -D__TRIGGER_BUG__ -debug-info-kind=limited -dwarf-version=4 -Wunknown-pragmas -Wuninitialized -ivfsoverlay-lib/opt/intelFPGA_pro/19.1.0/hld/linux64/lib/libaoc_clang_decrypt.so ##aoc: OpenCL parser completed successfully. ##aoc: Linking Object files.... ##aoc: Cleaning up existing temporary directory /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe touch /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe/.project.marker ##aoc: Adding wild-carded AUTO_SHIFT_REGISTER_RECOGNITION assignment to /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe/flat.qsf ##aoc: Adding wild-carded AUTO_SHIFT_REGISTER_RECOGNITION assignment to /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe/top.qsf ##aoc: Adding wild-carded AUTO_SHIFT_REGISTER_RECOGNITION assignment to /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe/base.qsf ##aoc: Adding wild-carded AUTO_SHIFT_REGISTER_RECOGNITION assignment to /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe/opencl_bsp_ip.qsf remove /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe.aoco.d.temp /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-link -irmover-type-merging=0 /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe.linked.aoco.bc /opt/intelFPGA_pro/19.1.0/hld/share/lib/acl/acl_early.bc -o krnl_chtest_a10gx_hostpipe.1.bc remove /home/rdnode/progers/19_1/p520/paderborn_io_chan_bug/krnl_chtest_pipe.linked.aoco.bc /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-opt -rewritetofpga "krnl_chtest_a10gx_hostpipe.1.bc" -o "krnl_chtest_a10gx_hostpipe.fpga.bc" remove krnl_chtest_a10gx_hostpipe.1.bc ##aoc: Optimizing and doing static analysis of code... /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-opt -march=fpga -O3 -board /opt/intelFPGA_pro/19.1.0/hld/board/a10_ref/hardware/a10gx_hostpipe/board_spec.xml -dbg-info-enabled --soft-elementary-math=false -pass-remarks-output=pass-remarks.yaml "krnl_chtest_a10gx_hostpipe.fpga.bc" -o "krnl_chtest_a10gx_hostpipe.kwgid.bc" ##aoc: Linking with IP library ... /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-opt -insert-ip-library-calls -dbg-info-enabled --soft-elementary-math=false "krnl_chtest_a10gx_hostpipe.kwgid.bc" -o "krnl_chtest_a10gx_hostpipe.lowered.bc" remove krnl_chtest_a10gx_hostpipe.kwgid.bc /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-link -irmover-type-merging=0 krnl_chtest_a10gx_hostpipe.lowered.bc /opt/intelFPGA_pro/19.1.0/hld/share/lib/acl/acl_late.bc -o krnl_chtest_a10gx_hostpipe.linked.bc remove krnl_chtest_a10gx_hostpipe.lowered.bc /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-opt -board /opt/intelFPGA_pro/19.1.0/hld/board/a10_ref/hardware/a10gx_hostpipe/board_spec.xml -always-inline -phase-3-inst-simplify -dce -stripnk -rename-basic-blocks -dbg-info-enabled --soft-elementary-math=false "krnl_chtest_a10gx_hostpipe.linked.bc" -o "krnl_chtest_a10gx_hostpipe.bc" remove krnl_chtest_a10gx_hostpipe.linked.bc /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/../../llvm/bin/aocl-llc -march=fpga -board /opt/intelFPGA_pro/19.1.0/hld/board/a10_ref/hardware/a10gx_hostpipe/board_spec.xml -pass-remarks-input=pass-remarks.yaml -use-swdimm=default -dbg-info-enabled "krnl_chtest_a10gx_hostpipe.bc" -o "krnl_chtest_a10gx_hostpipe.v" remove pass-remarks.yaml ##aoc: Checking if memory usage is larger than 100%... ##aoc: Memory usage is not above 100. remove krnl_chtest_a10gx_hostpipe.fpga.bc !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at krnl_chtest_a10gx_hostpipe/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 16% ; ; ALUTs ; 9% ; ; Dedicated logic registers ; 8% ; ; Memory blocks ; 13% ; ; DSP blocks ; 0% ; +----------------------------------------+---------------------------; remove krnl_chtest_a10gx_hostpipe.bc /opt/intelFPGA_pro/19.1.0/hld/linux64/bin/system_integrator --cic-global_no_interleave --bsp-flow top --rand-hash 0e31a03ce45e8d77f2cdaaeb08417ff14839dbfa /opt/intelFPGA_pro/19.1.0/hld/board/a10_ref/hardware/a10gx_hostpipe/board_spec.xml "krnl_chtest_a10gx_hostpipe.bc.xml" none Compiler Error: Trying to bind incompatible signal to input port Compiler Error: Port: avm_channel_id_host_to_dev_read (N9custom_ic3hdl21AvalonStreamPortGroupE) / Signal: avm_channel_id_host_to_dev_read (N9custom_ic3hdl23AvalonStreamSignalGroupE) Compiler Error: Bound signal: host_to_dev (N9custom_ic3hdl23AvalonStreamSignalGroupE) Compiler Error: Compiler Error: Port signal declaration: Compiler Error: logic avm_channel_id_host_to_dev_read_valid; Compiler Error: logic avm_channel_id_host_to_dev_read_ready; Compiler Error: logic [31:0] avm_channel_id_host_to_dev_read_data; Compiler Error: Bound signal declaration: Compiler Error: logic host_to_dev_valid; Compiler Error: logic host_to_dev_ready; Compiler Error: logic [255:0] host_to_dev_data; Error: System integrator FAILED. Refer to krnl_chtest_pipe/krnl_chtest_a10gx_hostpipe.log for details. [rdnode@localhost paderborn_io_chan_bug]$