New Contributor
ContributorHi @PGorl1, I am the manager to the engineer assigned to this case. Can you please elaborate a little more about you meant that doing the approach will add penalties in terms of performances: lower fmax and Occupancy%? Do you have any data that you could provide to support this so that we can evaluate at our end on what we can do differently?
New ContributorHi @NRaml,
we re-synthesized our designs with the 19.1.0 BSP. Now, the suggested work around that implements 128b-wide channels works better. We are able to achieve a good Occupancy%.
We tested the work around by connecting the RX and TX kernels to another FPGA card which receives/transmits data using 256b-wide channels at full throughput.
The theoretical peak throughput of the external channel in case of work around kernels can be computed as
Peak throughput = 256b * min(0.5*fmax, 156.25Mhz)
Considering the code proposed by GGene, the original problem was in the TX kernel (see attached image).
In the 18.1.1 BSP, the Occupancy% and consequently the percentage of achieved theoretical peak throughput was equal to 83%. With the 19.1.0 BSP, this value is 97%.
For now, we are getting the same Occupancy% also for other designs that implement this kind of work around.
Cheers,
Paolo
