Can I read and write buffers simultaneously with OpenCL.

​Hi,

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Please do expect some delay in response as most of our agents are out of office due to the year-end holidays. Thank you.

Regards,

Nooraini

Indeed you can read and write from/to two different buffer simultaneously. You should create two queues, one for each operation, and set the third parameter in clEnqueueRead/WriteBuffer to CL_FALSE so that the operations are performed in a non-blocking fashion. You can then use OpenCL events to synchronize the operations. Also this topic should probably be in the “FPGA Design Tools” section.

Hi @MN.​

I am looking at this thread now, may I know what version of compiler you are using ?

Also I understand you are looking at the execution by analyzing OpenCL profiler result, is this correct ?

Thanks,

Arslan

During the work with my FPGA Board (DE5net from Terasic with a StratixV FPGA from 2012) there occured a few more questions:

I want to implement an algorithm for bioinformatics. According to our theoretical analysis the transfer rate from the host to the board via PCIe will be the bottleneck. So I need to stream into the FPGA with the peak performance of PCIe. Furthermore I have to execute several kernel parallel. So is it possible, the my board is simply too old and the available OpenCL implementation does not satisfy this demand? If my board is too old, do you could redommend me one which is more appropriate for me?

Furthermore I'm wondering if you have a redbook for programming this board with OpenCL and a full documentation of the exact implementation of OpenCl?

Because the OpenCL Implementation for my board does only support PCIe gen2 I took also a look at Intel HLS because there PCIe gen3 is available. Do you have a full documentation of it? I didn't find any.

If you are sure your bottleneck is going to be the PCI-E transfer, there is no point in accelerating your application on a PCI-E-attached accelerator, be it FPGA, GPU or anything else. Running it on a CPU could be the best solution since the PCI-E transfer will be avoided. Furthermore, all OpenCL-capable Stratix V and Arria 10 boards that I know of are limited to 8x PCI-E while you can at least get 16x PCI-E on nearly all GPUs from the past few years which means they will be a better option for you.

The reason why you cannot run your kernels simultaneously likely has very little to do with the board you are using. There is either something in your host code preventing your kernels from running in parallel or there is some limitation in Altera/Intel's OpenCL run-time which is board-independent. As I mentioned in my previous reply, I have personally run kernels in parallel successfully on the same board. You can find the design here (v8 kernel):

https://github.com/fpga-opencl-benchmarks/rodinia_fpga/tree/35b061f6b9c976dc44f86d6c2bd007c756c64349/opencl/lud/ocl

Are you sure the OpenCL implementation of your board only supports PCI-E Gen 2.0? My Stratix V board is installed on a machine that only supports Gen 2.0 and hence, it has to run at Gen 2.0, but my Arria 10 board runs at Gen 3.0 on a newer motherboard without any issue. Maybe your motherboard doesn't support Gen 3.0?

Terasic's documentation for the DE5-Net board are here:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=158&No=526&PartNo=4

Intel FPGA SDK for OpenCL's documents are here:

https://www.intel.com/content/www/us/en/programmable/products/design-software/embedded-software-developers/opencl/support.html

Intel HLS documents are here:

https://www.intel.com/content/www/us/en/programmable/products/design-software/high-level-design/intel-hls-compiler/support.html

These links include all the official documents available.

@NYusof

Do you know, if Intel plans to support OpenCL PCIe 16x gen3 in future, and if yes, when do you think it's available?

Thanks

MN