OneAPI Support for Agilex 5 and 7 Development Kits
Hello, I've recently acquired an Agilex 5 065B Modular development kit (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html) and an Agilex 7 I-Series development kit (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html). I've been working through setting up the development environments for these boards, and would like to use the oneAPI HLS toolkit for them, if possible. So far, I've found a tutorial to create an accelerator support package for the Agilex 7 development kit that I have (https://ofs.github.io/ofs-2024.3-1/hw/common/user_guides/oneapi_asp/ug_oneapi_asp/). I'm planning to go through these steps shortly to setup my board for use with oneAPI, but I have yet to find any documentation for my Agilex 5 board. Is it possible to work with this Agilex 5 development kit using oneAPI, or is only the Quartus design flow supported at this time? Additionally, are there board support packages available (that I've just missed) - or soon to be available - for these cards if the HLS flow is an option? Thank you!
HAL Kernel Version Mismatch Error During FPGA Emulation with vector-add Sample
Hello Intel FPGA team, I'm currently working on the vector-add example from the official oneAPI-samples repository, specifically from: DirectProgramming/DPC++/DenseLinearAlgebra/vector-add I’m encountering the following runtime error when I attempt to run the emulation build: Error output: ./vector-add-buffers.fpga_emu HAL Kern: Version mismatch! Expected 0xa0c00001 but read 0x4130 Hardware version ID differs from version expected by software. Either: a) Ensure your compiled design was generated by the same ACL build currently in use, OR b) The host can not communicate with the compiled kernel. vector-add-buffers.fpga_emu: /nfs/sc/disks/swip_hld_1/ops/SC/hld/nightly/2022.1/96.2/l64/work/acl/acl/source/57c9d2bcb46afcf445b5da2406c0e6d85be93ef3/src/acl_kernel_if.cpp:733: int acl_kernel_if_init(acl_kernel_if*, acl_bsp_io, acl_system_def_t*): Assertion `0' failed. make: *** [Makefile.fpga:35: run_emu] Error 1 Environment details: Board: DE10-Agilex BSP Path: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/board/de10_agilex oneAPI version: Installed multiple versions. Active: 2022.0.2 dpcpp path: /opt/intel/oneapi/compiler/2022.0.2/linux/bin/dpcpp OS: Ubuntu (detected as Rocky Linux during install attempts) What I have tried: Verified the AOCL_BOARD_PACKAGE_ROOT is correctly set. Recompiled the design using make clean && make fpga_emu. Ran aoc -list-board-packages to confirm the installed board. Ensured Quartus, BSP, and compiler are aligned. Despite that, I still encounter the HAL version mismatch. Request: Could someone guide me on how to: Resolve this version mismatch issue? Confirm the correct environment and runtime versions are in sync? Completely clean older/duplicate oneAPI installations if that’s the root cause? @intel @OneAPI @fpga @agilex7 @de10 @intel6
PCIe 4.0 Example for Agilex 7 M-Series
Hello, We purchased this Agilex 7 M-Series Dev Kit (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html) for a project, and we're having trouble locating the design example for PCIe mentioned in the documentation. We could, however, identify an example in the documentation of the I-Series board, but the pin mapping is not straightforward. Could you please provide an example or documentation on configuring a basic design using the PCIe for the Agilex™ 7 FPGA M-Series Development Kit—HBM2e Edition (3x F-Tile & 1x R-Tile)? Also, is there any chance a BSP will be released for this dev kit? Thanks, Denisa
Understanding FPGA AI Suite with Quartus
Hi, I am new to the FPGA AI Suite and would appreciate your help in better understanding it. Referring to the attached Intel pipeline, specifically the path involving Quartus: When Quartus is involved, is the OpenVINO runtime inference engine still required to run the application? I assume that IP files are imported into Quartus. Do these files contain the model topology and weights needed to run the application, or is Quartus solely used to configure the FPGA hardware, with the inference handled by the OpenVINO runtime (via FPGA AI Suite)? If I test the model using a deep learning framework and then use the FPGA AI Suite, how can I effectively collaborate with the FPGA developer? I hope my questions are clear. Best regards.
