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Annu's avatar
Annu
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1 month ago

Debugging the FPGAs connected in passive serial mode

I have two cyclone 3 devices(EP3C16F484C8 & EP3C5F256C8) which is connected in passive serial mode. I wanted to debug the device and only JTAG connection is available to do so. I don't want to change...
Configuration
Core Logic
Programmable Logic Device
Annu's avatar
Annu
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1 month ago

I know the JTAG boundary scan is slow can we use VJTAG for this. If yes, how is it done? and also any manual for JTAG boundary scan is available

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

For internal core issue, SignalTap will be the best solution. For Boundary Scan, you can only debug interface pin issue and the detection will be very slow and not efficient for interface pin that keep on toggling.