Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
writing a word to cfm1 using on chip flash ip on max10
hii i have the neek board development kit , and i am writing my own logic to perform a writing of an image to cfm1 flash sector for remote update i am transferring the image through uart from rpd file just like in nios rsu example lab . i configured the on chip flash ip in this parameters data interface :parallel read burst mode :incrementing read burst count:8 configuration mode :dual compressed images i set the burstcount to 1 I managed to erase the CFM1 sector, and I read the status register to confirm that the erase of sectors 3 and 4 was successful. Sector 3 + 4 corresponds to CFM1. Before performing the write operation, I verify that the on-chip flash is in the idle state by reading the CSR status register. I place the word on the data_writedata signal of the Avalon bus with the correct address, assert the data_write signal, and then wait until waitrequest goes low before proceeding to the next word. I confirm that the write was successful by reading the ‘write successful’ bit in the CSR status register. but sometimes in the middle of the file transfer , i get a write failure and i am not sure why , my clock on board is 50 mhz and i am using pll to generate 75mhz. so i i am feeding the 75mhz clock to the on chip flash ip and my own writing fsm logic Using SignalTap, I can see that the word before the one where the write failed was written successfully. I send each word over the UART interface with a delay of 2.5 ms, which I believe is sufficient for the write to complete. I also check the waitrequest signal before proceeding to the next word and verify that the on-chip flash is in the idle state.” I would be thankful to know why I am getting a write failure and what I should check to resolve this issue? thanks
about cyclone 10gx transceiver
Hi, recently I am trying to debug cyclone 10 gx transceivers, and the settings are as the figures above. After reseting, I first send 32'h12345678 as the control world, and set tx_control[1:0] = 2'b10. During this time, in my logic I using rx_bitslip to slip the bits until rx_parallel_data is equal to 32'h12345678. After that, I continually send incremental counter value through transmitter with tx_control[1:0] = 2'b01, but the receiver gets rx_control[1:0] equal to 1, 2, 3, changing all the time, which is shown as following figure. So, did I set parameters wrongly? Or how can l solve it? Thank you.
Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank youLLM Implementation on Agilex 5 E-Series 065B Modular Dev Kit
I am currently working on deploying Large Language Model (LLM) inference using FPGA AI Suite on the Agilex 5 E-Series 065B Modular Development Kit. I have two clear and specific questions: Is the Agilex 5 E-Series 065B officially supported for LLM / Transformer inference with FPGA AI Suite? Is the following workflow officially supported for LLM inference on this board? Step 1: Export a pre-trained LLM from Hugging Face to OpenVINO IR format using optimum-intel Step 2: Generate the target FPGA architecture file using architecture_optimizer for Agilex 5. Step 3: Compile the OpenVINO IR model for the FPGA using: • dla_compiler → for Sequential flow, or • Spatial Compiler → for Spatial flow. Step 4: Integrate the generated FPGA AI Suite IP into a Quartus Prime project, generate the bitstream, and program it onto the Agilex 5 E-Series 065B board. Step 5: Run inference using the FPGA AI Suite runtime (host application). I understand this may not be a push-button process and could require significant modifications to the generated RTL — but is this workflow still considered a viable starting point for implementing LLM / Transformer inference on the Agilex 5 E-Series 065B? Thank you.Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chips
Hello Guys, I read one post here, which requested the way to design carry chain style TDC based on Agilex 9 chips. Here is that post linkcarry chain tdc | Altera Community - 351924 Kenney answer that post and give some recommendations about it. Now I have similar questions about carry chain TDC by using ALTERA's Cyclone 10 GX. Is that wire LUT delay lines in Cyclone 10 Gx devices?
Agilex5 / IBIS HSIO - LPDDR4
Hi, number of IBIS models for banks HSIO listed in ag-5-device-list-of-ibis-models.xlsx, is very important (several thousands). We are interfacing LPDDR4 on our HSIO banks at standard LVSTL11 single and diff. When generating an EMIF IP for that need, without touching defaults parameters (hereafter) , which are IBIS models to use among that list ? We are supposing « lvstl11_io_s3r40c_doff » and « dlvstl11_io_s3r40c_doff ».
