Backplane Ethernet 10GBASE-KR PHY FPGA IP
I would like to know more information about the Intel\Altera Backplane Ethernet 10GBASE-KR PHY FPGA IP . Can it be implemented in the Agilex 5 FPGA ? If not are there any plans to incorporate it there and what would be the time frame ? Also what type of license is offered. I tried the site contact :- https://www.altera.com/products/ip/po-3078/backplane-ethernet-10gbase-kr-phy-fpga-ip twice but I got no response ???
MAX10 DDR3 Timing
Hi, I need a definitive statement regarding the timing. The two attached screenshots were created with Quartus 23.1 but can also be found in 25.1. Although adjusting the temperature range reduced the number of failing paths (see screenshot 800MHz_300MHz_DDR3_1, which ran at -40°C to 100°C), there remain parts that do not meet the timing. According to the datasheet, this should work. The MAX10 being used is a 10M16DAF484I6G, which is the fastest speed grade. The memory is Micron MT41K256M16TW-107AAT. Br, Korbinian
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Agilex 5 Sulfur Partial Write Issue on F2H ACE‑Lite I/F (256‑bit) with AXI Master of 128‑bit
Hello Intel Support Team, I am working on an Agilex 5 Sulfur Development Board and implementing an HPS‑based design where a USB Host module (custom logic) acts as an AXI Master and performs memory accesses to SDRAM through the F2H ACE‑Lite interface. I am seeing an issue related to partial writes when the AXI data width is translated from 128‑bit to 256‑bit before reaching the F2H bridge. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Design Summary AXI Master (USB host logic) Address width: 32 bits Write data width: 128 bits Write strobe (WSTRB): 16 bits Interconnect Path (Platform Designer) The Master AXI interface passes through the following autogenerated components: mm_interconnect_0_ace5lite_cache_coherency_translator ace5lite_cache_coherency_translator ACE‑Lite Interface to F2H Address width: 32 bits Write data width: 256 bits Write strobe: 32 bits Observed Behavior (via SignalTap) The 128‑bit write data is properly expanded to 256‑bit by the translator. The 16‑bit WSTRB is correctly translated to 32‑bit, with only the lower or upper half asserted as expected. The AXI address falls correctly within the SDRAM region. The writes propagate through CCU → MPFE correctly (based on external visibility). Problem When reading back SDRAM from software running on the HPS, we observe that: 👉 The entire 256‑bit word in SDRAM is modified, even though 👉 only 128 bits of WSTRB were asserted on the ACE‑Lite interface. SignalTap shows the correct WSTRB on the F2H side, but SDRAM readback indicates that the "inactive" 128‑bit lanes are also being overwritten. Because the HPS subsystem is a hard macro, we cannot probe signals inside the CCU / MPFE / F2H bridge to see what is actually happening after the ACE‑Lite boundary. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Questions for Intel We would greatly appreciate guidance on the following: 1. ACE‑Lite 256‑bit Partial Write Support Are there any documented limitations or required settings for partial‑word writes on the 256‑bit F2H ACE‑Lite interface in Agilex 5? 2. MPFE / SDRAM Controller Behavior Does the MPFE / CCU / SDRAM controller internally convert all writes to full‑width beats, regardless of WSTRB? If so, is there a way to ensure correct byte‑enable behavior? 3. Required Qsys Settings? Are there specific configuration requirements for: The ACE‑Lite translator Interconnect pipeline stages Burst alignment Address alignment for partial writes Write‑data interleaving settings 4. Debugging Recommendations Since internal HPS signals cannot be probed, is there: Any documented method to trace ACE‑Lite transactions inside HPS? Any diagnostic registers or trace capabilities in CCU/MPFE? Any recommended debug flow for this type of issue?
Cyclone 10 LP's Extended Industrial parts
[Question] Customer have questions about Cyclone 10 LP's Extended Industrial (Tj = -40degC to 125degC) in the Product Catalog at the following URL. https://www.intel.com/content/www/us/en/content-details/730595/altera-product-catalog.html What is part number of Extended Industrial of "10 CL010YM164I7 G" as part number of Normal Industrial? What should the customer do if they want to check the power consumption by EPE(Early Power Estimator)? How can the customer design with Extended Industrial part if they want to compile with Quartus? Best Regards
[Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout
Device: Agilex 5 Issue Description: The Timing Analysis report indicates that a specific PLL output clock has a fanout of 21343(see screenshot below). Does this high fanout on non-global routing imply that the clock failed to be promoted to the Global Clock Network? Suspecting this was the issue, I configured the "Global Signal" assignment to "On" in the Assignment Editor and recompiled the design. However, this setting appears to be ineffective，the fanout still 21343. 【set_instance_assignment -name GLOBAL_SIGNAL ON -to u0|clock_subsystem|iopll|iopll_1|tennm_ph2_iopll~O_OUT_CLK0】 Could you please advise if this needs to be addressed and how to successfully enforce the Global Clock assignment? Thanks.
