Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!
TSE MAC+PCS (SGMII, Cyclone 10 GX): mdio_out/mdio_oen never toggle, no matter what I write
Cyclone 10 GX (10CX220Y), Triple-Speed Ethernet IP: core_variation=MAC_PCS, transceiver_type=NONE (external LVDS SERDES, TBI), enable_sgmii=true, enable_use_internal_fifo=true, useMDIO=true. Trying to read/write an external Marvell 88E1111 over MDIO via the MAC's control_port (System Console + JTAG-to-Avalon). Verified working: basic CSR read/write (rev, scratch_pad), tse_rst=0 / xcvr_ready=1 (out of reset), mdc toggling correctly at 1.25MHz on the pin, MDIO_ADDR0 (0x0F) and MDIO_ADDR1 (0x10) are real R/W registers (write/readback matches), mdio_oen tri-state glue matches Intel's own reference template exactly. Not working: I added (* preserve *) to mdio_in/mdio_out/mdio_oen and tapped them directly with SignalTap on TSEIP's own ports. With a falling-edge trigger on mdio_out, and while repeatedly writing MDIO_ADDR0/MDIO_ADDR1 and reading/writing both the phy0 (0x40+n) and phy1 (0x60+n) windows with genuinely varying values — mdio_out never shows a single transition. Since even a bare MDIO read frame must produce at least one falling edge (end of the all-1s preamble), this looks like no real MDIO transaction is ever being started from the CSR side. What am I missing — is there another enable/start bit or busy/status flag needed to actually kick off an MDIO transaction on this core_variation/config? Any pointer to the MDIO register section for this exact IP version (Quartus Prime Pro 24.1) would help too.
8 port 10/25G ethernet interface in Stratix 10
We have custom board made with Stratix 10 1ST085EN2F43I2LG. The board has 8 SFP28 ports the needs to talk to 10/25G ethernet devices. This board is used to test the connected devices by sending a fixed Ethernet packets and analyse the received Ethernet packets. The SFP ports needs to be selectable between 10G and 25G and enable/Disable RS-FEC. Also need the MAC statistics registers and PTP timestamping. We could see two different IP cores available for this in the IP catalogue, 25G Ethernet Stratix 10 IP, and Ethernet Stratix 10 E-Tile Hard IP. Which one is the right IP for this requirement.
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
We are trying to use the Infineon S25FS512S QSPI NOR Flash with Cyclone 10 GX in Active Serial x4 (AS x4) configuration by creating a Custom Flash Definition based on AN229767. JTAG programming completes successfully, but FPGA configuration fails in AS x4 mode. We have performed extensive debugging and would like to understand whether this is a supported use case or if there are any known limitations. Observations Flash Programming JTAG programming completes successfully. Flash verification completes successfully. Configuration Behavior Active Serial x1 configuration works correctly. Active Serial x4 configuration fails. The FPGA successfully issues the RDID (0x9F) command. The FPGA then attempts to read the Boot Information from address 0x00000000. Logic Analyzer Observation During AS x4 configuration, the FPGA issues the EBh (Quad I/O Read) command. According to the Infineon S25FS512S datasheet, the expected transaction is: EBh → 4-byte Address → Mode Byte (8 bits) → Dummy Cycles → Data However, the captured waveform shows: EBh → 4-byte Address → Dummy Cycles → Data No Mode Byte is observed between the address and dummy cycles. Based on the S25FS512S command protocol, this could cause the flash to interpret the transaction differently and return misaligned data. We would like Altera to confirm whether this behavior is expected from the Cyclone 10 GX configuration controller. Additional Information We reviewed AN229767, but could not find any mechanism in the Custom Flash Definition to configure or insert the Mode Byte required by the EBh command. We also observed that the Custom Flash Definition supports Read Register commands only for fixed register opcodes and does not appear to support RDAR (0x65) with a register address. Questions Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command? If not, is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer? Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition? Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference? Environment FPGA: Cyclone 10 GX Flash: Infineon S25FS512S Configuration Mode: Active Serial x1 (working), Active Serial x4 (failing) Programming Method: Quartus Programmer using a Custom Flash Definition based on AN229767 We would appreciate any guidance, clarification, or a reference implementation for using the S25FS512S with Cyclone 10 GX in Active Serial x4 mode.
JESD204B RX Link Never Achieves CGS at 12.8 Gbps on S10 ES (1SG280LU3F50E3VGS1, Quartus Pro 17.1)
Hi Team, I am using the Intel JESD204B RX Example Design on a Stratix 10 GX Engineering Sample FPGA (1SG280LU3F50E3VGS1, L-Tile) with Quartus Prime Pro 17.1.I have two JESD204B configurations using the same board, RTL, and hardware. Case 1 (Working):ADC Clock = 1228.8 MHz, Decimation = 6 Lane Rate = 8.192 Gbps REFCLK (Core/XCVR) = 409.6 MHz Link/Frame Clock = 204.8 MHz SYSREF = 6.4 MHz This configuration works correctly and the JESD link comes up successfully. Case 2 (Not Working): ADC Clock = 1280 MHz Decimation = 4 Lane Rate = 12.8 Gbps REFCLK (Core/XCVR) = 640 MHz Link/Frame Clock = 320 MHz SYSREF = 5 MHz The JESD204B parameters are identical in both cases: L = 4 M = 8 F = 4 S = 1 N = 16 NP = 16 K = 32 Subclass 1 In the failing case, the following status is observed: Core PLL Locked = Yes ADC PLL Locked (Register 0x056F = 0x80) rx_is_lockedtodata = 0xF rx_ready = 0x0F rx_cal_busy = 0 rx_analogreset = 0 rx_digitalreset = 0 jesd204_rx_link_ready = 1 jesd204_rx_link_valid = 0 The Debug Link Buffer outputs are always zero: jesd204_rx_dlb_kchar_data = 0 jesd204_rx_dlb_data_valid = 0 jesd204_rx_dlb_data = 0 jesd204_rx_dlb_disperr = 0 jesd204_rx_dlb_errdetect = 0 Therefore, no CGS (/K28.5/) characters are detected and the link never progresses beyond this point. I have verified the following: ADC SPI configuration is correct.SYSREF is present on both ADC and FPGA.Register 0x0120 is written with 0x1C and correctly reads back 0x18 after SYSREF capture.Register 0x056E is configured correctly for the 12.8 Gbps lane rate.Register 0x0201 is set correctly for decimation by 4.REFCLK, Link Clock, and Frame Clock frequencies are correct.Native PHY calibration completes successfully.No Quartus warnings are reported.The Intel example design is used without RTL modifications.I also tried lane swapping and RX polarity inversion, but the result was unchanged.This 12.8 Gbps configuration has never worked even once since the beginning, whereas the 8.192 Gbps configuration works reliably on the same hardware. Could you please advise: Is there any known limitation or errata for Stratix 10 ES (1SG280LU3F50E3VGS1 L-Tile) at 12.8 Gbps?Is any additional Native PHY or transceiver configuration required for 640 MHz reference clock and 12.8 Gbps lane rate?Are there any known issues in Quartus Prime Pro 17.1 related to JESD204B RX at this operating point?Any suggestions on additional debug steps would be greatly appreciated.AXI violation on H2F interface of S10
I'm using the H2F AXI interface to access external RAM via EMIF on an S10 SX SoC DK (1SX280HU2F50E1VGAS). There are situations where I see the valid signal of the W channel go from 1 to 0 while the ready signal is 0. This is a violation of the valid/ready handshake protocol of AXI. After a while the system freezes because no more write transaction are accepted on the AW channel. What can cause this? Are there any known bugs in the bus master of the HPS? Here is a waveform I sampled with SignalTap that shows the behavior: There is a Linux 6.1 running on the ARM core. The RAM on the FPGA side is used for video memory. It is listed in the device tree and our drivers use it to make video memory allocations. The memory is then mapped into user space and our test application transfers data into the memory (e.g. texture data).Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
