Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Signal counts incorrectly on EP4CE6E22C8N while others signal work fine (same code Verilog)
I am facing a strange issue on FPGA EP4CE6E22C8N (Cyclone IV), i use quartus II 13.0 and signaltap to debug. I have three input signals running in parallel, using the same HDL code and the same timing standard. Two signals work correctly, but one signal always counts incorrectly, even though the input waveform itself looks correct so i donn't know problem is hardware,software, setup quartus or all of its. Design description - The module counts the length of LOW level of signal inside a valid window. - The longest LOW segment is stored as max_len and max_pos. - The input signal is synchronized using a 3 flip-flop synchronizer. - Debugging is done using SignalTap, and the input signals are confirmed to be correct. Verilog Source Code module counter_max_in_segN #( parameter SEG_N_START_PIXEL_NUMBER, parameter SEG_N_END_PIXEL_NUMBER, parameter OFFSET_SEG_N, parameter MAX_CLK_COUNTER ) ( input wire clk, input wire rst, input wire sp, input wire vN_signal, output reg [9:0] out_len, output reg [9:0] out_pos, output wire be_cover ); reg [2:0] vN_sync_reg = 3'b111; wire vN_clean; reg [9:0] clk_counter = 10'd0; reg [9:0] max_len = 10'd0; reg [9:0] max_pos = 10'd0; reg [9:0] counter_shadow = 10'd0; reg [9:0] counter_pos = 10'd0; reg becover = 1'b0; assign be_cover = becover; always @(posedge clk) begin vN_sync_reg <= {vN_sync_reg[1:0], vN_signal}; if (sp || ~rst) begin clk_counter <= 10'd0; max_len <= 10'd0; max_pos <= 10'd0; out_len <= 10'd0; out_pos <= 10'd0; counter_pos <= 10'd0; counter_shadow <= 10'd0; becover <= 1'b0; end else begin clk_counter <= clk_counter + 1'b1; if (clk_counter > 10'd71 && clk_counter <= SEG_N_END_PIXEL_NUMBER + 10'd71) begin if (vN_clean == 1'b0) begin becover <= 1'b1; counter_pos <= clk_counter - 10'd71; counter_shadow <= counter_shadow + 10'd1; end else begin becover <= 1'b0; if (counter_shadow >= max_len) begin max_len <= counter_shadow + 10'd3; max_pos <= counter_pos; end counter_shadow <= 10'd0; counter_pos <= 10'd0; end end else if (clk_counter > 10'd288 + 10'd71 && max_len != 10'd0 && max_len <= max_pos) begin out_len <= max_len; out_pos <= max_pos + OFFSET_SEG_N + 1'd1; end end end assign vN_clean = (vN_sync_reg == 3'b000) ? 1'b0 : 1'b1; endmodule Declare in top module counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd0), .MAX_CLK_COUNTER(10'd380)) counter_seg1( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v1), .out_len(out_len_1), .out_pos(out_pos_1) ); counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd216), .MAX_CLK_COUNTER(10'd380)) counter_seg2( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v2), .out_len(out_len_2), .out_pos(out_pos_2) ); counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd287), .OFFSET_SEG_N(10'd432), .MAX_CLK_COUNTER(10'd380)) counter_seg3( .clk(cp), .rst(_rst), .sp(sp), .vN_signal(v3), .out_len(out_len_3), .out_pos(out_pos_3) ); Summary I try change pinout but has same problem above, the third signal always read wrong so i want to know what and why make this problem and also how to fix it? Thanks for all help. Result of signaltap
Video Clock Output to SDI II in Agilex 5
I'm trying to output a video chain using the VVP cores but I can't figure out how to connect the VCO to the SDI II. on Quartus 18.1, the VCO core would output vid_data[19..0], vid_trs, and vid_ln[10..0] which I would then connect straight to the SDI core. But i'm now using Quartus 25.3 PRO, VVP 24.1 manual (24.6 according the version readback registers) and its VCO outputs only a AXI4S_fr bus that doesn't have the same signals to connect straight to the SDI II core. I can't find any examples or documentations on this. The SDI II generate example usings an SDI RX connected to an SDI TX and that doesn't help me. any help on how to connect hte two cores??? thanks - rob
Asynchronous FIFO and discontinuous write clock
Hello, The FPGA is a Cyclone 10LP (10CL016YU256I7G). The FIFO is configured as separate write and read clocks, it is 32 words deep. I have a design where the write clock is discontinuous. I have a difference between simulation and hardware behavior. In fact, all works great in simulation. However, it does not work as expected in hardware. I suppose that simulation model is not accurate with the real hardware. What I observe, when I write the four words (full and empty signals are useless as I have another way of knowing how many words have been written), the first read is always 0 and the fourth read give me the penultimate word. So, question is : can we use this asynchronous FIFO with a discontinuous write clock ? Many thanks in advance for the help. Steve
Agilex 5 input termination differential
Hi, After switching from Quartus 24.3.1 (Build 102) to Quartus 25.1.1 (Build 125), I encountered an issue with signal integrity on my hardware. Differential pairs operating at 400 Mbps (_P/_N) are defined as 1.3 V True Differential Signaling with Input Termination – Differential enabled. This configuration works correctly in Quartus 24.3.1. We verified signal integrity using a specialized oscilloscope with a differential probe. As expected, enabling or disabling termination in the Assignment Editor had a significant impact on the signal shape. However, in Quartus 25.1.1, applying the same configuration does not affect signal integrity. The signal appears as if termination is always disabled, regardless of the ON/OFF setting for Input Termination – Differential. Is there a change in how differential I/Os with termination should be defined in Quartus 25.1.1? Or is this a potential issue in the new version? All my assignments show OK status, and there are no warnings related to these settings in the design (Ignored Assignments).
Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
Shift Register triggers occassionally on both clock edges
Good morning community, in my project a MAX10 M08 FPGA serves as an interface between a microcontroller and an ADC board with 32 channels. In order to parallelize the serial data from the board I developed a shift register. This register shall only read the first 512 bits of a data stream. Therefore a counter is included. -- serial-parallel converter synchronous to falling edge of DCLK p_ser_par_dclk : process (DCLK,nRES) is begin if (nRES = '0') then dout0_shr_dclk <= (others => '0'); dout1_shr_dclk <= (others => '0'); mod1023_count_i <= 0; elsif (falling_edge(DCLK)) then -- resets counter when nDRDY active if (nDRDY = '1') then mod1023_count_i <= 0; elsif (mod1023_count_i < 512) then mod1023_count_i <= mod1023_count_i + 1; end if; -- counter masks the 512 DCLK clock edges without data if (mod1023_count_i < 512) then -- shift-registers, alert bit, address bits, CRC bits shifted, maybe later omitted dout0_shr_dclk(0) <= DOUT0; dout1_shr_dclk(0) <= DOUT1; dout0_shr_dclk((snr_length - 1) downto 1) <= dout0_shr_dclk((snr_length - 2) downto 0); dout1_shr_dclk((snr_length - 1) downto 1) <= dout1_shr_dclk((snr_length - 2) downto 0); -- no shifting else dout1_shr_dclk <= dout1_shr_dclk; dout0_shr_dclk <= dout0_shr_dclk; end if; end if; end process p_ser_par_dclk; The data from the AD converters contains the channel number. Therefore there must be regular data patterns in the 512 bit wide vector when a complete set of 16*32bit have been written into the FIFO. I could never see this pattern when I visualized the internal data with the signal tap analyzer. What I can occassionally see is that the shift registers and the counter triggers at the wrong edge. This is a severe error. What could be the reason? Best regards Christof AbtDAC Interface Instability After Migrating from MAX7000 to MAX10
Hi all, In one of our legacy designs, we used the MAX7000 (EPM7128AETC100-10N) CPLD. Due to obsolescence, we updated the design to use the MAX10 (10M04SCE144C8G). After the migration, we are observing instability in the DAC interface during operation. Has anyone encountered similar behavior when moving from MAX7000 to MAX10? Are there any known circuit-level differences, I/O characteristics, or design considerations we should account for to ensure stable DAC communication? If we made some correction on RC filter its working, reason is root cause is needed for implementation. Any guidance or insights would be greatly appreciated. Thanks Niranjan. D
