core logic

69 Topics

AXI violation on H2F interface of S10
I'm using the H2F AXI interface to access external RAM via EMIF on an S10 SX SoC DK (1SX280HU2F50E1VGAS). There are situations where I see the valid signal of the W channel go from 1 to 0 while the ready signal is 0. This is a violation of the valid/ready handshake protocol of AXI. After a while the system freezes because no more write transaction are accepted on the AW channel. What can cause this? Are there any known bugs in the bus master of the HPS? Here is a waveform I sampled with SignalTap that shows the behavior: There is a Linux 6.1 running on the ARM core. The RAM on the FPGA side is used for video memory. It is listed in the device tree and our drivers use it to make video memory allocations. The memory is then mapped into user space and our test application transfers data into the memory (e.g. texture data).
c-thaler
8 hours ago Place FPGA Device
40Views
1like
2Comments
Cyclone V nRST assertion upon nPOR
Hello, I am looking for a confirmation on whether the nRST pin is driven low upon a nPOR input assertion. I have found no definite answer in the HPS TRM (cv_5v4 dated 2024.12.03). But HPS TRM version 1.3 (Nov 2012), Table 3-3 page 3-7 says with I ran an experiment today on our prototype, asserting nPOR once the system has boot-up (linux) and see no assertion of nRST pin. Also, in the Reset Manager register description, I see no configuration bit that would enable/disable nRST assertion upon nPOR. Can someone confirm the unconditional assertion of nRST upon a nPOR as I understand from HPS TRM from Nov 2012. Thanks, Best regard Pascal
PRega1
9 hours ago Place FPGA Device
32Views
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2Comments
Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
BrianSune_Froum
1 day ago Place FPGA Device
580Views
0likes
50Comments
Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
Roshan
1 day ago Place FPGA Device
21Views
0likes
2Comments
Memory Support with A5ED065BB32AI4S Agilex5 FPGA
Hi, I am using the A5ED065BB32AI4S FPGA, Want to connect the DDR4 X32+ECC with the 2A,2B,3A,3B. We have 512M X16 memory want to interface 4GB with the PS and 4GB with the PL how i can ? Thanks Jay
jaykrishna1
1 day ago Place FPGA Device
197Views
0likes
5Comments
Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.
Sameer-sahu
2 days ago Place FPGA Device
126Views
0likes
11Comments
Dedicated Clock Pins for MAX 10
Hello Intel Community, I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resources and the presence of only a single hardware PLL (PLL1) on this device, I need to ensure that my clock network architecture conforms strictly to the hardware requirements to achieve optimal jitter performance and complete phase compensation. My Application Topology: Clock Input: An external reference clock enters the FPGA and drives the inclk0 port of the instantiated ALTPLL IP core. Phase Shift: Inside the ALTPLL, the clock waveform is inverted by 180 degrees. Clock Distribution: This 180-degree phase-shifted clock is split into two destinations: Internal: It drives an internal single-clock FIFO (scfifo) within the FPGA fabric. External: It is routed out through a physical I/O pin to drive an external MCU. My Questions for Intel Support: Dedicated Input Pins: For the M153 package of the 10M02 device, which physical pin numbers are the true Dedicated Clock Input Pins that are directly hardwired to the internal PLL1's inclk0 port, enabling full hardware-level phase compensation (Normal Mode) without introducing routing delays or Quartus compilation warnings? Dedicated Output Pins: To output the 180-degree inverted clock to the external MCU, does this device feature any Dedicated Clock Output Pins (such as PLL external clock outputs) that are physically bonded out in the M153 package? Or are we required to route this clock out via regular user I/O pins through the global clock network? ALTPLL Operation Mode Advice: Considering that this clock simultaneously drives an internal FIFO and an external MCU, which compensation mode (Normal Mode vs. Zero-Delay Buffer Mode) does Intel recommend for the ALTPLL IP core to minimize clock skew and ensure optimal timing closure? Are there any specific parameters (e.g., compensate_clock) that must be explicitly configured to align with the chosen dedicated pins? Any official documentation snippets, device handbook references, or design guidelines regarding the clock routing constraints for this specific micro-package would be highly appreciated. Thank you in advance for your technical assistance! Best regards, Martin.
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MartinMaa
2 days ago Place FPGA Device
221Views
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12Comments
Global Clock & Regional clock inputs in Agilex M FPGA
Hi, Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ? Why multiple clock inputs of Global clocks and Regional clocks are provided in F-Tile of Agilex M FPGA? Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? When do we need to drive regional clock inputs ? When do I need to drive global clock inputs ? In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ? Regards, Thulasi
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Thulasi
3 days ago Place FPGA Device
57Views
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6Comments
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
SiddeshChavan
4 days ago Place FPGA Device
18Views
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0Comments
Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chips
Hello Guys, I read one post here, which requested the way to design carry chain style TDC based on Agilex 9 chips. Here is that post linkcarry chain tdc | Altera Community - 351924 Kenney answer that post and give some recommendations about it. Now I have similar questions about carry chain TDC by using ALTERA's Cyclone 10 GX. Is that wire LUT delay lines in Cyclone 10 Gx devices?
MinzhiWang
10 days ago Place FPGA Device
107Views
0likes
6Comments