MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application
Hello, I’m using Intel MAX10 Remote System Upgrade (RSU) with: CFM0 = Factory CFM1 = Application The firmware‑triggered RSU upgrade completes successfully, but after reconfiguration the device boots back into the Factory image instead of the Application image. Below is the design setup: RSU IP instantiated and connected over SPI Avalon‑MM master interface of RSU IP is exported to user logic onchip_flash data interface is also exported and visible in the top level Firmware performs erase/write/verify through the exported Avalon‑MM interface Autoboot decision is based on a bit stored in UFM, read at startup No external power cycle occurs during RSU (warm reconfiguration). Below are the observations: RSU programming via firmware completes without errors MAX10 reconfigures after RSU Cold boot works correctly Programming the App image via JTAG works Issue occurs only after warm RSU (no power cycle) Autoboot selection is controlled via a bit stored in UFM. For this I have exported the AV-MM I have the below questions: Is it expected that RSU does not automatically re‑enter autoboot logic? After warm RSU, must user RTL explicitly regenerate a boot / autoboot event? Are there recommended MAX10 reference patterns for autoboot handling after RSU? Thanks for any guidance or references.
About ALTIOBUF simulation
I'm trying to use the IP ALTIOBUF for input delay, but simulating failed, and the error message is: Bad default binding for component instance "ioconfiga : cyclonev_io_config".# (Component port "padtoinputregisterfinedelaysetting" is not on the entity.). I'm sure I've added all the necessary libraries(altera_mf, primitives....), and the device in use is cycloneV, my quartus version is 17.1, so is there anybody who have used this IP? In addition, who can give the timing diagram for this IP? thanks
HDMI example design errors with Agilex 7
Hello, I generated the HDMI example design for the Agilex 7 devkit and it compiled and worked fine. But when I ported it to my platform and remapped it to the nwe pins, I get these errors (for evenry RX lane and every TX lane): Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx ... Can you please clarify what the issue is? On my new platform, I am using Bank 12A Quad 3 (TX and RX) and for reference clocks fgt_12a_refclk_ch3 and fgt_12a_refclk_ch4. Thanks
Timing Slacks inside Altera IP
Hi, I am compiling my design for the device 10AX115N2F40I2SG using: Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition) I am encountering timing violations (negative slack) on the clock a10_internal_oscillator_clock0 across all synthesis seeds. Due to these violations, I am unable to close timing on my design. From my analysis, the failing paths appear to be internal to the Intel (Altera) IP, for example: From: ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|iopll_bootstrap:gen_pll_dprio.inst_iopll_bootstrap|gen_pll_dprio.r_dprio_writedata_in_use~RTM To: |ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~dprio_reg My understanding is that this clock is only active during PLL calibration at device power-up and is not used during normal functional operation. Given this, I would like to confirm whether it is safe and appropriate to constrain these paths as false paths. For example: "set_false_path -from [get_clocks {a10_internal_oscillator_clock0}]" Could you please advise if this approach is valid, or if there is a recommended way to properly constrain these paths? I attached an image of the slacks.
LVDS support on Agilex 7
HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?HDMI example design errors with Agilex 7
Hello, I generated the HDMI example design for the Agilex 7 devkit and it compiled and worked fine. But when I ported it to my platform and remapped it to the nwe pins, I get these errors (for evenry RX lane and every TX lane): Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Error(21843): cdr_f_out_hz == 1745000000 Error(21843): cdr_f_ref_hz == 87250000 Error(21843): is_used == TRUE Error(21843): location == UX12 Error(21843): rx_tuning_hint == RX_TUNING_HINT_DISABLED Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings Error(21843): Conflict 0 ---------------------------------------------------------------- Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_f_min_ref_limit_rule @ gdr.z1577b.u_ux_quad_3.flux_top Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_f_out_hz_rule @ gdr.z1577b.u_ux_quad_3.flux_top Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): Rule: gdrb_wrapper::topology_mapping_mux_rule @ Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): Rule: z1577b::topo_down_to_ux_and_barak_powerdown_rules @ gdr.z1577b Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): Input variables: Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx Error(21843): cdr_f_out_hz == 1745000000 Error(21843): cdr_f_ref_hz == 87250000 Error(21843): is_used == TRUE Error(21843): location == UX12 Error(21843): rx_tuning_hint == RX_TUNING_HINT_DISABLED Can you please clarify what the issue is? On my new platform, I am using Bank 12A Quad 3 (TX and RX) and for reference clocks fgt_12a_refclk_ch3 and fgt_12a_refclk_ch4. ThanksTiming Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory
Hi, I am working with a Cyclone-V 5CSXFC6C6U2317 FPGA and using the MegaWizard's IP FIFO SCFIFO in it. The SCFIFO is for custom logic and is outside of the HPS/ARM/Nios sub-system. My Quartus is 23.1 Prime Standard Edition. From the "FIFO IP User Guide for Quartus® Prime Design Suite: 25.1.1" it looks like I can enable (hard, memory-build in) ECC protection only for Arria 10 devices with M20K memory. My Cyclone-V has M10K memory (and Auto and MLAB memory) . It should be possible for me to add a soft-ECC module in the fabric, either inside the SCFIFO wrapper (from MegaWizard), or outside the SCFIFO wrapper. Has anyone done (or seen in Altera's Github) such a soft-ECC module ( for example using a Hamming SEC-DED (24,16) code or similar) ?UVM Questasim simulation
HI , I am trying to simulate a generic ALU in Systemverilog UVM test environment . My add_i is random input signal , but when i open my wave i dont see it toggling , but the display function reports it is being toggled ? here are my files : // alu package file // package alu_pkg; //----Transaction Class---- class transaction; //declaring the transaction items rand bit [3:0] a; rand bit [3:0] b; bit [6:0] c; rand bit add_i; function void display(string name); $display("-------------------------"); $display("- %s ",name); $display("-------------------------"); $display("- a = %0d, b = %0d",a,b); $display("- c = %0d",c); $display("-------------------------"); $display("-- ADD = %b --",add_i); endfunction endclass //---------------------------------------// //-----------Driver Class------------------ class driver; //used to count the number of transactions int no_transactions; //creating virtual interface handle virtual intf_alu#(.WORD_LENGTH(4)) vif; //creating mailbox handle mailbox gen2driv; //constructor function new(virtual intf_alu vif,mailbox gen2driv); //getting the interface this.vif = vif; //getting the mailbox handles from environment this.gen2driv = gen2driv; endfunction //Reset task, Reset the Interface signals to default/initial values task reset; wait(vif.reset); $display("[ DRIVER ] ----- Reset Started -----"); vif.a <= 0; vif.b <= 0; vif.valid <= 0; vif.add_i <= 0; vif.mul_i <= 0; vif.sub_i <= 0; vif.div_i <= 0; vif.and_i <= 0; vif.or_i <= 0; vif.xor_i <= 0; wait(!vif.reset); $display("[ DRIVER ] ----- Reset Ended -----"); endtask //drivers the transaction items to interface signals task main; forever begin transaction trans; gen2driv.get(trans); @(posedge vif.clk); vif.valid <= 1; //vif.add_i <= 1; vif.a <= trans.a; vif.b <= trans.b; @(posedge vif.clk); vif.valid <= 0; //vif.add_i <= 0; trans.c = vif.c; @(posedge vif.clk); trans.display("[ Driver ]"); no_transactions++; end endtask endclass //---------------------------------------// //----Generator Class------------------ class generator; //declaring transaction class rand transaction trans; //repeat count, to specify number of items to generate int repeat_count; //mailbox, to generate and send the packet to driver mailbox gen2driv; //event, to indicate the end of transaction generation event ended; //constructor function new(mailbox gen2driv); //getting the mailbox handle from env, in order to share the transaction packet between the generator and driver, the same mailbox is shared between both. this.gen2driv = gen2driv; endfunction //main task, generates(create and randomizes) the repeat_count number of transaction packets and puts into mailbox task main(); repeat(repeat_count) begin trans = new(); if( !trans.randomize() ) $fatal("Gen:: trans randomization failed"); trans.display("[ Generator ]"); gen2driv.put(trans); end -> ended; //triggering indicatesthe end of generation endtask endclass //---------------------------------------// //----Environment Class------------------ class environment; //generator and driver instance generator gen; driver driv; //mailbox handle's mailbox gen2driv; //virtual interface virtual intf_alu#(.WORD_LENGTH(4)) vif; //constructor function new(virtual intf_alu vif); //get the interface from test this.vif = vif; //creating the mailbox (Same handle will be shared across generator and driver) gen2driv = new(); //creating generator and driver gen = new(gen2driv); driv = new(vif,gen2driv); endfunction // task pre_test(); driv.reset(); endtask task test(); fork gen.main(); driv.main(); join_any endtask task post_test(); wait(gen.ended.triggered); wait(gen.repeat_count == driv.no_transactions); endtask //run task task run; pre_test(); test(); post_test(); $finish; endtask endclass //---------------------------------------// endpackage
