Global Clock & Regional clock inputs in Agilex M FPGA

Hi,

Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA.

1. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ?
2. Why multiple clock inputs of Global clocks and Regional clocks are  provided in F-Tile of Agilex M FPGA?
3. Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? 
4. When do we need to drive regional clock inputs ?
5. When do I need to drive global clock inputs ?
6. In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ?

Regards,

Thulasi