Forum Discussion
Occasional ContributorAgilex 3 PLL in Source Synchronous mode ?
Surprisingly, the compilation fails when we try to set a PLL in source synchronous mode in an Agilex 3, while this works as expected in Agilex 5. Compiles in "direct" mode. The pin assignment comes from the Atum A3-nano but we tried various dedicated clock inputs to no avail.
The error messages are a bit puzzling too (I think there are 11 PLLs in the A3CZ135BB18AE7S ) :
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL IP pll_altera_iopll_2110_hws7ggy.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): u_pll|iopll_0|tennm_ph2_iopll
Error (16234): No legal location could be found out of 5 considered location(s). Reasons why each location could not be used are summarized below:
Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to "u_pll|iopll_0|tennm_ph2_iopll". Promote refclk to a global clock or use a dedicated IOPLL refclk pin. (4 locations affected)
Info (175029): IOPLL_X106_Y53_N346
Info (175029): IOPLL_X121_Y31_N846
Info (175029): IOPLL_X106_Y2_N346
Info (175029): IOPLL_X1_Y3_N346
Error (175006): There is no routing connectivity between the IOPLL and the IOPLL
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): IOPLL_X121_Y6_N846
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 8 errors, 11 warnings
--------------------------------------------
This is very annoying for source synchronous interfaces (like RGMII).
Test case available indeed.
14 Replies
BCuzeCan you answer the question please ? If the pin assignment cannot work, it means the Terasic Atum A3 kit GB Ethernet port cannot be used...
AqidAyman_AlteraRegular Contributor
Hi BCuze,
Thank you for the follow-up, and sorry for the delay.
With the RGMII RxClock fixed on AT9, Quartus is reporting:
Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to <IOPLL>. Promote refclk to a global clock or use a dedicated IOPLL refclk pin.
That means AT9 is entering the clock network as a cluster clock resource, and there is no legal dedicated refclk route from that pin to an IOPLL location that can satisfy your placement. This is a device pin / clock-connectivity constraint, not a tool misconfiguration that can be overridden while keeping AT9 and source-synchronous compensation.
So, the specific assignment “AT9 drives an IOPLL in Source Synchronous compensation mode” is not workable on this pinout, which matches what we see when Quartus is allowed to pick a different clock pin (placement succeeds) versus when AT9 is forced (placement fails). Pin AT9 located in Bank 6E, which is an HVIO bank. The Agilex 3 Clocking and PLL User Guide (847921) states that the fabric-feeding PLL in HVIO banks 6E, 6F/6G, and 6H does not support compensation mode. Source synchronous is a compensation mode. That is why the Agilex 5 kit scheme does not port to this Atum A3 pinout.
It means this source-synchronous IOPLL from AT9 pin cannot be closed the way it was on the previous Agilex 5 kit. It does not by itself prove that Ethernet on the board is impossible under every architecture.
Can you share the board schematic? I will try to check if there are any other possible ways to solve this. Also, can you confirm you are using the kit below?
https://www.digikey.my/en/products/detail/terasic-inc/P0803/26766123
Regards,
Aqid- BCuze
Hi Aqid,
Yes, I confirm again that the Atum A3 nano is the Terasic board we're trying to use.
Terasic didn't want to share the complete schematics, even if we are a distributor, but we got some pages and the details about the PHY details including the bootstrap settings (RX[2:0]=100, TX[2:0]=100).
The pinout is what we used and it fails. Having access to the PHY MDIO doesn't help..
The PHY is using HVIOs : not smart...As I explained, we found no way to close the RGMII timings on the Intel Agilex 5 kit other than using the PLL in Source Synchronous mode.
Hence the conclusion that the Atum A3 nano FPGA Eth PHY cannot be used (reliably or at all). It's a board design mistake (anyway, IMO, choosing RGMII is a poor choice since Cyclone V).
The only FPGA feature that could be demonstrated on the Atum A3 board seems to be the MIPI link (tbv).
- BCuze
The test case QAR was attached to my original message (June 3rd 2026). 254 kB
I attach it again
- AqidAyman_Altera
Hi Bert,
Please check your inbox.
I have reach out to you r4egarding this.
Regards,
Aqid
- BCuze
Hi,
Letting Quartus select a suitable clock input pin does remove the error, sure...
But the problem is that we need actually to drive a PLL in Source synchronous mode by pin AT9 (1.8V LVCMOS).* This is not an option ! It is the Terasic Atum A3 nano board, and this scheme is the only way to reach timing convergence on the RGMII PHY (RxClock / RxData).
This scheme works on the Intel Agilex 5 kit.We cannot ask Terasic to redo the board layout.
What do you suggest ?* : note that the exact pin we need is AT9. We had to ask to get some schematics of the GBEth section.
The error message is :
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL IP pll_altera_iopll_2110_hws7ggy.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): u_pll|iopll_0|tennm_ph2_iopll
Error (16234): No legal location could be found out of 5 considered location(s). Reasons why each location could not be used are summarized below:
Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to "u_pll|iopll_0|tennm_ph2_iopll". Promote refclk to a global clock or use a dedicated IOPLL refclk pin. (4 locations affected)
Info (175029): IOPLL_X106_Y53_N346
Info (175029): IOPLL_X121_Y31_N846
Info (175029): IOPLL_X106_Y2_N346
Info (175029): IOPLL_X1_Y3_N346
Error (175006): There is no routing connectivity between the IOPLL and the IOPLL
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): IOPLL_X121_Y6_N846
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
- AqidAyman_Altera
Hi,
I am able to get the design compiled successfully by letting Quartus selecting the clock input pin. You need to remove the I/O standard assigned first. Unfortunately, the compilation is failed if I assigned to the specific pin you mentioned (AT9).
Unless, if you promote it as a global clock, then the compilation is passed.
Below settings in .qsf in your project file:
set_location_assignment PIN_AT9 -to CLOCK0_50 -comment IOBANK_6E
set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to CLOCK0_50 -entity pll_bug
set_instance_assignment -name GLOBAL_SIGNAL ON -to CLOCK0_50Regards,
Aqid
- BCuze
Hi Aqid,
Did you test with the provided testcase ? Did you find an explanation ?
Thx in advance,
Bert
- AqidAyman_Altera
Hi Bert,
I did not see the test case you provided in this ticket. Is it possible for you to share it with me through private message?
I have initiated a message to you.
Regards,
Aqid- BCuze
I used the "Attachment" button in the message editor and selected the file. (tried again on this answer).
And I didn't receive a message with the email address to use.
I dropped the QAR here too :
https://www.swisstransfer.com/d/447a9b69-3ca3-4ec6-8d5c-1a0562d2b834
BR
Bert
- AqidAyman_Altera
Hello,
Thank you for reaching out to us.
This looks to me either a pin resources issue or hardware limitation issue. Can you share with me the use case design where I can replicate the error from my side? I need to check it first. Preferably in .QAR file.
If you need to share it privately, let me know.
Regards,
Aqid
- BCuze
Hi,
Should be attached
