Agilex 3 PLL in Source Synchronous mode ?

Surprisingly, the compilation fails when we try to set a PLL in source synchronous mode in an Agilex 3, while this works as expected in Agilex 5. Compiles in "direct" mode. The pin assignment comes from the Atum A3-nano but we tried various dedicated clock inputs to no avail.
The error messages are a bit puzzling too (I think there are 11 PLLs in the A3CZ135BB18AE7S ) :

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.

Error (175001): The Fitter cannot place 1 IOPLL, which is within IOPLL IP pll_altera_iopll_2110_hws7ggy.

Info (14596): Information about the failing component(s):

Info (175028): The IOPLL name(s): u_pll|iopll_0|tennm_ph2_iopll

Error (16234): No legal location could be found out of 5 considered location(s). Reasons why each location could not be used are summarized below:

Error (23527): No route for refclk connection from "CLOCK0_50~CLUSTER" to "u_pll|iopll_0|tennm_ph2_iopll". Promote refclk to a global clock or use a dedicated IOPLL refclk pin. (4 locations affected)

Info (175029): IOPLL_X106_Y53_N346

Info (175029): IOPLL_X121_Y31_N846

Info (175029): IOPLL_X106_Y2_N346

Info (175029): IOPLL_X1_Y3_N346

Error (175006): There is no routing connectivity between the IOPLL and the IOPLL

Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements

Info (175029): 1 location affected

Info (175029): IOPLL_X121_Y6_N846

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

Error (16297): An error has occurred while trying to initialize the plan stage.

Error: Quartus Prime Fitter was unsuccessful. 8 errors, 11 warnings

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This is very annoying for source synchronous interfaces (like RGMII).

Test case available indeed.