Dedicated Clock Pins for MAX 10

Hello Intel Community,

I am currently designing a system using the Intel MAX 10 FPGA, specifically the 10M02SCM153C8G in the compact M153 micro-package. Due to the highly constrained pin resources and the presence of only a single hardware PLL (PLL1) on this device, I need to ensure that my clock network architecture conforms strictly to the hardware requirements to achieve optimal jitter performance and complete phase compensation.

My Application Topology:

Clock Input: An external reference clock enters the FPGA and drives the inclk0 port of the instantiated ALTPLL IP core.

Phase Shift: Inside the ALTPLL, the clock waveform is inverted by 180 degrees.

Clock Distribution: This 180-degree phase-shifted clock is split into two destinations:

Internal: It drives an internal single-clock FIFO (scfifo) within the FPGA fabric.

External: It is routed out through a physical I/O pin to drive an external MCU.

My Questions for Intel Support:

Dedicated Input Pins: For the M153 package of the 10M02 device, which physical pin numbers are the true Dedicated Clock Input Pins that are directly hardwired to the internal PLL1's inclk0 port, enabling full hardware-level phase compensation (Normal Mode) without introducing routing delays or Quartus compilation warnings?

Dedicated Output Pins: To output the 180-degree inverted clock to the external MCU, does this device feature any Dedicated Clock Output Pins (such as PLL external clock outputs) that are physically bonded out in the M153 package? Or are we required to route this clock out via regular user I/O pins through the global clock network?

ALTPLL Operation Mode Advice: Considering that this clock simultaneously drives an internal FIFO and an external MCU, which compensation mode (Normal Mode vs. Zero-Delay Buffer Mode) does Intel recommend for the ALTPLL IP core to minimize clock skew and ensure optimal timing closure? Are there any specific parameters (e.g., compensate_clock) that must be explicitly configured to align with the chosen dedicated pins?

Any official documentation snippets, device handbook references, or design guidelines regarding the clock routing constraints for this specific micro-package would be highly appreciated.

Thank you in advance for your technical assistance!

Best regards,

Martin.