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KJ's avatar
KJ
Icon for New Contributor rankNew Contributor
1 month ago

Power and thermal characterization of Agilex 5

We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you be able to help?

1) Typical static power model:

I'd like to evaluate a typical static power consumption, but the latest Quartus tool (26.1.0, build 110) only provides max characteristics.

Q1: When does Altera plan to release the typical model?

Q2: In the meantime, would it be possible to get access to a pre-release model or estimates of how leakage power differs between the typical and max process corners?

2) Power and thermal analyzer breakdown for an empty design:

For an almost empty design (only a single FF driven by an external clock), the report shows several power components I'd like to understand better:

  1. a) the design uses no DSP or RAM blocks but both static and dynamic power are reported for them.

Q3: Which fabric components draw power even when unused?

  1. b) The I/O contributes significantly. 

Q4: Is this only the clock buffer and the SDM/Active Serial config-related buffers that Quartus inserts automatically or are there additional assumptions behind it?

  1. c) The "Miscellaneous" also contributes significantly to the total power consumption.

Q5: Could you clarify what this category includes?

3) Powering down unused blocks:

Q6: Can the HPS and transceivers be fully powered down, i.e., voltage rails disconnected to save power?

For reference, I'm on Ubuntu 26.04 with Quartus 26.1.0 (build 110). I've attached the Quartus project for the "empty" design with its power analysis report.

I appreciate your help and I look forward to hearing from you.

Chris

Power

4 Replies

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hello Chris, 

     

    1- Typical static power model

    i- When the typical static power model will be available? 

    Ans: Please refer here Table 23

     

    ii- access to pre-release model 

    Ans: All the E-series power model is updated in 26.1

     

    2- Power and Thermal Analyzer on empty design

    i(a)- design use no DSP or RAM blocks

    Ans: This is expected. Even no DSP or M20K blocks instantiated, the silicon physically contributes leakage/static power. 

     

    i(b)- Which fabric component draw power significantly

    Ans: clock input buffer, Global clock, configuration related circuitry, SDM, default termination, unused IO bank static leakage etc.IO is only one part of the contributors.

     

    i(c) - what is included in miscellaneous category?

    Ans:  SDM related circuit, Configuration circuit, Device management logic, power-monitoring circuit(POR), temperature/voltage sensing circuit, etc.

     

    3- Can HPS and transceivers by fully powered down by disconnecting the power rails?

    Ans: Basically yes, but why? you can choose device variance without HPS and without transceiver if you dont want this feature. This variance comes without HPS and transceivers. 

     

    regards,
    Farabi

     

     

     

    • KJ's avatar
      KJ
      Icon for New Contributor rankNew Contributor
      1 month ago

      Hi Farabi,

      Thank you for your answers. They are very useful.

      With regards to power consumption of uninstantiated DSP and M20K blocks, the report shows they also contribute to dynamic power consumption, as opposed to just leakage power. Could you clarify why?

      With regards to powering down HPS/transceivers, choosing the part that doesn't have those in the first place would be ideal, but not all fabric sizes for Agilex 5 E come with that configuration option, unfortunately. 

      Regards,

      Chris

      • Farabi_Altera's avatar
        Farabi_Altera
        Icon for Regular Contributor rankRegular Contributor
        1 month ago

        Hello Chris, 

         

        1- Power analyzer partitions device power into categories. Some infrastructure power may be allocated to DSP or RAM category even though no DSP arithmetic or memory read/write activity is occurring. 

        2- Even individual blocks are power-gated, the surrounding clocking and infrastructure networks still exist on the die. The analyzer may distribute a portion of this activity into DSP/RAM categories. 

        3- Power Analyzer includes small baseline dynamic values to account for device-level activity that cannot be cleanly assigned elsewhere. In nearly empty design, these baseline values can appear in the calcualtion. 

         

        regards,
        Farabi