Power and thermal characterization of Agilex 5

We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you be able to help?

1) Typical static power model:

I'd like to evaluate a typical static power consumption, but the latest Quartus tool (26.1.0, build 110) only provides max characteristics.

Q1: When does Altera plan to release the typical model?

Q2: In the meantime, would it be possible to get access to a pre-release model or estimates of how leakage power differs between the typical and max process corners?

2) Power and thermal analyzer breakdown for an empty design:

For an almost empty design (only a single FF driven by an external clock), the report shows several power components I'd like to understand better:

1. a) the design uses no DSP or RAM blocks but both static and dynamic power are reported for them.

Q3: Which fabric components draw power even when unused?

1. b) The I/O contributes significantly. 

Q4: Is this only the clock buffer and the SDM/Active Serial config-related buffers that Quartus inserts automatically or are there additional assumptions behind it?

1. c) The "Miscellaneous" also contributes significantly to the total power consumption.

Q5: Could you clarify what this category includes?

3) Powering down unused blocks:

Q6: Can the HPS and transceivers be fully powered down, i.e., voltage rails disconnected to save power?

For reference, I'm on Ubuntu 26.04 with Quartus 26.1.0 (build 110). I've attached the Quartus project for the "empty" design with its power analysis report.

I appreciate your help and I look forward to hearing from you.

Chris