Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
Agilex 7 Decoupling capacitor scaling factor
Hi! I have got my power estimate from quartus prime based on our requirement, which is " board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , where would i get this value? is it related to FPGA part(AGFB027R24C2I2V) or the max current rating of my convertors? Thanks, Vigneswaran
Error with PDN Tool 2.0 for Cyclone V
Hello, I'm trying to use the PDN Tool 2.0, version 16, build 04.27, for Cyclone V. After starting the tool, I keep getting the following error message: Runtime error 53 File not found: 28nm_pdn_16.0_hid_04_27_32bit.dll I'm using Excel 2016. Does anyone have any idea how I can fix this problem? Thank you in advance. Matthias
Agilex 5 Power
Hello, I am using two A5EC043BB32AI4S devices and I am now planning their power rails. I have two questions. Is it possible to design one power supply (one regulator) per rail for both FPGASs There is a requirement in the PCB Design Guideline User Guide for ‘Recommended VR Accuracy (% of Vnom)’ of ±0.5%. What is the meaning of this requirement? As I understand it, this refers to the Voltage accuracy (excluding line regulation and load regulation). This is a very strict requirement, and most power regulators cannot meet it. What is the practical meaning or impact of not meeting this requirement? In the datasheet, however, only a maximum value is specified, and it is usually around 3%. P.S:the requirement of the ±0.5%.are in table 24 in PCB Design Guidelines (HSSI, EMIF,MIPI, True Differential, PDN) User Guide
AGMF039R47A1E2V Compact Thermal Model
Hello, I need assistance finding the AGMF039R47A1E2V compact thermal model. I navigated to this page: https://www.altera.com/design/devices/resources/package-thermal but when I clicked on the Agilex 7 compact thermal model link it takes me to a page that says there's 0 results. Thank you for your help!Cyclone 10 LP's Extended Industrial parts
[Question] Customer have questions about Cyclone 10 LP's Extended Industrial (Tj = -40degC to 125degC) in the Product Catalog at the following URL. https://www.intel.com/content/www/us/en/content-details/730595/altera-product-catalog.html What is part number of Extended Industrial of "10 CL010YM164I7 G" as part number of Normal Industrial? What should the customer do if they want to check the power consumption by EPE(Early Power Estimator)? How can the customer design with Extended Industrial part if they want to compile with Quartus? Best Regards
Cyclone IV E – PLL Power Track Width Recommendation Clarification
Hi, I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil trace width for the PLL power supply routing. Due to space constraints on our PCB, we have routed the PLL supply net as follows: From the ferrite bead to the FPGA cutout: 20 mil trace width After the cutout region leading into the FPGA power pin area: reduced to 6 mil trace width My questions are: Is it acceptable to reduce the PLL power trace width from 20 mil to 6 mil after the cutout region? If not, what issues might arise due to this narrower trace? I have attached a snapshot from the guideline for reference. Requesting your comments and guidance on whether this implementation is safe or if the narrower section could cause problems with PLL performance. Thanks in advance!
Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks!
