Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)
Hello everyone, While reviewing the schematics for a Terasic DE10 board, I noticed a specific circuit block on the power rails. See attached image From my understanding of the schematic, when a specific Enable (EN) signal drops or is disabled, this circuit actively shorts the power rails to ground. My question is regarding the fundamental design here: If the power to the board drops, or the EN signal to the voltage regulators is pulled low, the voltage to the FPGA will naturally stop being supplied anyway. Why is there a need to spend BOM cost and board space on actively shorting the rails to ground? I would love a more in-depth explanation from a board-level design perspective. What exact failure modes or risks does this active discharge circuit prevent in FPGAs? Is this considered a mandatory best practice for all Agilex/Stratix/Cyclone designs, or is it only necessary under specific power supply topologies? Thank you for the insights!
Power and thermal characterization of Agilex 5
We are working on the power characterization of a design based on the Agilex5 E-series and I've come across a few questions I haven't been able to fully resolve from Altera's documentation. Would you be able to help? 1) Typical static power model: I'd like to evaluate a typical static power consumption, but the latest Quartus tool (26.1.0, build 110) only provides max characteristics. Q1: When does Altera plan to release the typical model? Q2: In the meantime, would it be possible to get access to a pre-release model or estimates of how leakage power differs between the typical and max process corners? 2) Power and thermal analyzer breakdown for an empty design: For an almost empty design (only a single FF driven by an external clock), the report shows several power components I'd like to understand better: a) the design uses no DSP or RAM blocks but both static and dynamic power are reported for them. Q3: Which fabric components draw power even when unused? b) The I/O contributes significantly. Q4: Is this only the clock buffer and the SDM/Active Serial config-related buffers that Quartus inserts automatically or are there additional assumptions behind it? c) The "Miscellaneous" also contributes significantly to the total power consumption. Q5: Could you clarify what this category includes? 3) Powering down unused blocks: Q6: Can the HPS and transceivers be fully powered down, i.e., voltage rails disconnected to save power? For reference, I'm on Ubuntu 26.04 with Quartus 26.1.0 (build 110). I've attached the Quartus project for the "empty" design with its power analysis report. I appreciate your help and I look forward to hearing from you. ChriseFUSE : Agilex F series and AGilex I series PCIe card
Hi, While going through the schematics design of Agilex F series(1xE tile, 1X P tile) pcie card, I observed that in the there is a efuse "TPS259824" each for the 12v input from PCIe slot and 12V input from AUX connector where as in Agilex I series (2x R tiles, 1x F tile) pcie card it is removed from the schematics. EFuse protects the board from over current and inrush current, short circuit and overload, why is it removed from the Agilex I series Pcie card. PS: Please check the shared screen shots from schematics
Error : Arria 10 emif_reset_ interrupt acknowledge
Hi All, I am currently working with an Arria 10 FPGA on a custom board and have encountered an issue where the PCB restarts after the following error message appears: "Error: Arria 10 EMIF reset interrupt acknowledge" I have verified all supply voltages and clock signals, and they are within the expected ranges. Initially suspecting a DDR-related issue, I replaced the DDR component; however, the problem persists. Additionally, all status pins appear to be functioning as expected. I would appreciate any guidance or suggestions on how to further debug this issue. Thank you in advance for your support.
About floating voltage of the Agilex 3 power on reset
Hello, I am Naken, thank you for your support. I have created a board equipped with Agilex 3 and started debugging it recently. When checking the power pins during power-up, it appears that a floating voltage from the VCC system (0.75V) is entering the power system that supplies HVIO (3.3V). (I can send images individually if needed.) As described in the documentation, it mentions that due to floating voltage, VCCIO_PIO can be affected by VCCPT. 3.3. Floating Voltage • Power Management User Guide Agilex™ 3 FPGAs and SoCs • Altera Documentation and Resources Center Is it possible that the HVIO group experiences floating voltage due to the influence of the VCC system group? Best regards, NakenMaxV - Current Value
My customer is using MAX V CPLD. Part numbers are 5M1270ZF256C4N, 5M1270ZF324C5N. They have to interface 5V address and data lines of flash memory to these CPLDs. I studied datasheet, it is saying that we can interface 5V signal to Bank-3 IO pins if we use series resister plus internal I/O clamp diodes being enabled. I could not find acceptable current limit for clamp diode from datasheet. So that I can calculate resister value. Can you please provide max and nominal current limit value for internal IO clamp diode which can pass safely through it? Regards amolkumarQuartus and power domain
We actually one remaining pending issue with the Agilex chip that we can't get resolved and might need some help. The basic description is that when comparing the power consumption of the Agilex 5 on our module, to the Agilex 5 on the dev kit, at same temperature, before any configuration, our Agilex 5 consumes about 0.5-1W more. Besides this, all sub-systems seem to operate correctly (CPU, memory, FPGA, I/Os). This additional power consumption is worrying though, and we would like to understand it before spinning the next revision. Regarding the excess power on our board, it might also be a design issue, but we didn't find any hint yet despite multiple deep reviews and investigations. We already spent several weeks looking at this in every way we could think about, so there is already quite a bit of things we tried out, such as: - Measured the power rails, from the outside and from the inside as well, checking if there is any unexpected difference - Measured temperature from the outside (thermal camera) as well as from the multiple internal sensors - Reviewed power sequence, playing with various combinations to see if it made any difference - Reviewed multiple times schematics against documentation and dev kits The extra power is on the core rail. Now please look at the attachement: We collected side observations on an non-configured FPGA. Our board has a temperature-dependent power consumption. So we simply switched the fan off for a short period and then switched it back on. The main power consumption is on the 0.8 V rail (U500 RAA210130). A second interesting observation is the internal temperature of the Agilex: L0_0 is significantly hotter than the other three. When the fan is switched back on, the power consumption returns to its initial value. Very strange and unusual behavior. Could this somehow help set priorities and allow us to rank the most/least likely directions for investigating the source of the elevated power consumption?