Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered

Hello, 

I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. 

The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it.

Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. 

The A692 Power Sequencing Considerations app note states the below: 

So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. 

The Agilex 7 General-Purpose I/O User Guide states the following: 

• Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower
• Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS.
• Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. 

I don't see any mention of similar constraint for Transceiver I/O. 

The Agilex 7 Power Management User Guide states the following: 

Again, I see all I/O other than Transceiver I/O mentioned. 

Thanks!