IO speed limit while implementing high resolution PWM on Cyclone 10
I would like to implement high resolution PWM on a Cyclone 10 LP. One simple approach I have is running the IO at double data rate for a high possible switching frequency. However as the single ended IOs (3.3V LVTTL for example) cannot switch that fast, when I compiled the design I got a [limit due to minimum port rate restriction (tmin)] with original Fmax=425MHz restricted to 223MHz. But for my application I know I can control the minimum pulse width in software. So my question is where does the IO speed limit actually apply? Does it apply in the IO buffer or does it apply in the double data rate register? In the former case that should not create a problem because I am not switching every cycle, I only want to tune the pulse width with fine steps. In the later case it would. I want to ask this for both input and output, as I might want to measure the realized switching pattern as well. I am aware that another possible way is to add a delay to the IO. However correct me if I am wrong, I don't see how I can dynamically choose the IO delay in any of the IP / primitives. You can dynamically change the phase of the PLL I guess, but I am not sure how fast does it stabilize at the new phase. Also If I use multiple output in my design then I would need a dedicated clock output for each output.
LVDS SERDES rx_inclock idle
Hi, We are using LVDS SERDES IP as a multichannel LVDS receiver in Cyclone 10 GX device. The reciver is configured to run at DDR mode using 200MHz rx_inclock. The transmitter device output clock is not a free-running clock and is subjected to changes with correlation to the output data (for example clock is only running when the transmitter outputs data). I see in the Altera LVDS SERDES IP Core User Guide that the SERDES use IO PLL for that clock, meaning it should meet IO PLL cycle-to cycle clock jitter for the PLL input. Does that means that only a free running clock at a constant frequency and duty cycle can be used as part of the LVDS bus? How should i treat devices that has an LVDS bus clock that is correlated with data?
JTAG Test SW Issue (JTAG TopProbe)
Hi, I used JTAG TopProbe als Boundary Scan SW to change / read level at FPGA pins in the past successfully with Cyclone II designs. Unfortunately I ran into issues with newer designs using Cyclone IV, Cyclone 10 or MAX10 devices. With these devices I cannot set any output levels, the SW just supports reading external applied high or low signals. I know the SW is quite old, does not "do" much more than setting and watching pins and is also no longer develope actively. Thus, I'd also be happy with any suggestion for newer ("cheap") SW to use for this simple connectivity checks I'd planned to do. (I meanwhile tried to use JTAGLive (JTAG Buzz, freeware), which failed to recognize the USB Blaster unfortunately.) Any other SW suggestions (or "secret unlocks" for JTAG TopProbe) are apprechiated :-) KR Carlhermann
Agilex 5 input termination differential
Hi, After switching from Quartus 24.3.1 (Build 102) to Quartus 25.1.1 (Build 125), I encountered an issue with signal integrity on my hardware. Differential pairs operating at 400 Mbps (_P/_N) are defined as 1.3 V True Differential Signaling with Input Termination – Differential enabled. This configuration works correctly in Quartus 24.3.1. We verified signal integrity using a specialized oscilloscope with a differential probe. As expected, enabling or disabling termination in the Assignment Editor had a significant impact on the signal shape. However, in Quartus 25.1.1, applying the same configuration does not affect signal integrity. The signal appears as if termination is always disabled, regardless of the ON/OFF setting for Input Termination – Differential. Is there a change in how differential I/Os with termination should be defined in Quartus 25.1.1? Or is this a potential issue in the new version? All my assignments show OK status, and there are no warnings related to these settings in the design (Ignored Assignments).
[CycloneV SX] LVDS IO datarate
Hi, I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x So I set up the FPGA outputs to LVDS standard (2.5V), and using the alt_ddio megafunction. The timing constraints for the clock is set to 500MHz. However, the timing analyzer tells me that the maximum achievable datarate is 275MHz. From what I have gathered here, the FPGA should be able to sustain a datarate of 640Mbps only using the softcore. My simple question is : Is the LVDS maximum datarate only achievable when using the LVDS Softcore? Thank you for your answer.Multirate IP FHT Support
Hello I am trying to create a reconfigurable FPGA device using FHT transceivers to generate the highest possible speed PAM4 outputs. I'd like to create a device that can switch between many speeds at the same time, however, the F-Tile PMA and FEC Direct PHY Multirate IP currently does not support FHTs being reconfigured in any way (neither does the dynamic reconfiguration IP). Is there any news about when this feature is to be added? Thanks
DAC Interface Instability After Migrating from MAX7000 to MAX10
Hi all, In one of our legacy designs, we used the MAX7000 (EPM7128AETC100-10N) CPLD. Due to obsolescence, we updated the design to use the MAX10 (10M04SCE144C8G). After the migration, we are observing instability in the DAC interface during operation. Has anyone encountered similar behavior when moving from MAX7000 to MAX10? Are there any known circuit-level differences, I/O characteristics, or design considerations we should account for to ensure stable DAC communication? If we made some correction on RC filter its working, reason is root cause is needed for implementation. Any guidance or insights would be greatly appreciated. Thanks Niranjan. D
Cyclone V Clamping Diode Electrical Specification
Hi, Please provide the below information for the Cyclone V Device IO Banks signals. what is the clamping voltage for the internal diode when enabled. what is the normal protection voltage for IO pin when clamping diode is not enabled. What is the diode used for an Clamping diode, is it an Zenor Diode or TVS Diode or Schottky Diode
