about cyclone 10gx transceiver
Hi, recently I am trying to debug cyclone 10 gx transceivers, and the settings are as the figures above. After reseting, I first send 32'h12345678 as the control world, and set tx_control[1:0] = 2'b10. During this time, in my logic I using rx_bitslip to slip the bits until rx_parallel_data is equal to 32'h12345678. After that, I continually send incremental counter value through transmitter with tx_control[1:0] = 2'b01, but the receiver gets rx_control[1:0] equal to 1, 2, 3, changing all the time, which is shown as following figure. So, did I set parameters wrongly? Or how can l solve it? Thank you.
Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank you
PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit
Hello, I recently got this dev board, and I was trying to load the PCIe example design up on the board however it seems that it is not working, as it fails to enumerate! I followed the instructions on the PDF guide, and I also have my switches set correctly, however it is not working unfortunately! I assume that its an issue with the MAX 10 file, however the only other one I found on the forum is incompatible with my board! I also have the switches set correctly (SW13.1 ON), but any idea or thing helps! Thanks in advance for the help!
Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, BrianHDMI example design errors with Agilex 7
Hello, I generated the HDMI example design for the Agilex 7 devkit and it compiled and worked fine. But when I ported it to my platform and remapped it to the nwe pins, I get these errors (for evenry RX lane and every TX lane): Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx ... Can you please clarify what the issue is? On my new platform, I am using Bank 12A Quad 3 (TX and RX) and for reference clocks fgt_12a_refclk_ch3 and fgt_12a_refclk_ch4. ThanksVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0
Hi, We are working with the following differential clock input pins: - CLK_[T,B]_2[A,B]_[0:1] (P/N) - CLK_[T,B]_3[A,B]_[0:1] (P/N) Could you please confirm the allowed common-mode voltage range for these differential clock inputs?
