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Steve9's avatar
Steve9
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19 days ago

Agilex 7 F/I Series True Differential Input Termination

Hi, 

The Agilex F/I Series GPIO User Guide indicates that if using AC coupling for the true differential inputs you should add external voltage bias circuitry and has no examples of AC coupling without also externally biasing the inputs as shown in snippet below. 

I would like to confirm whether the Agilex 7 F/I series parts have internal voltage biasing such that if AC coupling, external biasing resistors would not be needed so long as VID (max 600mV, so 1200mV differential pk-pk max) is being met? The IBIS model for the part shows a consistent voltage bias for the inputs that is within the VICM range listed in the Agilex 7 F/I series datasheet (see snippet below) which implies the external biasing is not needed. And the AGILEX FM86/FM76 DEVELOPMENT KIT has some differential inputs that are AC coupled with no external biasing. 

 

 

Generic Io

6 Replies

  • FvM's avatar
    FvM
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    19 days ago

    Hi,

    don't agree with your conclusions. There are no indications of internal bias circuit. Datasheet just specifies required voltage levels without mentioning how they are achieved. It's identical to other parts specification that surely miss internal bias. Didn't yet check mentioned dev kit schematic.

    • Steve9's avatar
      Steve9
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      19 days ago

      Ok thanks, I agree datasheet doesn't indicate internal bias. I was basing my comments about internal bias based on the IBIS model seeming to have an internal Bias when the tds12_inp input buffer model is used for the Agilex. But that may just be a difference between what can be inferred from the model and what is the case in reality. I appreciate your response. 

  • FvM's avatar
    FvM
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    19 days ago

    Checked dev kit schematic, I believe it implements AC coupling for transceiver but not LVDS.

    • Steve9's avatar
      Steve9
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      19 days ago

      Thanks. this is the dev kit I was referring to. It looks like the following differential pairs into the FPGA fabric are AC coupled with no external bias. There are bias resistors that are DNI'd on schematic/BOM so they are not installed. What do you think about those? If that was done on the dev kit it made me think AC coupling w/ no bias was acceptable. 

      ToD_MASTER_CLK_125M_P/N

      PTP_SAMPLE_CLK_250M_P/N

      https://www.intel.com/content/www/us/en/content-details/843994/agilex-7-fpga-f-series-development-kit-production-1-2x-f-tile-revd-dk-dev-agf023fa-development-kit-board-schematic.html

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        18 days ago

        Hi Steve,

        reviewing documents and reference design, I agree that GPIO manual, datasheet and development kit schematic are inconsistent in several regards. Looking also at IBIS file, there seems to be a non-linear pull-up feature for TDS input standard which effectively pulls Vicm to about half supply with applied signal. Not sure if IBIS input characteristic is real or roughly simplified.

        So all-in-all, it seems like development kit implementation is a possible minimal effort termination option.

        Regards
        Frank